TPS650231RSBR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 TPS650231 Power Management IC for Li-Ion Powered Systems 1 Features 2 Applications • • • • 1 • • • • • • • • • • • • • • 1.7-A, 90% Efficient Step-Down Converter for Processor Core (VDCDC1) 1.2-A, Up to 95% Efficient Step-Down Converter for System Voltage (VDCDC2) 0.8-A, 92% Efficient Step-Down Converter for Memory Voltage (VDCDC3) 30-mA LDO and Switch for Real-Time Clock (VRTC) 2 × 200-mA General-Purpose LDO Dynamic Voltage Management for Processor Core Preselectable LDO Voltage Using Two Digital Input Pins Externally Adjustable Reset Delay Time Battery Backup Functionality Separate Enable Pins for Inductive Converters I2C™-Compatible Serial Interface 85-μA Quiescent Current Low-Ripple PFM Mode Thermal Shutdown Protection Available in 40-Pin, 5-mm × 5-mm VQFN (RSB) or 49-Ball, 3-mm × 3-mm DSBGA (YFF) Package Smart Phones Netbooks and MIDs Portable Media Players 3 Description The TPS650231 device is an integrated power management IC for applications powered by one Li-Ion or Li-Polymer cell, and which requires multiple power rails. The TPS650231 provides three highly efficient step-down converters targeted at providing the core voltage, peripheral, I/O, and memory rails in a processor-based system. The core converter allows for on-the-fly voltage changes through serial interface, allowing the system to implement dynamic power savings. Device Information(1) PART NUMBER TPS650231 PACKAGE BODY SIZE (NOM) VQFN (40) 5.00 mm × 5.00 mm DSBGA (49) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic TPS6502x Example SoC 2.2 µH Monitored Voltage1 R1 DCDC1 R2 PWRFAIL + ± R4 LOWBATT + ± Monitored Voltage2 R3 CORE 22 µF 2.2 µH 1.8-V IO Domain DCDC2 22 µF 3.3-V IO Domain LDO1 2.2 µF BACKUP RTC AND RESPWRON VBACKUP 2.2 µF System Reset Memory 2.2 µH DCDC3 DCDC1_EN DCDC2_EN DCDC3_EN LDO_EN DEFDCDC1 DEFDCDC2 DEFDCDC3 22 µF Memory Enables and Vout Select LDO1 Peripherals 2.2 µF System Platform 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 1 1 1 2 3 3 7 Absolute Maximum Ratings ..................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 8 Electrical Characteristics........................................... 8 Electrical Characteristics: Control Signals ................ 9 Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3, VINDCDC13............................................................. 10 7.8 Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO......................................... 10 7.9 Electrical Characteristics: VDCDC1 Step-Down Converter ................................................................. 11 7.10 Electrical Characteristics: VDCDC2 Step-Down Converter ................................................................. 11 7.11 Electrical Characteristics: VDCDC3 Step-Down Converter ................................................................. 12 7.12 Timing Requirements ............................................ 13 7.13 Typical Characteristics .......................................... 16 8 Detailed Description ............................................ 21 8.1 8.2 8.3 8.4 8.5 8.6 9 Overview ................................................................. Functional Block Diagrams ..................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 21 22 23 29 30 32 Application and Implementation ........................ 38 9.1 Application Information............................................ 38 9.2 Typical Application ................................................. 40 10 Power Supply Recommendations ..................... 45 10.1 Requirements for Supply Voltages Below 3.0 V ... 45 11 Layout................................................................... 46 11.1 Layout Guidelines ................................................. 46 11.2 Layout Example .................................................... 46 12 Device and Documentation Support ................. 47 12.1 12.2 12.3 12.4 12.5 Device Support...................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 47 47 47 47 47 13 Mechanical, Packaging, and Orderable Information ........................................................... 47 4 Revision History Changes from Original (August 2010) to Revision A • 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 5 Description (continued) All three step-down converters enter a low-power mode at light load for maximum efficiency across the widest possible range of load currents. The TPS650231 also integrates two general-purpose, 200-mA LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage range from 1.5 V to 6.5 V, thus allowing them to be supplied from one of the step-down converters or directly from the battery. The default output voltage of the LDOs can be digitally set to 4 different voltage combinations using the DEFLDO1 and DEFLDO2 pins. The serial interface can be used for dynamic voltage scaling, masking interrupts, or for disabling, enabling, and setting the LDO output voltages. The interface is compatible with the fast and standard mode I2C specifications, allowing transfers at up to 400 kHz. The TPS650231 is available in a 40-pin VQFN (RSB) package or in a 49-ball DSBGA (YFF) package, and operates over a free-air temperature of –40°C to +85°C. 6 Pin Configuration and Functions PWRFAIL DEFDCDC2 PGND2 VDCDC2 L2 VINDCDC2 PWRFAIL_SNS VCC LOWBAT_SNS AGND1 RSB Package 40-Pin VQFN Top View 40 39 38 37 36 35 34 33 32 31 DEFDCDC3 1 30 SCLK VDCDC3 2 29 SDAT 3 28 INT L3 4 27 RESPWRON VINDCDC3 5 26 TRESPWRON VINDCDC1 6 25 DCDC1_EN L1 7 24 DCDC2_EN PGND1 8 23 DCDC3_EN VDCDC1 9 22 LDO_EN 10 21 LOWBAT PGND3 DEFDCDC1 VLDO1 VINLDO VLDO2 VRTC AGND2 VBACKUP VSYSIN DEFLDO1 DEFLDO2 HOT_RESET 11 12 13 14 15 16 17 18 19 20 Pin Functions: TPS650231RSB PIN NAME NO. I/O DESCRIPTION SWITCHING REGULATOR SECTION AGND1 40 — Analog ground. All analog ground pins are connected internally on the chip. AGND2 17 — Analog ground. All analog ground pins are connected internally on the chip. DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 3 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Pin Functions: TPS650231RSB (continued) PIN NAME NO. I/O DESCRIPTION DEFDCDC1 10 I Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V; DEFDCDC1 can also be connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V. DEFDCDC2 32 I Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC2 can also be connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V. DEFDCDC3 1 I Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC3 can also be connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V. L1 7 — Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. L2 35 — Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here. L3 4 — Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here. PGND1 8 — Power ground for VDCDC1 converter PGND2 34 — Power ground for VDCDC2 converter PGND3 3 — Power ground for VDCDC3 converter PowerPAD™ — — Connect the power pad to analog ground. VCC 37 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. VCC also supplies serial interface block. VDCDC1 9 I VDCDC1 feedback voltage sense input. Connect directly to VDCDC1 VDCDC2 33 I VDCDC2 feedback voltage sense input. Connect directly to VDCDC2 VDCDC3 2 I VDCDC3 feedback voltage sense input. Connect directly to VDCDC3 VINDCDC1 6 I Input voltage for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC. VINDCDC2 36 I Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC. VINDCDC3 5 I Input voltage for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC. LDO REGULATOR SECTION DEFLD01 12 I Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2. DEFLD02 13 I Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2. LDO_EN 22 I Enable input for LDO1 and LDO2. A logic high enables the LDOs, a logic low disables the LDOs. VBACKUP 15 I Connect the backup battery to this input pin VINLDO 19 I Input voltage for LDO1 and LDO2 VLDO1 20 O Output voltage of LDO1 VLDO2 18 O Output voltage of LDO2 VRTC 16 O Output voltage of the LDO and switch for the real-time clock VSYSIN 14 I Input of system voltage for VRTC switch 2 CONTROL AND I C SECTION HOT_RESET 11 I Push button input that reboots or wakes up the processor through RESPWRON output pin. INT 28 O Open drain output LOW_BAT 21 O Open drain output of LOW_BAT comparator LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output PWRFAIL 31 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition. PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output RESPWRON 27 O Open drain system reset output SCLK 30 I Serial interface clock line SDAT 29 I/O TRESPWRON 26 I 4 Serial interface data and address Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 YFF Package 49-Pin DSBGA Bottom View VLDO1 VINLDO VLDO2 VBACKUP DEFLDO2 DEFLDO1 VDCDC1 A7 LDO_EN DCDC2_EN AGND VSYSIN PGND1 PGND1 PGND1 A6 DCDC3_EN DCDC1_EN VRTC DEFDCDC1 L1 L1 L1 A5 Trespwron SDAT VDCDC2 Vcc VINDCDC13 VINDCDC13 VINDCDC13 A4 DEFDCDC2 PGND2 L2 VINDCDC2 VDCDC3 L3 VINDCDC13 A3 SCLK PGND2 L2 PWRFAIL _SNS VINDCDC2 PGND3 L3 A2 /PWRFAIL PGND2 G1 L2 F1 VINDCDC2 E1 DEFDCDC3 D1 C1 AGND PGND3 B1 A1 Pin Functions: TPS650231YFF PIN NAME NO. I/O DESCRIPTION SWITCHING REGULATOR SECTION AGND B1, E6 Analog ground. All analog ground pins are connected internally on the chip. DCDC1_EN F5 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. DCDC2_EN F6 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. DCDC3_EN G5 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. DEFDCDC1 D5 I Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V; DEFDCDC1 can also be connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V. DEFDCDC2 G3 I This pin needs to be connected to a resistor divider between VDCDC2 and GND. The output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V. DEFDCDC3 C1 I Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC3 can also be connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V. L1 A5, B5, C5 O Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. L2 E1, E2, E3 O Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here. L3 A2, B3 O Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here. PGND1 A6, B6, C6 Power ground for VDCDC1 converter PGND2 F1, F2, F3 Power ground for VDCDC2 converter PGND3 A1, B2 Power ground for VDCDC3 converter Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 5 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Pin Functions: TPS650231YFF (continued) PIN I/O DESCRIPTION D4 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. VCC must be connected to the same voltage supply as VINDCDC13 and VINDCDC2. VCC also supplies the serial interface block. VDCDC1 A7 I VDCDC1 feedback voltage sense input. Connect directly to VDCDC1 VDCDC2 E4 I VDCDC2 feedback voltage sense input. Connect directly to VDCDC2 VDCDC3 C3 I VDCDC3 feedback voltage sense input. Connect directly to VDCDC3 VINDCDC13 A3, A4, B4, C4 I Input voltage for VDCDC1 and VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC2 and VCC. VINDCDC2 D1, D2, D3 I Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage supply as VINDCDC13 and VCC. NAME NO. VCC LDO REGULATOR SECTION DEFLD01 B7 I Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2. DEFLD02 C7 I Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2. LDO_EN G6 I Enable input for LDO1 and LDO2. A logic high enables the LDOs, a logic low disables the LDOs. VBACKUP D7 I Connect the backup battery to this input pin VINLDO F7 I Input voltage for LDO1 and LDO2 VLDO1 G7 O Output voltage of LDO1 VLDO2 E7 O Output voltage of LDO2 VRTC E5 O Output voltage of the LDO and switch for the real-time clock VSYSIN D6 I Input of system voltage for VRTC switch 2 CONTROL AND I C SECTION PWRFAIL G1 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition. PWRFAIL_SNS C2 I Input for the comparator driving the PWRFAIL output SCLK G2 I Serial interface clock line SDAT F4 I/O TRESPWRON G4 I 6 Serial interface data and address Connect a 1-nF capacitor from this pin to GND Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VI MIN MAX UNIT –0.3 7 V Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 2500 mA Peak current at all other pins 1000 mA 85 °C 125 °C 150 °C Input voltage range on all pins except AGND and PGND pins with respect to AGND TA Operating free-air temperature TJ Junction temperature Tstg Storage temperature (1) –40 –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX Input voltage range step-down converters (VINDCDC1, VINDCDC2, VINDCDC3); pins need to be tied to the same voltage rail 2.5 6 Output voltage range for VDCDC1 step-down converter (1) 0.6 VINDCDC1 (1) 0.6 VINDCDC2 Output voltage range for VDCDC3 step-down converter (1) 0.6 VINDCDC3 VI Input voltage range for LDOs (VINLDO) 1.5 6.5 VO Output voltage range for LDOs (VLDO1, VLDO2) 1 VINLDO1-2 IO(DCDC1) Output current at L1 VCC VO Output voltage range for VDCDC2 step-down converter 1700 Inductor at L1 (2) 1.5 (2) CI(DCDC1) Input capacitor at VINDCDC1 CO(DCDC1) Output capacitor at VDCDC1 (2) IO(DCDC2) Output current at L2 1.5 (2) CI(DCDC2) Input capacitor at VINDCDC2 CO(DCDC2) Output capacitor at VDCDC2 (2) IO(DCDC3) Output current at L3 1.5 CI(DCDC3) Input capacitor at VINDCDC3 (2) 10 CO(DCDC3) Output capacitor at VDCDC3 (2) 10 (2) CI(VCC) Input capacitor at VCC CI(VINLDO) Input capacitor at VINLDO (2) CO(VLDO1-2) Output capacitor at VLDO1, VLDO2 (2) IO(VLDO1-2) Output current at VLDO1, VLDO2 (1) (2) V mA mA μH 2.2 μF μF 22 800 Inductor at L3 (2) V μF 10 10 V μF 22 1200 Inductor at L2 (2) V μH 2.2 10 10 UNIT mA μH 2.2 μF μF 22 1 μF 1 μF μF 2.2 200 mA When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1 See Application Information section for more information Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 7 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) MIN (2) NOM MAX UNIT μF CO(VRTC) Output capacitor at VRTC TA Operating ambient temperature –40 4.7 85 °C TJ Operating junction temperature –40 125 °C 10 Ω Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering (3) (3) 1 Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted accordingly. 7.4 Thermal Information TPS650231 THERMAL METRIC (1) RSB (VQFN) YFF (DSBGA) UNIT 40 PINS 49 BALLS RθJA Junction-to-ambient thermal resistance 32.7 40 °C/W RθJC(top) Junction-to-case (top) thermal resistance 15.3 10 °C/W RθJB Junction-to-board thermal resistance 13.6 15 °C/W ψJT Junction-to-top characterization parameter 0.1 0.1 °C/W ψJB Junction-to-board characterization parameter 5.4 14 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). 7.5 Electrical Characteristics VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VLDO1 AND VLDO2 LOW-DROPOUT REGULATORS VI Input voltage range for LDO1, 2 1.5 6.5 V VO(LD01) LDO1 output voltage range 1 3.15 V VO(LDO2) LDO2 output voltage range 1.05 3.3 V VI = 1.8 V, VO = 1.3 V IO Maximum output current for LDO1, LDO2 I(SC) LDO1 and LDO2 short-circuit current limit 200 VI = 1.5 V, VO = 1.3 V Minimum voltage drop at LDO1, LDO2 mA 120 V(LDO1) = GND, V(LDO2) = GND 400 IO = 50 mA, VINLDO = 1.8 V 120 IO = 50 mA, VINLDO = 1.5 V 65 IO = 200 mA, VINLDO = 1.8 V 150 mA mV 300 Output voltage accuracy for LDO1, LDO2 IO = 10 mA –2% 1% Line regulation for LDO1, LDO2 VINLDO1, 2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5 V, IO = 10 mA –1% 1% Load regulation for LDO1, LDO2 IO = 0 mA to 50 mA –1% Regulation time for LDO1, LDO2 Load change from 10% to 90% 1% μs 10 ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3 VIH High-level input voltage 1.3 VCC VIL Low-level input voltage 0 0.1 V 0.05 μA Input bias current 0.001 V THERMAL SHUTDOWN T(SD) (1) 8 Thermal shutdown Increasing junction temperature 160 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C Typical values are at TA = 25°C Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 Electrical Characteristics (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX –2% 2.35 2% UNIT INTERNAL UNDERVOLTAGE LOCKOUT UVLO Internal UVLO V(UVLO_HYST) Internal UVLO comparator hysteresis VCC falling 120 V mV VOLTAGE DETECTOR COMPARATOR INPUTS PWRFAIL_SNS, LOWBAT_SNS Comparator threshold (PWRFAIL_SNS, LOWBAT_SNS) LOWBAT_SNS for TPS650231RSB only Falling threshold Hysteresis Propagation delay ILK –1% 1 1% V 40 50 60 mV 10 μs 0.001 0.1 μA 25-mV overdrive Input leakage current POWER-GOOD V(PGOODF) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing –12% –10% –8% V(PGOODR) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing –7% –5% –3% 7.6 Electrical Characteristics: Control Signals VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT SCLK, SDAT (INPUT) VIH High level input voltage for the SCLK pin Rpullup at SCLK = 4.7 kΩ, pulled to VRTC; For VCC = 2.5 V to 5.25 V 1.4 VCC V VIH High level input voltage for the SDAT pin Rpullup at SDAT = 4.7 kΩ, pulled to VRTC; For VCC = 2.5 V to 5.25 V 1.69 VCC V VIH High level input voltage for the SDAT pin Rpullup at SDAT = 4.7 kΩ, pulled to VRTC; For VCC = 2.5 V to 4.5 V 1.55 VCC V VIL Low level input voltage Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 0 0.35 V IH Input bias current 0.1 μA V 0.01 HOT_RESET , DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2 VIH High-level input voltage 1.3 VCC VIL Low-level input voltage 0 0.4 V IIB Input bias current 0.01 0.1 μA tdeglitch Deglitch time at HOT_RESET 30 35 ms 6 V 25 LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (OUTPUT) VOH High-level output voltage VOL Low-level output voltage IIL = 5 mA Duration of low pulse at RESPWRON External capacitor 1 nF ICONST Internal charge or discharge current on pin TRESPWRON Used for generating RESPWRON delay 1.7 2 2.3 μA TRESPWRON_LOWTH Internal lower comparator threshold on pin TRESPWRON Used for generating RESPWRON delay 0.225 0.25 0.275 V TRESPWRON_UPTH Internal upper comparator threshold on pin TRESPWRON Used for generating RESPWRON delay 0.97 1 1.103 V Resetpwron threshold VRTC falling –3% 2.4 3% V Resetpwron threshold VRTC rising –3% 2.52 3% V Leakage current Output inactive high 0.001 0.1 μA ILK (1) 0 0.3 100 V ms Typical values are at TA = 25°C Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 9 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 7.7 Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3, VINDCDC13 VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) TYP (1) MAX All 3 DCDC converters enabled, zero load, and no switching, LDOs enabled; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 85 100 All 3 DCDC converters enabled, zero load, and no switching, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 78 90 DCDC1 and DCDC2 converters enabled, zero load, and no switching, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 57 70 DCDC1 converter enabled, zero load, and no switching, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 43 55 All 3 DCDC converters enabled and running in PWM, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 2 3 1.5 2.5 0.85 2 All converters disabled, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 23 33 μA All converters disabled, LDOs off; VCC = 2.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V 3.5 5 μA 43 μA PARAMETER I(q) II Operating quiescent current, PFM Current into VCC; PWM TEST CONDITIONS MIN μA DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V DCDC1 converter enabled and running in PWM, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V I(q) Quiescent current All converters disabled, LDOs off; VCC = 3.6 V, VBACKUP = 0 V; V(VSYSIN) = 0 V I(SD) (1) UNIT mA Shutdown supply current into VINDCDC1 for TPS650231RSB DCDC1_EN = GND 0.1 1 μA Shutdown supply current into VINDCDC2 for TPS650231RSB DCDC2_EN = GND 0.1 1 μA Shutdown supply current into VINDCDC3 for TPS650231RSB DCDC3_EN = GND 0.1 1 μA Shutdown supply current into VINDCDC13 for TPS650231YFF DCDC1_EN = DCDC3_EN = GND 0.2 2 μA Typical values are at TA = 25°C 7.8 Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 20 33 μA 3 μA UNIT VBACKUP, VSYSIN, VRTC I(q) Operating quiescent current VBACKUP = 3 V, VSYSIN = 0 V; VCC = 2.6 V, current into VBACKUP I(SD) Operating quiescent current VBACKUP < V_VBACKUP, current into VBACKUP 2 VRTC LDO output voltage VSYSIN = VBACKUP = 0 V, IO = 0 mA 3 Output current for VRTC VSYSIN < 2.57 V and VBACKUP < 2.57 V 30 mA VRTC short-circuit current limit VRTC = GND; VSYSIN = VBACKUP = 0 V 100 mA Maximum output current at VRTC for RESPWRON = 1 VRTC > 2.6 V, VCC = 3 V; VSYSIN = VBACKUP = 0 V Output voltage accuracy for VRTC VSYSIN = VBACKUP = 0 V; IO = 0 mA –1% 1% Line regulation for VRTC VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA –1% 1% Load regulation VRTC IO = 1 mA to 30 mA; VSYSIN = VBACKUP = 0 V –3% Regulation time for VRTC Load change from 10% to 90% Input leakage current at VSYSIN VSYSIN < V_VSYSIN IO VO Ilkg (1) 10 V 30 mA 1% μs 10 2 μA rDS(on) of VSYSIN switch 12.5 Ω rDS(on) of VBACKUP switch 12.5 Ω Input voltage range at VBACKUP 2.73 3.75 V Input voltage range at VSYSIN 2.73 3.75 V Typical values are at TA = 25°C Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VSYSIN threshold VSYSIN falling –3% 2.55 3% V VSYSIN threshold VSYSIN rising –3% 2.65 3% V VBACKUP threshold VBACKUP falling –3% 2.55 3% V VBACKUP threshold VBACKUP falling –3% 2.65 3% V Operating quiescent current Current per LDO into VINLDO 20 33 μA Shutdown current Total current for both LDOs into VINLDO, VLDO = 0 V 0.1 1 μA VINLDO I(q) I(SD) 7.9 Electrical Characteristics: VDCDC1 Step-Down Converter VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) PARAMETER TEST CONDITIONS VI Input voltage range, VINDCDC1 IO Maximum output current rDS(on) P-channel MOSFET ON-resistance VINDCDC1 (VINDCDC13) = V(GS) = 3.6 V Ilkg P-channel leakage current VINDCDC1 (VINDCDC13) = 6 V rDS(on) N-channel MOSFET ON-resistance VINDCDC1 (VINDCDC13) = V(GS) = 3.6 V Ilkg N-channel leakage current V(DS) = 6 V Forward current limit (P-channel and N-channel) 2.5 V < V(VINDCDC1) < 6 V fS MIN TYP (1) 2.5 MAX 6 1700 Oscillator frequency 125 261 mΩ 2 μA 130 260 mΩ 7 10 μA 1.94 2.19 2.44 A 1.95 2.25 2.55 MHz VINDCDC1 (VINDCDC13) = 2.5 V to 6 V; 0 mA ≤ IO ≤ 1.7 A –2% 2% Fixed output voltage FPWMDCDC1 = 1; all VDCDC1 VINDCDC1 (VINDCDC13) = 2.5 V to 6 V; 0 mA ≤ IO ≤ 1.7 A –1% 1% Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 0 VINDCDC1 (VINDCDC13) = VDCDC1 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.7 A –2% 2% Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 1 VINDCDC1 (VINDCDC13) = VDCDC1 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.7 A –1% 1% Line regulation VINDCDC1 (VINDCDC13) = VDCDC1 + 0.3 V (min 2.5 V) to 6 V; IO = 10 mA 0% V Load regulation IO = 10 mA to 1700 mA tStart Start-up time Time from active EN to start switching 145 175 200 tRamp VOUT ramp-up time 0.25% Time to ramp from 5% to 95% of VOUT 400 750 1000 Internal resistance from L1 to GND (1) V mA Fixed output voltage FPWMDCDC1 = 0; all VDCDC1 VDCDC1 discharge resistance UNIT A 1 DCDC1 discharge = 1 μs μs MΩ Ω 300 Typical values are at TA = 25°C 7.10 Electrical Characteristics: VDCDC2 Step-Down Converter VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) PARAMETER VI TEST CONDITIONS Input voltage range, VINDCDC2 TYP (1) 2.5 VDCDC2 = 1.2V 1200 1000 IO Maximum output current VINDCDC2 = 3.7 V; 3.3 V – 1% ≤ VDCDC2 ≤ 3.3 V + 1% rDS(on) P-channel MOSFET ON-resistance VINDCDC2 = V(GS) = 3.6 V Ilkg P-channel leakage current VINDCDC2 = 6 V rDS(on) N-channel MOSFET ON-resistance VINDCDC2 = V(GS) = 3.6 V (1) MIN MAX 6 UNIT V mA 140 150 300 mΩ 2 μA 297 mΩ Typical values are at TA = 25°C Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 11 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Electrical Characteristics: VDCDC2 Step-Down Converter (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) PARAMETER TEST CONDITIONS TYP (1) MAX 7 10 μA 1.74 1.94 2.12 A 1.95 2.25 2.55 MHz MIN Ilkg N-channel leakage current V(DS) = 6 V ILIMF Forward current limit (P-channel and N-channel) 2.5 V < VINDCDC2 < 6 V fS Oscillator frequency VDCDC2 Adjustable output voltage with resistor divider at DEFDCDC2; FPWMDCDC2 = 0 VINDCDC2 = VDCDC2 + 0.4 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.2 A –2% 2% VDCDC2 Adjustable output voltage with resistor divider at DEFDCDC2; FPWMDCDC2 = 1 VINDCDC2 = VDCDC2 + 0.4 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.2 A –1% 1% Line regulation VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA 0% V Load regulation IO = 10 mA to 1.2 A tStart Start-up time Time from active EN to start switching 145 0.25% 175 200 tRamp VOUT ramp-up time Time to ramp from 5% to 95% of VOUT 400 750 1000 Internal resistance from L2 to GND VDCDC2 discharge resistance A 1 DCDC2 discharge = 1 UNIT µs μs MΩ Ω 300 7.11 Electrical Characteristics: VDCDC3 Step-Down Converter VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) DEFDCDC3 = GND 800 IO Maximum output current VINDCDC3 (VINDCDC13) = 3.6 V; 3.3 V – 1% ≤ VDCDC3 ≤ 3.3 V + 1% 525 rDS(on) P-channel MOSFET ON-resistance VINDCDC3 (VINDCDC13) = V(GS) = 3.6 V 310 698 Ilkg P-channel leakage current VINDCDC3 (VINDCDC13) = 6 V 0.1 2 μA rDS(on) N-channel MOSFET ON-resistance VINDCDC3 (VINDCDC13) = V(GS) = 3.6 V 220 503 mΩ Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA Forward current limit (P-channel and N-channel) 2.5 V < VINDCDC3 (VINDCDC13) < 6 V 1.28 1.49 1.69 A 1.95 2.25 2.55 MHz Oscillator frequency 6 UNIT Input voltage range, VINDCDC3 fS 2.5 MAX VI mA VDCDC3 = 1.8 V; VINDCDC3 (VINDCDC13) = 2.5 V to 6 V; 0 mA ≤ IO ≤ 0.8 A –2% 2% VDCDC3 = 3.3 V; VINDCDC3 (VINDCDC13) = 3.6 V to 6 V; 0 mA ≤ IO ≤ 0.8 A –1% 1% VDCDC3 = 1.8 V; VINDCDC3 (VINDCDC13) = 2.5 V to 6 V; 0 mA ≤ IO ≤ 0.8 A –2% 2% VDCDC3 = 3.3 V; VINDCDC3 (VINDCDC13) = 3.6 V to 6 V; 0 mA ≤ IO ≤ 0.8 A –1% 1% Adjustable output voltage with resistor divider at DEFDCDC3 FPWMDCDC3 = 0 VINDCDC3 (VINDCDC13) = VDCDC3 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 800 mA –2% 2% Adjustable output voltage with resistor divider at DEFDCDC3; FPWMDCDC3 = 1 VINDCDC3 (VINDCDC13) = VDCDC3 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 800 mA –1% 1% Line regulation VINDCDC3 (VINDCDC13) = VDCDC3 + 0.3 V (min 2.5 V) to 6 V; IO = 10 mA Fixed output voltage FPWMDCDC3 = 0 Fixed output voltage FPWMDCDC3 = 1 0% Load regulation IO = 10 mA to 800 mA Start-up time Time from active EN to start switching 145 175 200 tRamp VOUT ramp-up time Time to ramp from 5% to 95% of VOUT 400 750 1000 VDCDC3 discharge resistance (1) 12 0.25% 1 DCDC3 discharge = 1 300 mΩ V tStart Internal resistance from L3 to GND V A µs μs MΩ Ω Typical values are at TA = 25°C Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 7.12 Timing Requirements Operating conditions: VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 2.5 V to 5.5 V, VBACKUP = 3.0 V, TA = –40°C to +85°C MIN MAX UNIT 400 kHz fMAX Clock frequency twH(HIGH) Clock high time 600 twL(LOW) Clock low time 1300 tR DATA and CLK rise time 300 ns tF DATA and CLK fall time 300 ns th(STA) Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns tsu(DATA) Setup time for repeated START condition 600 ns th(DATA) Data input hold time 100 ns tsu(DATA) Data input setup time 100 ns tsu(STO) STOP condition setup time 600 ns t(BUF) Bus free time 1300 ns ns ns DATA t(BUF) th(STA) t(LOW) tf tr CLK th(STA) t(HIGH) tsu(STA) th(DATA) STO tsu(STO) tsu(DATA) STA STA STO Figure 1. Serial I/F Timing Diagram Figure 2. HOT_RESET Timing (TPS650231RSB Only) Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 13 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 VCC www.ti.com 2.35V 1.9V 1.2V 2.47V 1.9V 0.8V UVLO* VRTC 2.52V 2.4V 3.0V RESPWRON tNRESPWRON DCDCx_EN Ramp within 800 μs VO DCDCx slope depending on load LDO_EN VO LDOx *... internal signal VSYSIN=VBACKUP=GND; VINLDO=VCC Figure 3. Power-Up and Power-Down Timing 14 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 Figure 4. DVS Timing Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 15 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 7.13 Typical Characteristics Table 1. Table of Graphs FIGURE η Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 Efficiency vs Output current Output voltage vs Output current at 85°C Figure 11, Figure 12 Line transient response Figure 13, Figure 14, Figure 15 Load transient response Figure 16, Figure 17, Figure 18 VDCDC2 PFM operation Figure 19 VDCDC2 low-ripple PFM operation Figure 20 VDCDC2 PWM operation Figure 21 Start-up VDCDC1, VDCDC2 and VDCDC3 Figure 22 Start-up LDO1 and LDO2 Figure 23 Line transient response Figure 24, Figure 25, Figure 26 Load transient response Figure 27, Figure 28, Figure 29 100 100 VI = 2.5 V 90 90 VI = 3 V 80 80 VI = 4.2 V 60 VI = 5 V 50 40 30 50 VI = 4.2 V 40 VI = 5 V 20 TA = 25°C, VO = 1.2 V, PFM Mode 10 0 0.01 0.1 1 10 100 1k IO - Output Current - mA 10 0 0.01 10 k 100 100 VI = 3 V 90 90 80 80 VI = 3.6 V 70 VI = 2.5 V Efficiency - % VI = 5 V 50 40 30 1 10 100 1k IO - Output Current - mA TA = 25°C, VO = 1.8 V, PWM Mode 70 VI = 4.2 V 60 0.1 10 k Figure 6. DCDC1: Efficiency vs Output Current Figure 5. DCDC1: Efficiency vs Output Current Efficiency - % VI = 3.6 V 60 30 20 VI = 2.5 V VI = 3 V 60 VI = 3.6 V 50 VI = 4.2 V 40 VI = 5 V 30 TA = 25°C, VO = 1.8 V, PFM Mode 20 10 0 0.01 0.1 1 10 100 1k IO - Output Current - mA 20 10 10 k Figure 7. DCDC2: Efficiency vs Output Current 16 VI = 2.5 V VI = 3 V 70 Efficiency - % Efficiency - % 70 VI = 3.6 V TA = 25°C, VO = 1.2 V, PWM Mode 0 0.01 0.1 1 10 100 1k IO - Output Current - mA 10 k Figure 8. DCDC2: Efficiency vs Output Current Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 100 100 90 80 VI = 3 V 70 70 VI = 3.6 V 60 Efficiency - % Efficiency - % TA = 25°C, 90 V = 1.8 V, O PWM Mode 80 VI = 2.5 V VI = 4.2 V VI = 5 V 50 40 VI = 3 V VI = 3.6 V 60 VI = 4.2 V 50 VI = 5 V 40 30 30 20 20 TA = 25°C, VO = 1.8 V, PFM Mode 10 0 0.01 0.1 1 10 100 1k IO - Output Current - mA 10 0 0.01 10 k Figure 9. DCDC3: Efficiency vs Output Current 0.1 1 10 100 1k IO - Output Current - mA 10 k Figure 10. DCDC3: Efficiency vs Output Current 3.3 3.4 TA = 85°C DEFDCDC3 = VINDCDC3 VI = 3.8 V 3.35 3.267 VI = 3.7 V VO - Output Voltage - V VO - Output Voltage - V VI = 2.5 V 3.234 VI = 3.5 V 3.201 VI = 3.6 V VI = 3.8 V 3.3 VI = 3.7 V 3.25 3.2 VI = 3.5 V 3.168 3.15 TA = 85°C DEFDCDC2 = VINDCDC2 3.135 0.1 1 IO - Output Current - A 10 3.1 0.1 Figure 11. DCDC2: Output Voltage vs Output Current at 85°C VI = 3.7 V to 4.7 V VO = 1.2 V, IO = 100 mA DEFDCDC1 = GND PWM Mode VI = 3.6 V 1 IO - Output Current - A 10 Figure 12. DCDC3: Output Voltage vs Output Current at 85°C C1 High 4.72 V C1 High 4.02 V C1 Low 3.72 V C1 Low 3.02 V C2 Pk-Pk 24.7 mV VI = 3 V to 4 V, VO = 1.8 V, IO = 100 mA; DEFDCDC2 = resistor divider; set for VO = 1.8 V, PWM Mode C2 Mean 1.20701 V Figure 13. VDCDC1 Line Transient Response C2 Pk-Pk 128 mV C2 Mean 1.8002 V Figure 14. VDCDC2 Line Transient Response Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 17 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com VI = 3.6 V to 4.6 V, VO = 3.3 V, IO = 100 mA, DEFDCDC1 = VINDCDC3, PWM Mode C1 High 4.62 V C4 High 1.56 A C1 Low 3.62 V C4 Low 120 mA VI = 3.8 V, VO = 1.2 V, IO = 170 mA to 1530 mA C2 Pk-Pk 91 mV C2 Pk-Pk 166 mV C2 Mean 3.2993 V C2 Mean 1.2046 V Figure 15. VDCDC3 Line Transient Response C4 High 1.12 A Figure 16. VDCDC1 Load Transient Response VI = 3.8 V, VO = 3.3 V, IO = 120 mA to 720 mA C4 High 720 mA C4 Low 80 mA C4 Low 80 mA C2 Pk-Pk 147 mV C2 Pk-Pk 194 mV VI = 3.8 V, VO = 1.8 V, IO = 120 mA to 1080 mA C2 Mean 3.2961 V C2 Mean 1.7993 V Figure 17. VDCDC2 Load Transient Response Figure 18. VDCDC3 Load Transient Response VI = 3.8 V, VO = 1.8 V, ILOAD = 1 mA; PFM Mode C2 Pk-Pk 20.6 mV C2 Mean 1.81186 V Figure 19. VDCDC2 Output Voltage Ripple 18 Figure 20. VDCDC2 Output Voltage Ripple Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 mV Figure 21. VDCDC2 Output Voltage Ripple Figure 22. Start-Up VDCDC1, VDCDC2, and VDCDC3 ENABLE C1 High 3.82 V VCC = 3.8 V, VI LDO = 3.3 V to 3.8 V VO = 2.1 V, IO = 25 mA LDO1 C1 Low 3.29 V C2 Pk-Pk 4.2 mV C2 Mean 2.10252 V LDO2 Figure 24. LDO1 Line Transient Response Figure 23. Start-Up LDO1 and LDO2 Ch1 = VI Ch2 = VO IO = 25 mA VO = 3.3 V TA = 25oC C1 High 4.51 V Ch1 = VI Ch2 = VO IO = 10 mA VO = 3 V o TA = 25 C C1 High 3.82 V C1 Low 3.99 V C1 Low 3.28 V C2 PK-PK 6.1 mV C2 PK-PK 22.8 mV C2 Mean 3.29828 V C2 Mean 2.98454 V Figure 25. LDO2 Line Transient Response Figure 26. VRTC Line Transient Response Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 19 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com VCC = 3.8 V, VI = 3.3 V, VO = 2.1 V, IO = 20 mA to 180 mA C4 High 184 mA C4 High 180 mA C4 Low 16 mA C4 Low 16 mA C2 Pk-Pk 53.1 mV C2 Pk-Pk 78.1 mV C2 Mean 2.10024 V C2 Mean 3.29606 V VCC = 3.8 V, VI = 3.8 V, VO = 3.3 V, IO = 20 mA to 180 mA Figure 27. LDO1 Load Transient Response Figure 28. LDO2 Load Transient Response C4 High 21.4 mA C4 Low -1.4 mA C2 PK-PK 76 mV C2 Mean 2.9762 V Ch2 = VO Ch4 = IO VI = 3.8 V VO = 3 V o TA = 25 C Figure 29. VRTC Load Transient Response 20 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 8 Detailed Description 8.1 Overview TPS650231 has 5 regulator channels, 3 DCDCs and 2 LDOs. DCDC3 has dynamic voltage scaling feature, DVS, that allows for power reduction to CORE supplies during idle operation or over voltage during heavy-duty operation. With DVS and 2 more DCDCs plus 2 LDOs, the TPS650231 is ideal for CORE, Memory, IO, and peripheral power for the entire system of a wide range of suitable applications. The device incorporates enables for the DCDCs and LDOs, I2C for device control, push-button and a reset interface that complete the system and allow for the TPS650231 to be adapted for different kinds of processors or FPGAs. For noise-sensitive circuits, the DCDCs can be synchronized out of phase from one another, reducing the peak noise at the switching frequency. Each converter can be forced to operate in PWM mode to ensure constant switching frequency across the entire load range. However, for low-load efficiency performance the DCDCs automatically enter PSM mode which reduces the switching frequency when the load current is low, saving power at idle operation. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 21 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 8.2 Functional Block Diagrams VCC VSYSIN VBACKUP VRTC TPS650231RSB BBAT SWITCH Thermal Shutdown VINDCDC1 L1 DCDC1 Buck Converter 1700 mA SCLK SDAT VDCDC1 DEFDCDC1 PGND1 Serial Interface VINDCDC2 DCDC1_EN L2 DCDC2_EN DCDC2 Buck Converter 1200 mA DCDC3_EN LDO_EN CONTROL VDCDC2 DEFDCDC2 PGND2 HOT_RESET Dynamic Voltage Management RESPWRON INT VINDCDC3 L3 LOWBAT_SNS PWRFAIL_SNS LOW_BATT PWRFAIL DCDC3 Buck Converter 1000 mA UVLO VREF OSC VDCDC3 DEFDCDC3 PGND3 TRESPWRON LDO1 200 mA DEFLDO1 DEFLDO2 VLDO1 VINLDO LDO2 200 mA VLDO2 AGND1 AGND2 Figure 30. TPS650231 VQFN Package 22 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 Functional Block Diagrams (continued) VSYSIN THERMAL SHUTDOWN VCC VBACKUP DCDC3 STEP -DOWN CONVERTER BBAT SWITCH VRTC SCLK STEP-DOWN CONVERTER Serial Interface DCDC2 CONTROL L2 VDCDC2 DEFDCDC2 STEP-DOWN CONVERTER Dynamic Voltage Scaling /PWRFAlL L1 VDCDC1 DEFDCDC1 PGND1 VINDCDC2 DCDC1_EN DCDC2_EN DCDC3_EN LDO _ EN PWRFAIL_ SNS PGND3 VINDCDC13 DCDC1 SDAT L3 VDCDC3 DEFDCDC3 PGND2 VLDO1 UVLO VREF OSC VLDO1 200 mA LDO TRESPWRON AGND VINLDO DEFLDO1 VLDO2 DEFLDO2 VLDO2 200 mA LDO Figure 31. TPS650231 DSBGA Package 8.3 Feature Description 8.3.1 VRTC Output and Operation With or Without Backup Battery The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail (that is, for a real-time clock). The TPS650231 asserts the RESPWRON signal if VRTC drops below 2.4 V. VRTC is selected from a priority scheme based on the VSYSIN and VBACKUP inputs. When the voltage at the VSYSIN pin exceeds 2.65 V, VRTC connects to the VSYSIN input through a PMOS switch and all other paths to VRTC are disabled. The PMOS switch drops a maximum of 375 mV at 30-mA, which must be considered when using VRTC. VSYSIN can be connected to any voltage source with the appropriate input voltage, including VCC or, if set to 3.3-V output, DCDC2 or DCDC3. When VSYSIN falls below 2.65 V or shorts to ground, the PMOS switch connecting VRTC and VSYSIN opens and VRTC then connects to either VBACKUP or the output of a dedicated 3-V or 30-mA LDO. Texas Instruments recommends connecting VSYSIN to VCC or ground, connecting VCC if a non-replaceable primary cell is connected to VBACKUP and ground if the VRTC output floats. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 23 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) If the PMOS switch between VSYSIN and VRTC is open and VBACKUP exceeds 2.65 V, VRTC connects to VBACKUP through a PMOS switch. The PMOS switch drops a maximum of 375 mV at 30 mA, which must be considered if using VRTC. A typical application may connect VBACKUP to a primary Li button cell, but any battery that provides a voltage between 2.65 V and 6 V (that is, a single Li-Ion cell or a single boosted NiMH battery) is acceptable, to supply the VRTC output. NOTE In systems with no backup battery, the VBACKUP pin must be connected to GND. If the switches between VRTC and VSYSIN or VBACKUP are open, the dedicated 3-V or 30-mA LDO, driven from VCC, connects to VRTC. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V. Inside TPS650231 there is a switch (Vmax switch) which selects the higher voltage between VCC and VBACKUP. This is used as the supply voltage for some basic functions. The functions powered from the output of the Vmax switch are: • INT output • RESPWRON output • HOT_RESET input • LOW_BATT output • PWRFAIL output • Enable pins for DC-DC converters, LDO1 and LDO2 • Undervoltage lockout comparator (UVLO) • Reference system with low-frequency timing oscillators • LOW_BATT and PWRFAIL comparators The main 2.25-MHz oscillator, and the I2C interface are only powered from VCC. spacer VSYSIN Vref V_VSYSIN priority #1 VCC VBACKUP Vref V_VBACKUP priority #2 V_VSYSIN V_VBACKUP EN VRTC LDO priority #3 VRTC RESPWRON Vref A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3% B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3% Figure 32. RTC and RESPWRON 24 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 Feature Description (continued) 8.3.2 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3 The TPS650231 incorporates three synchronous step-down converters operating typically at 2.25-MHz fixedfrequency pulse width modulation (PWM) at moderate to heavy-load currents. At light-load currents the converters automatically enter power save mode and operate with pulse frequency modulation (PFM). The VDCDC1 converter is capable of delivering 1.7-A output current, the VDCDC2 converter is capable of delivering 1.2-A, and the VDCDC3 converter delivers up to 800 mA. The converter output voltages can be programmed through the DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins. For DEFDCDC1 and DEFDCDC3, the pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The VDCDC1 converter defaults to 1.2 V or 1.6 V depending on the DEFDCDC1 configuration pin, if DEFDCDC1 is tied to ground the default is 1.2 V, if it is tied to VCC the default is 1.6 V. When the DEFDCDC1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See Application Information for more details. The core voltage can be reprogrammed through the serial interface in the range of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst any programmed voltage change is underway, whether the voltage is being increased or decreased. The DEFCORE and DEFSLEW registers are used to program the output voltage and slew rate during voltage transitions. The DEFDCDC2 pin does not have the logic function in parallel and always needs to be connected with a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V. The VDCDC3 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC3 configuration pin. If DEFDCDC3 is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC3 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V. The stepdown converter outputs (when enabled) are monitored by power-good comparators, the outputs of which are available through the serial interface. The outputs of the DC-DC converters can be optionally discharged through on-chip 300-Ω resistors when the DC-DC converters are disabled. During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feedforward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the adaptive dead-time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch. The three DC-DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A 180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3 switch turn on decreases the input RMS current and smaller input capacitors can be used. The phase of the three converters can be changed using the CON_CTRL register. 8.3.3 Power Save Mode Operation As the load current decreases, the converters enter the power save mode operation. During power save mode, the converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 2.25 MHz, nominal for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 25 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) To optimize the converter efficiency at light load, the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM is calculated with Equation 1, Equation 2, and Equation 3. VINDCDC1 IPFMDCDC1 enter = (1) 24 Ω VINDCDC2 IPFMDCDC2 enter = 26 Ω (2) VINDCDC3 IPFMDCDC3 enter = 39 W (3) During the power save mode the output voltage is monitored with a comparator, and by maximum skip burst width. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter effectively delivers a constant current defined with Equation 4, Equation 5, and Equation 6. VINDCDC1 IPFMDCDC1 leave = 18 W (4) VINDCDC2 IPFMDCDC2 leave = 20 W (5) VINDCDC3 IPFMDCDC3 leave = 29 W (6) If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode if either of the following conditions are met: 1. the output voltage drops 2% below the nominal VO due to increasing load current 2. the PFM burst time exceeds 16 × 1 / fs (7.11 μs typical). These control methods reduce the quiescent current to typically 14 μA per converter, and the switching activity to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light-load current results in a low-output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The PSM is disabled through the I2C interface to force the individual converters to stay in fixed-frequency PWM mode. 8.3.4 Low-Ripple Mode Setting bit 3 in register CON-CTRL to 1 enables the low-ripple mode for all of the DC-DC converters if operated in PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is reduced, depending on the actual load current. The lower the actual output current on the converter, the lower the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage ripple between PFM mode and low-ripple PFM mode. As this feature also increases switching frequency, it is used to keep the switching frequency above the audible range in PFM mode down to a low-output current. 8.3.5 Soft-Start Each of the three converters has an internal soft-start circuit that limits the inrush current during start-up. The soft-start is realized by using a low current to initially charge the internal compensation capacitor. The soft-start time is typically 750 μs if the output voltage ramps from 5% to 95% of the final target value. If the output is already precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a short delay of typically 170 μs between the converter being enabled and switching activity actually starting. This allows the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent discharging of the output while the internal soft-start ramp catches up with the output voltage. 26 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 Feature Description (continued) 8.3.6 100% Duty Cycle Low-Dropout Operation The TPS650231 converters offer a low input-to-output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load current and output voltage. It is calculated in Equation 7. Vin min + Vout min ) Iout max ǒrDS(on) max ) RLǓ where • • • • Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions) rDS(on)max = maximum P-channel switch rDS(on) RL = DC resistance of the inductor Voutmin = nominal output voltage minus 2% tolerance limit (7) 8.3.7 Active Discharge When Disabled When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN, or OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled through the CON_CTRL2 register in the serial interface. When this feature is enabled, the VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300-Ω (typical) load which is active as long as the converters are disabled. 8.3.8 Power-Good Monitoring All three step-down converters and both the LDO1 and LDO2 linear regulators have power-good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5% hysteresis. The outputs of these comparators are available in the PGOODZ register through the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are disabled and the relevant PGOODZ register bits indicate that power is good. 8.3.9 Low-Dropout Voltage Regulators The low-dropout voltage regulators are designed to operate well with low-value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the LDO_EN pin, both LDOs can be disabled or programmed through the serial interface using the REG_CTRL and LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect external regulators in parallel in systems with a backup battery. The TPS650231 step-down and LDO voltage regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the junction temperature rises above 160°C. 8.3.10 Undervoltage Lockout The undervoltage lockout circuit for the five regulators on the TPS650231 prevents the device from malfunctioning at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Consider this current if an external RC filter is used at the VCC pin to remove switching noise from the TPS650231 internal analog circuitry supply. NOTE When any of the DC-DC converters are running, there is an input current at the VCC pin, which is up to 3 mA when all three converters are running in PWM mode. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 27 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) 8.3.11 Power-Up Sequencing The TPS650231 power-up sequencing is designed to be entirely flexible and customer-driven. This is achieved by providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The relevant control pins are described in Table 2. Table 2. Control Pins and Status Outputs for DC-DC Converters PIN NAME I/O FUNCTION DEFDCDC3 I Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.8 V, DEFDCDC3 = VCC defaults VDCDC3 to 3.3 V. DEFDCDC2 I Feedback pin of the VDCDC2 switching converter, connected to a resistive divider. The output voltage can be set between 0.6 V and VINDCDC2 V. DEFDCDC1 I Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 1.2 V, DEFDCDC1 = VCC defaults VDCDC1 to 1.6 V. DCDC3_EN I Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter DCDC2_EN I Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter DCDC1_EN I Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter HOT_RESET I TPS650231RSB only: The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any TPS650231 settings except the output voltage of VDCDC1. Activating HOT_RESET sets the voltage of VDCDC1 to its default value defined with the DEFDCDC1 pin. HOT_RESET is internally de-bounced by the TPS650231. RESPWRON O TPS650231RSB only: RESPWRON is held low when power is initially applied to the TPS650231. The VRTC voltage is monitored: RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin. TRESPWRON I Connect a capacitor here to define the RESET time at the RESPWRON pin (1 nF typically gives 100 ms). 8.3.12 System Reset + Control Signals The RESPWRON signal can be used as a global reset for the application. It is an open-drain output. The RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms. The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and LOWBAT_SNS input signals. Each input signal is compared to a 1-V threshold (falling edge) with 5% (50 mV) hysteresis. The DCDC1 converter is reset to its default output voltage defined by the DEFDCDC1 input, when HOT_RESET is asserted. Other I2C registers are not affected. Generally, the DCDC1 converter is set to its default voltage with one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout (UVLO) condition, or RESPWRON active. The RESPWRON, HOT_RESET, LOW_BAT, and LOWBAT_SNS pins are not available in TPS650231YFF. 8.3.12.1 DEFLDO1 and DEFLDO2 These two pins are used to set the default output voltage of the two 200-mA LDOs. The digital value applied to the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of both LDOs can be changed during operation with the I2C interface as described in the interface description. Table 3. LDO1 and LDO2 Default Voltage Options 28 DEFLDO2 DEFLDO1 VLDO1 VLDO2 0 0 1.3 V 3.3 V 0 1 2.8 V 3.3 V 1 0 1.3 V 1.8 V 1 1 2.1 V 3.3 V Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 8.3.12.2 Interrupt Management and the INT Pin The INT pin combines the outputs of the PGOOD comparators from each DC-DC converter and the LDOs. The INT pin is used as a POWER_OK pin to indicate when all enabled supplies are in regulation. The INT pin remains active (low state) during power up as long as all enabled power rails are below their regulation limit. When the last enabled power rail is within regulation, the INT pin transitions to a high state. During operation, if one of the enabled supplies goes out of regulation, INT transitions to a low state, and the corresponding bit in the PGOODZ register goes high. If the supply goes back to its regulation limits, INT transitions back to a high state. While INT is in an active-low state, reading the PGOODZ register through the I2C bus forces INT into a high-Z state. Because this pin requires an external pullup resistor, the INT pin transitions to a logic high state even though the supply in question is still out of regulation. The corresponding bit in the PGOODZ register still indicates that the power rail is out of regulation. Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO interrupts because this provides the POWER_OK function. If none of the DCDC converters or LDOs are enabled, /INT defaults to a low state independently of the settings of the MASK register. 8.4 Device Functional Modes The TPS650231 device is in the ON or the OFF mode. The OFF mode is entered when the voltage on VCC is below the UVLO threshold, 2.35 V (typically). When the voltage at VCC has increased above UVLO, the device enters ON mode. In the ON mode, the DCDCs and LDOs are available for use. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 29 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 8.5 Programming 8.5.1 Serial Interface The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS650231 has a 7-bit address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from the register addresses not listed in this section results in FFh being read out. For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS650231 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS650231 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS650231 device must leave the data line high to enable the master to generate the stop condition DATA CLK Data Line Stable; Data Valid Change of Data Allowed Figure 33. Bit Transfer on the Serial Interface CE DATA CLK S P START Condition STOP Condition Figure 34. START and STOP Conditions 30 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 Programming (continued) SCLK SDAT A6 A5 A0 A4 ACK R/W R5 R0 0 0 Start R6 R7 ACK D5 D6 D7 D0 ACK 0 0 Register Address Slave Address Stop Data Note: SLAVE = TPS650231 Figure 35. Serial I/F WRITE to TPS650231 Device SCLK SDAT A6 Start A0 R/W ACK 0 0 R7 R0 A6 ACK A0 R/W ACK 1 0 0 Register Address Slave Address D0 D7 ACK Slave Drives the Data Slave Address Stop Master Drives ACK and Stop Repeated Start Note: SLAVE = TPS650231 Figure 36. Serial I/F READ from TPS650231: Protocol A SCLK SDA A6 A0 R/W ACK 0 Start R7 R0 0 Slave Address 0 Register Address A6 ACK A0 R/W ACK D0 ACK 0 1 Stop Start D7 Slave Address Slave Drives the Data Stop Master Drives ACK and Stop Note: SLAVE = TPS650231 Figure 37. Serial I/F READ from TPS650231: Protocol B Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 31 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 8.6 Register Maps 8.6.1 VERSION Register Address: 00h (Read Only) Table 4. VERSION Register VERSION B7 B6 B5 B4 B3 B2 B1 B0 Bit name and function 0 0 1 0 0 0 1 1 Read/write R R R R R R R R 8.6.2 PGOODZ Register Address: 01h (Read Only) Table 5. PGOODZ Register PGOODZ B7 B6 B5 B4 B3 B2 B1 B0 PWRFAILZ LOWBATTZ PGOODZ VDCDC1 PGOODZ VDCDC2 PGOODZ VDCDC3 PGOODZ LDO2 PGOODZ LDO1 – Set by signal PWRFAIL LOWBATT PGOODZ VDCDC1 PGOODZ VDCDC2 PGOODZ VDCDC3 PGOODZ LDO2 PGOODZ LDO1 – Default value loaded PWRFAILZ LOWBATTZ PGOOD VDCDC1 PGOOD VDCDC2 PGOOD VDCDC3 PGOOD LDO2 PGOOD LDO1 – R R R R R R R R Bit name and function Read/write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 32 PWRFAILZ: 0= indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold. 1= indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold. LOWBATTZ: 0= indicates that the LOWBATT_SNS input voltage is above the 1-V threshold. 1= indicates that the LOWBATT_SNS input voltage is below the 1-V threshold. PGOODZ VDCDC1: 0= indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if the VDCDC1 converter is disabled. 1= indicates that the VDCDC1 converter output voltage is below its target regulation voltage PGOODZ VDCDC2: 0= indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if the VDCDC2 converter is disabled. 1= indicates that the VDCDC2 converter output voltage is below its target regulation voltage PGOODZ VDCDC3: 0= indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if the VDCDC3 converter is disabled and during a DVM controlled output voltage transition 1= indicates that the VDCDC3 converter output voltage is below its target regulation voltage PGOODZ LDO2: 0= indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is disabled. 1= indicates that LDO2 output voltage is below its target regulation voltage PGOODZ LDO1: 0= indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is disabled. 1= indicates that the LDO1 output voltage is below its target regulation voltage Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 8.6.3 MASK Register Address: 02h (Read or Write), Default Value: C0h Table 6. MASK Register MASK Bit name and function Default Default value loaded Read/write B7 B6 B5 B4 B3 B2 B1 B0 MASK PWRFAILZ MASK LOWBATTZ MASK VDCDC1 MASK VDCDC2 MASK VDCDC3 MASK LDO2 MASK LDO1 – 1 1 0 0 0 0 0 0 UVLO UVLO UVLO UVLO UVLO UVLO UVLO – R/W R/W R/W R/W R/W R/W R/W – The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK = 1 masks PGOODZ. 8.6.4 REG_CTRL Register Address: 03h (Read or Write), Default Value: FFh The REG_CTRL register is used to disable or enable the power supplies through the serial interface. The contents of the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The REG_CTRL bits are automatically reset to default when the corresponding enable pin is low. Table 7. REG_CTRL Register REG_CTRL B7 B6 B5 B4 B3 B2 B1 B0 Bit name and function – – VDCDC1 ENABLE VDCDC2 ENABLE VDCDC3 ENABLE LDO2 ENABLE LDO1 ENABLE – Default 1 1 1 1 1 Set by signal – – Default value loaded – – UVLO UVLO Read/write – – R/W R/W Bit 5 1 1 1 LDO_ENZ LDO_ENZ – UVLO UVLO UVLO – R/W R/W R/W – DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ VDCDC1 ENABLE DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when DCDC1_EN returns high. Bit 4 VDCDC2 ENABLE DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when DCDC2_EN returns high. Bit 3 VDCDC3 ENABLE DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when DCDC3_EN returns high. Bit 2 LDO2 ENABLE LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high. Bit 1 LDO1 ENABLE Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 33 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high. 8.6.5 CON_CTRL Register Address: 04h (Read or Write), Default Value: B1h Table 8. CON_CTRL Register CON_CTRL B7 B6 B5 B4 B3 B2 B1 B0 Bit name and function DCDC2 PHASE1 DCDC2 PHASE0 DCDC3 PHASE1 DCDC3 PHASE0 LOW RIPPLE FPWM DCDC2 FPWM DCDC1 FPWM DCDC3 1 0 1 1 0 0 0 0 UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO R/W R/W R/W R/W R/W R/W R/W R/W Default Default value loaded Read/write The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when lowoutput voltage ripple is vital. It is also used to control the phase shift between the three converters to minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is taken as the reference and consequently has a fixed zero phase shift. Table 9. DCDC2 and DCDC3 Phase Delay DCDC2 CONVERTER DELAYED BY CON_CTRL 00 zero 00 zero 01 1/4 cycle 01 1/4 cycle 10 1/2 cycle 10 1/2 cycle 11 3/4 cycle 11 3/4 cycle CON_CTRL Bit 3 Bit 2 Bit 1 Bit 0 34 DCDC3 CONVERTER DELAYED BY LOW RIPPLE: 0= PFM mode operation optimized for high efficiency for all converters 1= PFM mode operation optimized for low-output voltage ripple for all converters FPWM DCDC2: 0= DCDC2 converter operates in PWM or PFM mode 1= DCDC2 converter is forced into fixed-frequency PWM mode FPWM DCDC1: 0= DCDC1 converter operates in PWM or PFM mode 1= DCDC1 converter is forced into fixed-frequency PWM mode FPWM DCDC3: 0= DCDC3 converter operates in PWM or PFM mode 1= DCDC3 converter is forced into fixed-frequency PWM mode Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 8.6.6 CON_CTRL2 Register Address: 05h (Read or Write), Default Value: 40h Table 10. CON_CTRL2 Register CON_CTRL2 B7 B6 B5 B4 B3 B2 B1 B0 Bit name and function GO Core adj allowed – – – DCDC2 discharge DCDC1 discharge DCDC3 discharge 0 1 0 0 0 0 0 0 UVLO + DONE RESET(1) – – – UVLO UVLO UVLO R/W R/W – – – R/W R/W R/W Default Default value loaded Read/write The CON_CTRL2 register can be used to take control the inductive converters. • • • • RESET(1): CON_CTRL2[6] is reset to its default value by one of these events: Undervoltage lockout (UVLO) HOT_RESET pulled low RESPWRON active VRTC below threshold Bit 7 Bit 6 Bit 2– 0 GO: 0= no change in the output voltage for the DCDC1 converter 1= the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is complete. The transition is considered complete in this case when the desired output voltage code has been reached, not when the VDCDC1 output voltage is actually in regulation at the desired voltage. CORE ADJ Allowed: 0= the output voltage is set with the I2C register 1= DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V respectively at start-up 0= the output capacitor of the associated converter is not actively discharged when the converter is disabled 1= the output capacitor of the associated converter is actively discharged when the converter is disabled. This decreases the fall time of the output voltage at light load Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 35 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 8.6.7 DEFCORE Register Address: 06h (Read or Write), Default Value: 14h/1Eh Table 11. DEFCORE Register DEFCORE B7 B6 B5 B4 B3 B2 B1 B0 Bit name and function – – – CORE4 CORE3 CORE2 CORE1 CORE0 Default 0 0 0 1 DEFDCDC1 DEFDCDC1 DEFDCDC1 DEFDCDC1 Default value loaded – – – RESET(1) RESET(1) RESET(1) RESET(1) RESET(1) Read/write – – – R/W R/W R/W R/W R/W RESET(1): DEFCORE is reset to its default value by one of these events: • Undervoltage lockout (UVLO) • HOT_RESET pulled low • RESPWRON active • VRTC below threshold Table 12. DCDC1 DVS Voltages CORE4 CORE3 36 CORE2 CORE1 CORE0 VDCDC1 CORE4 CORE3 CORE2 CORE1 CORE0 0 0 0 0 0 0.8 V 1 0 0 0 0 1.2 V 0 0 0 0 1 0.825 V 1 0 0 0 1 1.225 V 0 0 0 1 0 0.85 V 1 0 0 1 0 1.25 V 0 0 0 1 1 0.875 V 1 0 0 1 1 1.275 V 0 0 1 0 0 0.9 V 1 0 1 0 0 1.3 V 0 0 1 0 1 0.925 V 1 0 1 0 1 1.325 V 0 0 1 1 0 0.95 V 1 0 1 1 0 1.35 V 0 0 1 1 1 0.975 V 1 0 1 1 1 1.375 V 0 1 0 0 0 1V 1 1 0 0 0 1.4 V 0 1 0 0 1 1.025 V 1 1 0 0 1 1.425 V 0 1 0 1 0 1.05 V 1 1 0 1 0 1.45 V 0 1 0 1 1 1.075 V 1 1 0 1 1 1.475 V 0 1 1 0 0 1.1 V 1 1 1 0 0 1.5 V 0 1 1 0 1 1.125 V 1 1 1 0 1 1.525 V 0 1 1 1 0 1.15 V 1 1 1 1 0 1.55 V 0 1 1 1 1 1.175 V 1 1 1 1 1 1.6 V Submit Documentation Feedback VDCDC1 Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 8.6.8 DEFSLEW Register Address: 07h (Read or Write), Default Value: 06h Table 13. DEFSLEW Register DEFSLEW B7 B6 B5 B4 B3 B2 B1 B0 Bit name and function – – – – – SLEW2 SLEW1 SLEW0 Default – – – – – 1 1 0 Default value loaded – – – – – UVLO UVLO UVLO Read/write – – – – – R/W R/W R/W Table 14. DCDC1 DVS Slew Rate SLEW2 SLEW1 SLEW0 VDCDC1 SLEW RATE 0 0 0 0.225 mV/μs 0 0 1 0.45 mV/μs 0 1 0 0.9 mV/μs 0 1 1 1.8 mV/μs 1 0 0 3.6 mV/μs 1 0 1 7.2 mV/μs 1 1 0 14.4 mV/μs 1 1 1 Immediate 8.6.9 LDO_CTRL Register Address: 08h (Read or Write), Default Value: Set with DEFLDO1 and DEFLDO2 Table 15. LDO_CTRL Register LDO_CTRL B7 B6 B5 B4 B3 B2 B1 B0 RSVD LDO2_2 LDO2_1 LDO2_0 RSVD LDO1_2 LDO1_1 LDO1_0 Default – DEFLDOx DEFLDOx DEFLDOx – DEFLDOx DEFLDOx DEFLDOx Default value loaded – UVLO UVLO UVLO – UVLO UVLO UVLO Read/write – R/W R/W R/W – R/W R/W R/W Bit name and function The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2. LDO_CTRL[7] and LDO_CTRL[3] are reserved and must always be written to 0. The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 3. Table 16. LDO2 and LDO1 I2C Voltage Options LDO2_2 LDO2_1 LDO2_0 LDO2 OUTPUT VOLTAGE LDO1_2 LDO1_1 LDO1_0 LDO1 OUTPUT VOLTAGE 0 0 0 1.05 V 0 0 0 1V 0 0 1 1.2 V 0 0 1 1.1 V 0 1 0 1.3 V 0 1 0 1.3 V 0 1 1 1.8 V 0 1 1 2.1 V 1 0 0 2.5 V 1 0 0 2.2 V 1 0 1 2.8 V 1 0 1 2.6 V 1 1 0 3.0 V 1 1 0 2.8 V 1 1 1 3.3 V 1 1 1 3.15 V Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 37 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Input Voltage Connection The low power section of the control circuit for the step-down converters DCDC1, DCDC2, and DCDC3 is supplied by the VCC pin while the circuitry with high power such as the power stage is powered from the VINDCDC1, VINDCDC2, and VINDCDC3 pins. For proper operation of the step-down converters, VINDCDC1, VINDCDC2, VNDCDC3, and VCC need to be tied to the same voltage rail. Step-down converters that are planned to be not used, still need to be powered from their input pin on the same rails than the other step-down converters and VCC. LDO1 and LDO2 share a supply voltage pin which can be powered from the VCC rails or from a voltage lower than VCC, for example, the output of one of the step-down converters as long as it is operated within the input voltage range of the LDOs. If both LDOs are not used, the VINLDO pin can be tied to GND. 9.1.2 Unused Regulators In case a step-down converter is not used, its input supply voltage pin VINDCDCx still must be connected to the VCC rail along with supply input of the other step-down converters. TI recommends closing the control loop such that an inductor and output capacitor is added in the same way as it would be when operated normally. If one of the LDOs is not used, its output capacitor must be added as well. If both LDOs are not used, the input supply pin as well as the output pins of the LDOs (VINLDO, VLDO1, VLDO2) must be tied to GND. 9.1.3 Reset Condition of DCDC1 If DEFDCDC1 is connected to ground and DCDC1_EN is pulled high after VINDCDC1 is applied, the output voltage of DCDC1 defaults to 1.225 V instead of 1.2 V (high by 2%). Figure 38 illustrates the problem. VCC/VINDCDC1 DCDC1_EN 1.225 V 1.225 V 1.225 V VDCDC1 Figure 38. Default DCDC1 38 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 Application Information (continued) One workaround is to tie DCDC1_EN to VINDCDC1 (Figure 39). VCC/VINDCDC1 DCDC1_EN 1.20 V 1.20 V 1.20 V VDCDC1 Figure 39. Workaround 1 Another workaround is to write the correct voltage to the DEF_CORE register through I2C. This can be done before or after the converter is enabled. If written before the enable, the only bit changed is DEF_CORE[0]. The voltage is 1.2 V, however, when the enable is pulled high (Figure 40). VCC/VINDCDC1 DCDC1_EN I2C Bus DEF_CORE ?? 0x1F 0x11 1.225 V VDCDC1 0x10 ?? 0x1F 0x1E 1.20 V 1.20 V Pull DCDC1_EN High Write DEF_CORE to 0x10 Write CON_CTRL [7] to 1 0x10 Write DEF_CORE to 0x10 Pull DCDC1_EN High Figure 40. Workaround 2 A third workaround is to generate a HOT_RESET after enabling DCDC1 (Figure 41). VCC/VINDCDC1 DCDC1_EN HOT_RESET 1.225 V 1.20 V VDCDC1 1.225 V 1.20 V Figure 41. Workaround 3 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 39 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com Application Information (continued) Table 17. Differences of TPS650231 vs TPS65023 and TPS65023B ITEM DESCRIPTION TPS65023 TPS65023B TPS650231 Minimum 1.65 V; Vcc = 2.5 V to 5.25 V VIH High level input voltage for the SDAT pin Minimum 1.3 V Minimum 1.65 V; Vcc = 2.5 V to 5.25 V VIH High level input voltage for the SCLK pin Minimum 1.3 V Minimum 1.4 V, Vcc = 2.5 V to 5.25 V Minimum 1.4 V, Vcc = 2.5 V to 5.25 V VIL Low level input voltage for SCLK and SDAT pin Maximum 0.4 V Maximum 0.35 V Maximum 0.35 V th(DATA) Data input hold time Minimum 300 ns Minimum 100 ns Minimum 100 ns tsu(DATA) Data input setup time Minimum 300 ns Minimum 100 ns Minimum 100 ns 1.8 V 1.8 V 2.1 V 1) DEFDCDC2 = LOW: Vo = 1.8 V 2) DEFDCDC2 = HIGH: Vo = 3.3 V 3) 0.6 V feedback input 1) DEFDCDC2 = LOW: Vo = 1.8 V 2) DEFDCDC2 = HIGH: Vo = 3.3 V 3) 0.6 V feedback input 0.6 V feedback input only (allows voltage scaling with external resistor divider without restrictions) LDO1 voltage for setting LDO1_[2..0] = 011 DEFDCDC2 pin functionality 9.2 Typical Application TPS650231 Figure 42. Typical Configuration for the Texas Instruments TMS320DM644x DaVinci Processors 40 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 Typical Application (continued) 9.2.1 Design Requirements The TPS650231 device has only a few design requirements. Use the following parameters for the design examples: • 1-μF bypass capacitor on VCC, located as close as possible to the VCC pin to ground • VCC and VINDCDCx must be connected to the same voltage supply with minimal voltage difference • Input capacitors must be present on the VINDCDCx and VIN_LDO supplies if used • Output inductor and capacitors must be used on the outputs of the DCDC converters if used • Output capacitors must be used on the outputs of the LDOs if used 9.2.2 Detailed Design Procedure 9.2.2.1 Inductor Selection for the DC-DC Converters Each of the converters in the TPS650231 typically use a 2.2-μH output inductor. Larger or smaller inductor values are used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest DC resistance must be selected for highest efficiency. For a fast transient response, a 2.2-μH inductor in combination with a 22-μF output capacitor is recommended. Equation 8 calculates the maximum inductor current under static load conditions. The saturation current of the inductor must be rated higher than the maximum inductor current as calculated with Equation 8. This is needed because during heavy-load transient the inductor current rises above the value calculated under Equation 8. 1 * Vout Vin DI + Vout L L ƒ (8) I Lmax + I outmax ) DI L 2 where • • • • f = Switching frequency (2.25 MHz typical) L = Inductor value ΔIL = Peak-to-peak inductor ripple current ILMAX = Maximum inductor current (9) The highest inductor current occurs at maximum Vin. Open-core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS650231 (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core material from inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies. See Table 18 and the typical applications for possible inductors. Table 18. Tested Inductors DEVICE INDUCTOR VALUE TYPE COMPONENT SUPPLIER 2.2 μH LPS4012-222LMB Coilcraft 2.2 μH VLCF4020T-2R2N1R7 TDK For DCDC2 or DCDC3 2.2 μH LQH32PN2R2NN0 Murata 2.2 μH PSI25201T-2R2 Cyntec For DCDC1 1.5 μH LQH32PN1R5NN0 Murata All Converters Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 41 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 9.2.2.2 Output Capacitor Selection The advanced fast response voltage mode control scheme of the inductive converters implemented in the TPS650231 allow the use of small ceramic capacitors with a typical value of 10 μF for each converter without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. See Table 19 for recommended components. If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. Just for completeness, the RMS ripple current is calculated with Equation 10. V 1 - out Vin 1 x IRMSCout = Vout x L x ¦ 2 x Ö3 (10) At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor in Equation 11. V 1 - out Vin 1 DVout = Vout x x + ESR L x ¦ 8 x Cout x ¦ ( ) where • the highest output voltage ripple occurs at the highest input voltage Vin (11) At light-load currents, the converters operate in PSM and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage. 9.2.2.3 Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low-ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. Each DC-DC converter requires a 10-μF ceramic input capacitor on its input pin VINDCDCx. The input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the input for the DC-DC converters. A filter resistor of up to 10R and a 1-μF capacitor is used for decoupling the VCC pin from switching noise. NOTE The filter resistor may affect the UVLO threshold because up to 3 mA can flow through this resistor into the VCC pin when all converters are running in PWM mode. Table 19. Possible Capacitors CAPACITOR VALUE CASE SIZE COMPONENT SUPPLIER COMMENTS 22 μF 22 μF 0805 TDK C2012X5R0J226MT Ceramic 0805 Taiyo Yuden JMK212BJ226MG Ceramic 10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic 10 μF 0805 TDK C2012X5R0J106M Ceramic 10 μF 0603 Taiyo Yuden JMK107BJ106 Ceramic 9.2.2.4 Output Voltage Selection The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down converter. For DEFDCDC1 and DEFDCDC3 there are default voltages defined when the pin is tied to a logic low or logic high signal. See Table 20 for the default voltages if the pins are pulled to GND or to Vcc. If a different voltage is needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 43. 42 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 The output voltage of VDCDC1 is set with the I2C interface. If the voltage is changed from the default, using the DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC1 can not change the voltage set with the register. TI does not recommend changing the divider ratio of a resistor divider connected at DEFDCDC1 or DEFDCDC3 during operation as the internal logic may detect a logic high signal in error during the change from a high voltage to a lower voltage and scales the output to the voltage defined by DEFDCDCx = HIGH. As DEFDCDC2 does not have these default fixed voltages, the resistor divider can be changed during operation. Table 20. DCDC1 and DCDC3 Default Voltage Levels PIN DEFDCDC1 DEFDCDC3 LEVEL DEFAULT OUTPUT VOLTAGE VCC 1.6 V GND 1.2 V VCC 3.3 V GND 1.8 V This function is not available on the DCDC2 converter. DEFDCDC2 always needs to be connected to a resistive divider. Using an external resistor divider for the DEFDCDCx is shown in Figure 43. 1Ω V(bat) VCC 1 mF VDCDC3 L3 VINDCDC3 VO L CI CO R1 DEFDCDC3 DCDC3_EN R2 AGND PGND Figure 43. External Resistor Divider When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input voltage V(bat). The total resistance (R1+R2) of the voltage divider must be kept in the 1-MΩ range to maintain a high efficiency at light load. V(DEFDCDCx) = 0.6 V VOUT = VDEFDCDCx x R1 + R2 R2 R1 = R2 x ( VOUT VDEFDCDCx ) - R2 (12) 9.2.2.5 VRTC Output It is required to add a capacitor of 4.7-μF minimum to the VRTC pin, even the output may be unused. 9.2.2.6 LDO1 and LDO2 The LDOs in the TPS650231 are general-purpose LDOs which are stable using ceramics capacitors. The minimum output capacitor required is 2.2 μF. The LDOs output voltage can be changed to different voltages between 1 V and 3.3 V using the I2C interface. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and provides the highest efficiency. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 43 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 9.2.2.7 TRESPWRON This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V. The timing is generated by charging and discharging the capacitor with a current of 2 μA between a threshold of 0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms. While there is no real upper and lower limit for the capacitor connected to TRESPWRON, TI recommends to not leave signal pins open. ( t(reset) = 2 x 128 x (1 V - 0.25 V) x C(reset) 2 mA ) where • • t(reset) is the reset delay time C(reset) is the capacitor connected to the TRESPWRON pin (13) The minimum and maximum values for the timing parameters called ICONST (2 μA), TRESPWRON_UPTH (1 V) and TRESPWRON_LOWTH (0.25 V) can be found in Specifications. 9.2.2.8 VCC Filter An RC filter connected at the VCC input is used to keep noise from the internal supply for the bandgap and other analog circuitry. A typical value of 1 Ω and 1 μF is used to filter the switching spikes, generated by the DC-DC converters. A larger resistor than 10 Ω must not be used because the current into VCC of up to 3 mA causes a voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to switch off too early. 9.2.3 Application Curves Graphs were taken using the EVM with the following inductor and output capacitor combinations: CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE VDCDC1 LQH32PN1R5 JMK107BJ106 2 × 10 μF VDCDC2 LQH32PN2R2 JMK107BJ106 2 × 10 μF VDCDC3 LQH32PN2R2 JMK107BJ106 2 × 10 μF space 100 100 90 VI = 2.5 V 90 VI = 3 V 80 80 VI = 4.2 V 60 VI = 3.6 V VI = 3.6 V 70 Efficiency - % Efficiency - % 70 VI = 5 V 50 40 20 60 VI = 5 V 50 40 0.1 1 10 100 1k IO - Output Current - mA TA = 25°C, VO = 1.8 V, PFM Mode 20 TA = 25°C, VO = 1.2 V, PFM Mode 10 10 10 k Figure 44. DCDC1: Efficiency vs Output Current 44 VI = 2.5 V VI = 4.2 V 30 30 0 0.01 VI = 3 V 0 0.01 0.1 1 10 100 1k IO - Output Current - mA 10 k Figure 45. DCDC2: Efficiency vs Output Current Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 100 90 VI = 2.5 V 80 VI = 3 V Efficiency - % 70 VI = 3.6 V 60 VI = 4.2 V VI = 5 V 50 40 30 20 TA = 25°C, VO = 1.8 V, PFM Mode 10 0 0.01 0.1 1 10 100 1k IO - Output Current - mA 10 k Figure 46. DCDC3: Efficiency vs Output Current 10 Power Supply Recommendations 10.1 Requirements for Supply Voltages Below 3.0 V For a supply voltage on pins VCC, VINDCDC1, VINDCDC2, and VINDCDC3 below 3.0 V, TI recommends enabling the DCDC1, DCDC2, and DCDC3 converters in sequence. If all 3 step-down converters are enabled at the same time while the supply voltage is close to the internal reset detection threshold, a reset may be generated during power-up. Therefore, TI recommends enabling the DC-DC converters in sequence. This can be done by driving one or two of the enable pins with a RC delay or by driving the enable pin by the output voltage of one of the other step-down converters. If a voltage above 3.0 V is applied on pin VBACKUP while VCC and VINDCDCx is below 3.0 V, there is no restriction in the power-up sequencing as VBACKUP is used to power the internal circuitry. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 45 TPS650231 SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 www.ti.com 11 Layout 11.1 Layout Guidelines As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Take care in board layout to get the specified performance. If the layout is not carefully done, the regulators may show poor line and/or load regulation, and stability issues, as well as EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitors must be placed as close as possible to the IC pins as well as the inductor and output capacitor. For TPS650231RSB, connect the PGND pins of the device to the PowerPAD land of the PCB and connect the analog ground connections (AGND) to the PGND at the PowerPAD. It is essential to provide a good thermal and electrical connection of all GND pins using multiples through to the GND-plane. Keep the common path to the AGND pins, which returns the small signal components, and the high current of the output capacitors as short as possible to avoid ground noise. The VDCDCx line must be connected right to the output capacitor and routed away from noisy components and traces (for example, the L1, L2, and L3 traces). For TPS650231YFF, connect the PGND pins of the device and the analog ground connections (AGND) to the GND plane on the board. It is essential to provide a good thermal and electrical connection of all GND pins to the GND-plane. Keep the common path to the AGND pins, which returns the small signal components, and the high current of the output capacitors as short as possible to avoid ground noise. The VDCDCx line must be connected right to the output capacitor and routed away from noisy components and traces (for example, the L1, L2, and L3 traces). 11.2 Layout Example VIN Cout L3 Cout CIN VDCDC3 PGND3 Figure 47. DC–DC Regulator Layout Example 46 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 TPS650231 www.ti.com SLVSAE3A – AUGUST 2010 – REVISED JANUARY 2016 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. 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Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: TPS650231 47 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS650231RSBR ACTIVE WQFN RSB 40 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 650231 TPS650231RSBT ACTIVE WQFN RSB 40 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 650231 TPS650231YFFR ACTIVE DSBGA YFF 49 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TPS650231 TPS650231YFFT ACTIVE DSBGA YFF 49 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TPS650231 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of