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TPS65262
SLVSCF9C – JANUARY 2014 – REVISED JULY 2014
TPS65262 4.5- to 18-V Input Voltage, 3-A/1-A/1-A Output Current Triple Synchronous
Step-Down Converter With Dual Adjustable 200-mA/100-mA LDOs
1 Features
3 Description
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The TPS65262 is a monolithic triple synchronous
step-down (buck) converter with 3-A/1-A/1-A output
current. A wide 4.5- to 18-V input supply voltage
range encompasses the most intermediate bus
voltage operating off 5-, 9-, 12-, or 15-V power bus.
The converter, with constant frequency peak current
mode, is designed to simplify its application while
giving designers options to optimize the system
according to targeted applications. The device
operates at 600-kHz fixed switching frequency. The
loop compensations for buck 2 and buck3 have been
integrated for less external components. The 180°
out-of-phase operation between buck1 and buck2, 3
(buck2 and buck3 run in phase) minimizes the input
filter requirements. At light load, the device
automatically operates in PSM, which provides high
efficiency by reducing switching losses.
1
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•
•
•
•
•
•
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Operating Input Voltage Range: 4.5 to 18 V
Feedback Reference Voltage: 0.6 V ±1%
Maximum Continuous Output Current: 3 A/1 A/1 A
Fixed 600-kHz Switching Frequency
Integrated Dual LDOs With Input Voltage Range:
1.3 to 18 V and Continuous Output Current: 200
mA/100 mA
Programmable Soft Start Time for Buck1
Fixed 1-ms Soft Start Time for Buck2 and Buck3
Internal Loop Compensation for Buck2 and Buck3
Dedicated Enable Pins for Each Buck
Automatic Power-Up/Power-Down Sequence
Pulse Skipping Mode (PSM) at Light Load
Output Voltage Power Good Indicator
Thermal Overloading Protection
32-Pin VQFN (RHB) 5-mm × 5-mm Package
2 Applications
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•
•
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DTV
Set-Top Boxes
Home Gateway and Access Point Networks
Wireless Routers
Surveillance
POS Machine
Two low dropout voltage linear regulators (LDO) are
also built in TPS65262 with input voltage range 1.3 to
18 V, continuous output current 200 mA/100 mA,
independent enable and adjustable output voltage.
The TPS65262 features an automatic power
sequence with driving MODE pin to high and
configuring EN1, EN2, and EN3 pins.
The device features overvoltage protection,
overcurrent and short-circuit protection, and
overtemperature protection. A power good pin asserts
when any output voltages are out of regulation.
Device Information(1)
PART NUMBER
TPS65262
PACKAGE
VQFN (32)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Typical Application
Efficiency vs Output Load
Vin
100%
Vout1
VINx
LX1
90%
80%
PGOOD
FB1
MODE
Vout2
SS1
LX2
TPS65262
LDO1
LVIN1
LOUT1
LFB1
LEN1
FB2
Vout3
LDO2
LX3
LVIN2
LOUT2
LFB2
LEN2
60%
50%
40%
30%
TPS65262
VIN 12 V
VOUT 3.3 V
20%
10%
FB3
AGND
Efficiency (%)
70%
ENx
PGND
0%
0.01
0.10
Output Load t A
1.00
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65262
SLVSCF9C – JANUARY 2014 – REVISED JULY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application ................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
6
7
9
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 22
9
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Application .................................................. 23
10 Power Supply Recommendations ..................... 33
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 34
12 Device and Documentation Support ................. 35
12.1 Trademarks ........................................................... 35
12.2 Electrostatic Discharge Caution ............................ 35
12.3 Glossary ................................................................ 35
13 Mechanical, Packaging, and Orderable
Information ........................................................... 35
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2014) to Revision C
Page
•
Updated data sheet to new TI standards .............................................................................................................................. 1
•
Corrected package type to VQFN ......................................................................................................................................... 1
•
Updated V(ESD) ratings in Handling Ratings and notes ........................................................................................................... 5
•
Updated MIN VFB and added note to Gm_PS1/2/3 ...................................................................................................................... 7
•
Added new graphs to the Typical Characteristics and moved plots to the Application Curves ........................................... 11
•
Expanded the Applications section to include more information ......................................................................................... 23
•
Updated Figure 63 FB1 pin name ........................................................................................................................................ 34
Changes from Revision A (January 2014) to Revision B
•
Changed Data sheet status from Product Preview to Production Data ................................................................................ 1
Changes from Original (January 2014) to Revision A
•
2
Page
Page
Changed Imax_LDO1 min spec ................................................................................................................................................... 8
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Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS65262
TPS65262
www.ti.com
SLVSCF9C – JANUARY 2014 – REVISED JULY 2014
6 Pin Configuration and Functions
EN1
FB1
SS1
COMP1
V7V
AGND
FB3
EN3
32-Pin Plastic VQFN
RHB Package
Top View
24
23
22
21
20
19
18
17
BST1 25
16
BST3
LX1 26
15
LX3
PGND1 27
14
PGND3
13
VIN3
LEN1 29
12
VIN2
LFB1 30
11
PGND2
LOUT1 31
10
LX2
LVIN1 32
9
VIN1 28
4
5
6
7
8
PGOOD
MODE
FB2
EN2
LOUT2
3
LEN2
2
LFB2
1
LVIN2
Thermal Pad
BST2
(There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.)
Pin Functions
PIN
NAME
DESCRIPTION
NO.
LVIN2
1
Input power supply for LDO2. Connect LVIN2 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 1 µF).
LOUT2
2
LDO2 output. Connect LOUT2 pin as close as possible to the (+) terminal of an output ceramic capacitor (suggest 1 µF).
LFB2
3
Feedback Kelvin sensing pin for LDO2 output voltage. Connect this pin to LDO2 resistor divider.
LEN2
4
Enable for LDO2. Float to enable.
PGOOD
5
An open-drain output, asserts low if output voltage of any buck is beyond regulation range due to thermal shutdown,
overcurrent, undervoltage, or ENx shut down.
MODE
6
When high, an automatic power-up/power-down sequence is provided according to states of EN1, EN2 and EN3 pins.
FB2
7
Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
EN2
8
Enable for buck2. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck2 with a resistor
divider.
BST2
9
Boot strapped supply to the high side floating gate driver in Buck2. Connect a capacitor (recommend 47 nF) from BST2
pin to LX2 pin.
LX2
10
Switching node connection to the inductor and bootstrap capacitor for Buck2. The voltage swing at this pin is from a
diode voltage below the ground up to VIN2 voltage.
PGND2
11
Power ground connection of Buck2. Connect PGND2 pin as close as possible to the (–) terminal of VIN2 input ceramic
capacitor.
VIN2
12
Input power supply for Buck2. Connect VIN2 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
VIN3
13
Input power supply for Buck3. Connect VIN3 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
PGND3
14
Power ground connection of Buck3. Connect PGND3 pin as close as possible to the (–) terminal of VIN3 input ceramic
capacitor.
LX3
15
Switching node connection to the inductor and bootstrap capacitor for Buck3. The voltage swing at this pin is from a
diode voltage below the ground up to VIN3 voltage.
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Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS65262
3
TPS65262
SLVSCF9C – JANUARY 2014 – REVISED JULY 2014
www.ti.com
Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
BST3
16
Boot strapped supply to the high side floating gate driver in Buck3. Connect a capacitor (recommend 47 nF) from BST3
pin to LX3 pin.
EN3
17
Enable for Buck3. Float to enable. Can use this pin to adjust the input undervoltage lockout of Buck3 with a resistor
divider.
FB3
18
Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to Buck3 resistor divider.
AGND
19
Analog ground common to buck controllers and other analog circuits. It must be routed separately from high current
power grounds to the (-) terminal of bypass capacitor of input voltage VIN.
V7V
20
Internal LDO for gate driver and internal controller. Connect a 1-µF capacitor from the pin to power ground
COMP1
21
Error amplifier output and loop compensation pin for Buck1. Connect a series resistor and capacitor to compensate the
control loop of buck1 with peak current PWM mode.
SS1
22
Soft-start and tracking input for Buck1. An internal 5-µA pullup current source is connected to this pin. The soft-start time
can be programmed by connecting a capacitor between this pin and ground.
FB1
23
Feedback Kelvin sensing pin for Buck1 output voltage. Connect this pin to Buck1 resistor divider.
EN1
24
Enable for Buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout of Buck1 with a resistor
divider.
BST1
25
Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47 nF) from BST1
pin to LX1 pin.
LX1
26
Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a
diode voltage below the ground up to VIN1 voltage.
PGND1
27
Power ground connection of buck1. Connect PGND1 pin as close as possible to the (–) terminal of VIN1 input ceramic
capacitor.
VIN1
28
Input power supply for buck1. Connect VIN1 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
LEN1
29
Enable for LDO1. Float to enable.
LFB1
30
Feedback Kelvin sensing pin for LDO1 output voltage. Connect this pin to LDO1 resistor divider.
LOUT1
31
LDO1 output. Connect LOUT1 pin as close as possible to the (+) terminal of an output ceramic capacitor (suggest 1 µF).
LVIN1
32
Input power supply for LDO1. Connect LVIN1 pin as close as possible to the (+) terminal of an input ceramic capacitor
(suggest 1 µF).
PAD
—
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.
4
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS65262
TPS65262
www.ti.com
SLVSCF9C – JANUARY 2014 – REVISED JULY 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (operating in a typical application circuit) (1)
Voltage at
TJ
(1)
MIN
MAX
VIN1, VIN2, VIN3, LVIN1, LVIN2
–0.3
20
LX1, LX2, LX3 (Maximum withstand voltage transient
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