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TPS65268-Q1
SLVSE48B – JANUARY 2018 – REVISED MAY 2019
TPS65268-Q1 4-V to 8-V, 3-A, 2-A, 2-A Triple Synchronous Step-Down Converter
1 Features
3 Description
•
•
The TPS65268-Q1 device incorporates triplesynchronous buck converters with 4- to 8-V wide
input voltage. The converter with constant frequency
peak current mode is designed to simplify its
application while giving designers options to optimize
the system according to targeted applications. The
switching frequency of the converters is adjustable
from 200 kHz to 2.3 MHz with an external resistor.
Operation that is 180° out-of-phase between BUCK1
and BUCK2, and BUCK3 (BUCK2 and BUCK3 run in
phase) minimizes the input filter requirements.
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
operating junction temperature
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
Operating input voltage range 4- to 8-V maximum
continuous output current 3 A, 2 A,
2A
Feedback reference voltage 0.6 V ±1%
Adjustable clock frequency from 200 kHz to 2.3
MHz
Forced continuous current mode (FCCM)
External clock synchronization
Dedicated enable and soft-start pins for each buck
Output voltage power good indicator
Thermal overloading protection
1
•
•
•
•
•
•
•
•
Each buck converter in the TPS65268-Q1 device
operates in forced continuous-current mode (FCCM)
at light load condition for reduced output voltage
ripple and improved load transient response.
The TPS65268-Q1 device features overvoltage,
overcurrent, short-circuit, and overtemperature
protection.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2 Applications
TPS65268-Q1
•
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Automotive
Car audio and video
Home gateway and access point networks
Surveillance
PVINx
LX1
100
VOUT1
90
VIN
TPS65268-Q1
80
FB1
LX2
ROSC
FB2
LX3
VOUT2
VOUT3
70
Efficiency (%)
PGOOD
ENx
SSx
60
50
40
30
Vin = 5V, Fsw = 2MHz
Vout1 = 1.5V
Vout2 = 1.2V
Vout3 = 2.5V
20
AGND
PGND
5.00 mm × 5.00 mm
Efficiency vs Output Load
Application Schematic
VIN
VQFN (32)
FB3
10
0
0.01
Copyright © 2017, Texas Instruments Incorporated
0.02
0.05
0.1
0.2 0.3 0.5 0.7 1
Output Load (A)
2
3
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65268-Q1
SLVSE48B – JANUARY 2018 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 22
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 33
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2018) to Revision B
•
Page
Changed Figure 52 thermal signature .................................................................................................................................. 30
Changes from Original (January 2018) to Revision A
Page
•
Changed the maximum value for the BUCK2/BUCK3 peak inductor current limit parameter from 3.9 A to 4 A in the
Electrical Characteristics table ............................................................................................................................................... 6
•
Changed the unit for soft start current from mA to µA in the SS Pin Charge Current vs Temperature graph....................... 9
2
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SLVSE48B – JANUARY 2018 – REVISED MAY 2019
5 Pin Configuration and Functions
SS1
COMP1
FB1
ROSC
PGOOD
FB3
COMP3
SS3
24
23
22
21
20
19
18
17
RHB Package
32-Pin VQFN With Exposed Thermal Pad
Top View
BST1
25
16
BST3
LX1
26
15
LX3
PGND1
27
14
PGND3
PVIN1
28
13
PVIN3
VIN
29
12
PVIN2
V7V
30
11
PGND2
EN1
31
10
LX2
EN2
32
9
Thermal
1
2
3
4
5
6
7
8
EN3
AGND
AGND
AGND
AGND
FB2
COMP2
SS2
Pad
BST2
Not to scale
No electric signal is down bonded to thermal pad inside the device. Exposed thermal pad must be soldered to PCB
for optimal thermal performance.
Pin Functions
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
EN3
I
Enable for BUCK3. Float to enable. Use this pin to adjust the UVLO input voltage of BUCK3 with a
resistor divider.
AGND
G
Analog ground common to buck controllers and other analog circuits. This pin must be routed separately
from high-current power grounds to the negative pin of bypass capacitor of input voltage (VIN).
6
FB2
I
Feedback Kelvin sensing pin for BUCK2 output voltage. Connect this pin to the BUCK2 resistor divider.
7
COMP2
O
Error amplifier output and loop compensation pin for BUCK2. Connect a series resistor and capacitor to
compensate the control loop of BUCK2 with peak-current PWM mode.
8
SS2
O
Soft-start and tracking input for BUCK2. An internal 5.2-µA pullup current source is connected to this pin.
The soft-start time can be programmed by connecting a capacitor between this pin and ground.
9
BST2
O
Boot-strapped supply to the high-side floating gate driver in BUCK2. Connect a capacitor (recommended
value of 47 nF) from the BST2 pin to LX2 pin.
10
LX2
O
Switching node connection to the inductor and bootstrap capacitor for BUCK2. The voltage swing at this
pin is from a diode voltage below the ground up to the PVIN2 voltage.
11
PGND2
G
Power ground connection of BUCK2. Connect the PGND2 pin as close as possible to the negative pin of
VIN2 input ceramic capacitor.
12
PVIN2
P
Input power supply for BUCK2. Connect the PVIN2 pin as close as possible to the positive pin of an input
ceramic capacitor (recommended value of 10 µF).
1
2
3
4
5
(1)
I = Input, O = Output, P = Supply, G = Ground
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Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
PVIN3
P
Input power supply for BUCK3. Connect the PVIN3 pin as close as possible to the positive pin of an input
ceramic capacitor (recommended value of 10 µF).
14
PGND3
G
Power ground connection of BUCK3. Connect the PGND3 pin as close as possible to the negative pin of
the VIN3 input ceramic capacitor.
15
LX3
O
Switching node connection to the inductor and bootstrap capacitor for BUCK3. The voltage swing at this
pin is from a diode voltage below the ground up to the PVIN3 voltage.
16
BST3
O
Boot-strapped supply to the high-side floating gate driver in BUCK3. Connect a capacitor (recommended
value of 47 nF) from the BST3 pin to LX3 pin.
17
SS3
O
Soft-start and tracking input for BUCK3. An internal 5.2-µA pullup current source is connected to this pin.
The soft-start time can be programmed by connecting a capacitor between this pin and ground.
18
COMP3
O
Error amplifier output and loop compensation pin for BUCK3. Connect a series resistor and capacitor to
compensate the control loop of BUCK3 with peak-current PWM mode.
19
FB3
I
Feedback Kelvin sensing pin for BUCK3 output voltage. Connect this pin to the BUCK3 resistor divider.
20
PGOOD
O
Output voltage supervision pin. When all buck converters are in the regulation range of the PGOOD
monitor, the PGOOD pin is asserted high.
21
ROSC
O
Clock frequency adjustment pin. Connect a resistor from this pin to ground to adjust the clock frequency.
When connected to an external clock, the internal oscillator synchronizes to the external clock.
22
FB1
I
Feedback Kelvin sensing pin for BUCK1 output voltage. Connect this pin to the BUCK1 resistor divider.
23
COMP1
O
Error amplifier output and loop compensation pin for BUCK1. Connect a series resistor and capacitor to
compensate the control loop of BUCK1 with peak current PWM mode.
24
SS1
O
Soft-start and tracking input for BUCK1. An internal 5.2-µA pullup current source is connected to this pin.
The soft-start time can be programmed by connecting a capacitor between this pin and ground.
25
BST1
O
Boot-strapped supply to the high-side floating gate driver in BUCK1. Connect a capacitor (recommended
value of 47 nF) from the BST1 pin to LX1 pin.
26
LX1
O
Switching node connection to the inductor and bootstrap capacitor for BUCK1. The voltage swing at this
pin is from a diode voltage below the ground up to the PVIN1 voltage.
27
PGND1
G
Power ground connection of BUCK1. Connect the PGND1 pin as close as possible to the negative pin of
PVIN1 input ceramic capacitor.
28
PVIN1
P
Input power supply for BUCK1. Connect the PVIN1 pin as close as possible to the positive pin of an input
ceramic capacitor (suggest 10 µF).
29
VIN
P
Buck controller power supply
30
V7V
O
Internal LDO regulator for gate driver and internal controller. Connect a 1-µF capacitor from the pin to
power ground.
31
EN1
I
Enable for BUCK1. Float to enable. Use this pin to adjust the UVLO input voltage of BUCK1 with a
resistor divider.
32
EN2
I
Enable for BUCK2. Float to enable. Use this pin to adjust the UVLO input voltage of BUCK2 with a
resistor divider.
—
PAD
—
No electric signal is down bonded to thermal pad inside the device. Exposed thermal pad must be
soldered to PCB for optimal thermal performance.
NO.
NAME
13
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
PVIN1, PVIN2, PVIN3,VIN
LX1, LX2, LX3 (Maximum withstand voltage transient < 20 ns)
MIN
MAX
UNIT
–0.3
12
V
–1
15
V
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively
–0.3
7
V
EN1, EN2, EN3, V7V, PGOOD
–0.3
7
V
FB1, FB2, FB3, COMP1 , COMP2, COMP3, ROSC, SS1, SS2, SS3
–0.3
3.6
V
AGND, PGND1, PGND2, PGND3
–0.3
0.3
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic
discharge
(1)
Charged-device model (CDM), per AEC Q100011
UNIT
±2000
All pins
±500
Corner pins (1, 8, 9, 16, 17, 24, 25,
and 32)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
PVIN1, PVIN2, PVIN3,VIN
MAX
UNIT
4
8
V
LX1, LX2, LX3 (Maximum withstand voltage transient 4 V
PVIN
VIN
Ih
R1
EN
R2
Ip
+
±
Figure 24. Adjustable VIN and PVIN UVLO
7.3.3 Soft-Start Time
The voltage on the respective SSx pin controls the startup of buck output. When the voltage on the SSx pin is
less than the internal 0.6-V reference, the TPS65268-Q1 device regulates the internal feedback voltage to the
voltage on the SSx pin instead of 0.6 V. The SSx pin can be used to program an external soft-start function or to
allow the output of buck converter to track another supply during start-up. The device has an internal pullup
current source of 5.2 µA (typical) that charges an external soft-start capacitor to provide a linear ramping voltage
at the SSx pin. The TPS65268-Q1 device regulates the internal feedback voltage to the voltage on the SSx pin,
allowing the output voltage to rise smoothly from 0 V to the regulated voltage of the pin without inrush current.
Use Equation 4 to calculate the approximate soft-start time.
CSS (nF) u Vref (V)
tSS (ms)
ISS (µA)
where
•
tSS is the soft-start time
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•
•
•
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CSS is the soft-start capacitance
ISS is the soft-start current
Vref is the reference voltage
(4)
Many of the common power-supply sequencing methods can be implemented using the SSx and ENx pins.
Figure 25 shows the method implementing ratiometric sequencing by connecting the SSx pins of the three buck
channels. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start
time, the pullup current source must be tripled in Equation 4.
EN
EN threshold = 1.2 V
31 EN1
32 EN2
1
EN3
VOUT3 = 2.5 V
24 SS1
VOUT1 = 1.5 V
8
SS2
VOUT2 = 1.2 V
17 SS3
CSS
t SS =
CSS × 0.6 V
15.6 µA
Figure 25. Ratiometric Power-Up Using SSx Pins
The user can implement simultaneous power-supply sequencing by connecting the capacitor to the SSx pin,
shown in Figure 26. Use Equation 4 and Equation 5 to calculate the value of the capacitors.
CSS1
CSS2
CSS3
VOUT1 VOUT2 VOUT3
(5)
16
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EN
31
EN threshold = 1.2 V
EN1
32
EN2
1
EN3
VOUT3 = 2.5 V
24
SS1
CSS1
VOUT1 = 1.5 V
8
SS2
CSS2
VOUT2 = 1.2 V
17
SS3
CSS3
t SS
CSS 3 u 0.6 V
5.2 PA
Figure 26. Simultaneous Startup Sequence Using SSx Pins
7.3.4 Power-Up Sequencing
The TPS65268-Q1 device has a dedicated enable pin and soft-start pin for each converter. The converter enable
pins are biased by a current source that allows for easy sequencing by the addition of an external capacitor.
Disabling the converter with an active pulldown transistor on the ENx pin allows for predictable power-down
timing operation. Figure 27 shows the timing diagram of a typical buck power-up sequence with connecting a
capacitor at the ENx pin.
A typical 1.4-µA current is charging the ENx pin from the input supply. When the ENx pin voltage rises to typical
0.4 V, the internal V7V LDO regulator turns on. A 3.9-µA pullup current sources the ENx pin. After the ENx pin
voltage reaches the ENx enabling threshold, a 3-µA hysteresis current sources to the pin to improve noise
sensitivity. The internal soft-start comparator compares the SSx pin voltage to 1.2 V. When the SSx pin voltage
ramps up to 1.2 V, PGOOD monitor is enabled. After PGOOD deglitch time, PGOOD is deasserted. The SSx pin
voltage is eventually clamped around 2.1 V.
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VIN
V7V
EN Threshold
ENx Rise Time
Dictated by CEN
Charge CEN with 6.9 µA
1.2 V
t
ENx
CSS u 0.6 V
5.2 µA
0.4 V
EN Threshold
Soft-Start Rise Time
Dictated by CSS
About 2.1 V
1.2 V
0.6 V
SSx
Prebias Startup
PGOOD Deglitch Time
VOx
t
PGOOD
CENx u 1.2 V 0.4 V
3.9 µA
t=
t
CSS u 1.2 V
5.2 µA
CENx u 0.4 V
1.4 µA
Figure 27. Startup Power Sequence
7.3.5 V7V Low-Dropout Regulator and Bootstrap
Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V
pin. The internal built-in low-dropout (LDO) linear regulator supplies 4.96 V (typical) from 5 V VIN to the V7V
voltage. The user should connect a 1-µF ceramic capacitor from the V7V pin to power ground.
If the input voltage decreases to the UVLO threshold voltage, the UVLO comparator detects the V7V pin voltage
and forces the converter off.
Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in Figure 28, which is
normally recharged during each cycle through an internal low-side MOSFET or the body diode of a low-side
MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less
than the input voltage and the BST-LX voltage is below regulation. TI recommends using a 47-nF ceramic
capacitor. TI recommends using a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of
10 V or higher because of the stable characteristics over temperature and voltage. Each low-side MOSFET
driver is powered from the V7V pin directly.
To improve dropout, the device is designed to operate at 100% duty cycle as long as the BST to LXx pin voltage
is greater than the BST-LX UVLO threshold, which is typically 2.1 V. When the voltage between the BST and
LXx pins drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side
MOSFET is turned on allowing the boot capacitor to be recharged.
18
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VIN
LDO
+
(VBSTx ± VLXx)
±
2.1 V
nBootUV
PVINx
V7V
CBIAS
1 µF
BSTx
UVLO Bias Buck
Controller
nBootUV
PWM
Gate
Driver
High-side
MOSFET
CB
LXx
nBootUV
BootUV
Protection
PWM
Gate
Driver
Low-side
MOSFET
CLK
Figure 28. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram
7.3.6 Out-of-Phase Operation
To reduce the input ripple current, the switch clock of BUCK1 is 180° out-of-phase from the clock of BUCK2 and
BUCK3. This operation enables the system to have less input current ripple to reduce the size, cost, and EMI of
the input capacitors.
7.3.7 Output Overvoltage Protection (OVP)
The device incorporates an OVP circuit to minimize output voltage overshoot. When the output is overloaded, the
error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower
than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum
output current. After the condition is removed, the regulator output rises and the error amplifier output transitions
to the steady-state voltage. In some applications with small output capacitance, the load can respond faster than
the error amplifier which leads to the possibility of an output overshoot. Each buck converter compares the FB
pin voltage to the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET
is turned off preventing current from flowing to the output and minimizing output overshoot. When the FB voltage
drops lower than the OVP threshold, the high-side MOSFET turns on at the next clock cycle.
7.3.8 Slope Compensation
To prevent the subharmonic oscillations when the device operates at duty cycles greater than 50%, the
TPS65268-Q1 devices adds built-in slope compensation, which is a compensating ramp to the switch current
signal.
7.3.9 Overcurrent Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and low-side MOSFET.
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7.3.9.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control that uses the COMP pin voltage to control the turnoff of the highside MOSFET and the turnon of the low-side MOSFET on a cycle-by-cycle basis. During each cycle, the switch
current and the current reference generated by the COMP pin voltage are compared and, when the peak switch
current intersects the current reference, the high-side switch is turned off.
7.3.9.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During
normal operation, the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET can also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 256 switching cycles shown in Figure 29, the device shuts down
and restarts after the hiccup time of 8192 cycles. The hiccup mode helps to reduce the device power dissipation
under severe overcurrent condition.
OCP peak-inductor current threshold
Soft-start time
OC limiting (waiting) time
256 cycles
Hiccup time
8192 cycles
tSS
CSS u 0.6 V
5.2 µA
Output over loading
IL
Inductor Current
Soft-start time is reset after OC waiting time
About 2.1 V
VSS
SS Pin Voltage
OC fault removed, soft-start, and output recovery
0.6 V
Output hard short circuit
VOUT
Output Voltage
Figure 29. Overcurrent Protection
7.3.10 Power Good
The PGOOD pin is an open-drain output. When the feedback voltage of each buck converter is between 95%
(rising) and 105% (falling) of the internal voltage reference, the PGOOD pin pulldown is deasserted and the pin
floats. TI recommends using a pullup resistor with a value of 10 kΩ to 100 kΩ connected to a voltage source that
is 5.5 V or less. The PGOOD pin is in a defined state when the VIN input voltage is greater than 1 V, but with
reduced current sinking capability. The PGOOD pin achieves full current sinking capability after the VIN input
voltage is above UVLO threshold, which is 3.8 V.
20
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The PGOOD pin is pulled low when any feedback voltage of buck converter is lower than 92.5% (falling) or
greater than 107.5% (rising) of the nominal internal reference voltage. Also, when the PGOOD pin is pulled low
and during an UVLO condition on the input voltage, thermal shutdown is asserted, the ENx pin is pulled low, or
the converter is in soft-start period.
7.3.10.1 Adjustable Switching Frequency
The ROSC pin can be used to set the switching frequency by connecting a resistor to ground. The switching
frequency of the device is adjustable from 200 kHz to 2.3 MHz.
To determine the ROSC resistance for a given switching frequency, use Equation 6 or the curve in Figure 30. To
reduce the solution size, the user should set the switching frequency as high as possible, but consider tradeoffs
of the supply efficiency and minimum controllable on-time.
fOSC (kHz)
37254 u R
0.966
(k:)
(6)
2300
Switching Frequency (kHz)
2000
1700
1400
1100
800
500
200
10
30
50
70
90
110 130 150 170 190 210 230
ROSC (k:)
D022
Figure 30. ROSC vs Switching Frequency
When an external clock applies to ROSC pin, the internal PLL has been implemented to allow internal clock
synchronizing to an external clock from 200 kHz to 2300 kHz. To implement the clock synchronization feature,
connect a square-wave clock signal to the ROSC pin with a duty cycle from 20% to 80%. The clock signal
amplitude must transition lower than 0.4 V and higher than 2.0 V. The start of the switching cycle is synchronized
to the falling edge of ROSC pin.
In applications where both resistor mode and synchronization mode are needed, the user can configure the
device as shown in Figure 31. Before an external clock is present, the device works in resistor mode and the
ROSC resistor sets the switching frequency. When an external clock is present, the synchronization mode
overrides the resistor mode. The first time the ROSC pin is pulled above the ROSC high threshold (2 V), the
device switches from the resistor mode to the synchronization mode and the ROSC pin is in the high impedance
state as the PLL starts to lock onto the frequency of the external clock. TI does not recommend switching from
the synchronization mode back to the resistor mode because the internal switching frequency drops to 100 kHz
first before returning to the switching frequency set by ROSC resistor.
Device
Mode
Selection
ROSC
ROSC
Figure 31. Works With Resistor Mode and Synchronization Mode
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7.3.11 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C (typical). The device reinitiates the power-up sequence when the junction temperature drops below 140°C
(typical).
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the ENx voltage is above the enable threshold, the
TPS65268-Q1 device operates at continuous current mode (CCM) with a fixed frequency for optimized output
ripple.
7.4.2 Standby Operation
When the TPS65268-Q1 device operates in normal CCM, the device can be placed in standby by pulling the
ENx pin low.
22
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a triple-synchronous step-down DC-DC converter. The device is typically used to convert a higher
DC voltage to lower DC voltages with continuous available output current of 3 A, 2 A, 2 A.
8.2 Typical Application
The following design procedure can be used to select component values for the TPS65268-Q1. This section
presents a simplified discussion of the design process.
C1
0.047uF
R1
L1
VOUT1 1.5V 3A
0
VIN 4.5 to 5.5V
VOUT1
VIN
C5
10uF
C6
10uF
C7
10uF
29
28
12
13
GND
VIN
PVIN1
PVIN2
PVIN3
GND
V7V
C9
1uF
C11
DNP
GND DNI
R8
30.1k
C15
270pF
C14
DNP
DNI
R10
24.9k
C18
330pF
C16
DNP
DNI
V7V
23
COMP1
7
COMP2
18
COMP3
BST1
25
LX1
26
ROSC
21
FB1
22
BST2
C19
180pF
31
32
1
EN1
EN2
EN3
GND
24
8
17
GND
EN1
EN2
EN3
SS1
SS2
SS3
C22
0.01uF
2
3
GND
GND
VFB1
6
L2
33
PAD
GND
4
AGND
FB3
GND
C17
GND
VFB2
VFB2
R14
16
15
GND
GND
C20
0.047uF
82pF
R13
10.0k
10.0k
L3
GND
0
VOUT3 2.5V 2A
VOUT3
20
19
VFB3
R30
C23 DNPC24
22uF
DNI
1uH
V7V
C26
GND
27
11
14
GND
VFB3
R22
22pF
R21
10.0k
31.6k
TPS65268-Q1
GND
VOUT2 1.2V 2A
VOUT2
100K
PGND1
PGND2
PGND3
R5
10.0k
C12 DNPC13
22uF
DNI
0.52uH
R15
AGND
AGND
47pF
15.0k
C10
0.047uF
R7
VFB1
R6
10
5
PGOOD
C25
0.01uF
20.5k
9
FB2
BST3
GND
GND
AGND
LX3
C21
0.01uF
C8
GND
R23
0
LX2
R12
46.4k
GND
30
C2 DNPC3
22uF
DNI
0.52uH
U1
C4
1uF
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 32. Typical Application Schematic
8.2.1 Design Requirements
This example details the design of triple-synchronous step-down converter. A few parameters must be known to
start the design process. These parameters are typically determined at the system level. For this example, start
with the known parameters listed in Table 2.
Table 2. Design Parameters
PARAMETER
VALUE
VOUT1
1.5 V
IOUT1
3A
VOUT2
1.2 V
IOUT2
2A
VOUT3
2.5 V
IOUT3
2A
Transient response 1-A load step
±5%
Input voltage
5 V normal, 4.5 to 5.5V
Output voltage ripple
±1%
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Table 2. Design Parameters (continued)
PARAMETER
VALUE
Switching frequency
2 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Inductor Selection
Use Equation 7 to calculate the value of the output inductor. LIR is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor-ripple currents impacts the selection of the output capacitor because
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for
the majority of applications. Use Equation 7 to calculate the value of the inductor.
VINmax VOUT
VOUT
L
u
IOUT u LIR
VINmax u fSW
(7)
For the output filter inductor, the RMS current and saturation current ratings must not be exceeded. Use
Equation 8 and to calculate RMS inductor current (ILrms) and peak inductor current (ILpeak).
ILrms
ILpeak
2
IOUT
IOUT
§ VOUT u VINmax VOUT
¨¨
VINmax u L u fSW
©
12
·
¸¸
¹
2
(8)
Iripple
2
where
Iripple
VINmax VOUT
VOUT
u
L
VINmax u fSW
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the peak inductor current level
calculated in Equation 9. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
8.2.2.2 Output Capacitor Selection
The three primary considerations for selecting the value of the output capacitor are:
• Output capacitor which determines the modulator pole
• Output voltage ripple
• How the regulator responds to a large change in load current
The output capacitance must be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation would occur if the desired hold-up times for the
regulator occur where the output capacitor must hold the output voltage above a certain level for a specified
amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient
output current if the current requirements of the load experience a large, fast increase, such as a transition from
no load to full load. The regulator typically requires two or more clock cycles for the control loop to experience a
change in load current and output voltage, and to adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for two clock cycles while only
allowing a tolerable amount of droop in the output voltage. Use Equation 10 to calculate the minimum output
capacitance (CO) required to accomplish this.
2 u 'IOUT
COUT
fSW u 'VOUT
24
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where
•
•
•
ΔIOUT is the change in output current
fsw is the regulators switching frequency
ΔVOUT is the allowable change in the output voltage
(10)
Equation 11 calculates the minimum output capacitance required to meet the output voltage ripple specification.
1
1
COUT !
u
VOUTripple
8 u fSW
IOUTripple
where
•
•
•
fSW is the switching frequency
VOUTripple is the maximum allowable output voltage ripple
IOUTripple is the inductor ripple current
(11)
Use Equation 12 to calculate the maximum ESR an output capacitor can have to meet the output voltage ripple
specification.
VOUTripple
Resr
IOUTripple
(12)
Additional capacitance deratings for aging, temperature, and DC bias should be factored in, which increase this
minimum value. Capacitors generally have limits to the amount of ripple current they can support without failing
or producing excess heat. The user must specify an output capacitor that can support the inductor ripple current.
Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Use
Equation 13 to calculate the RMS ripple current that the output capacitor must support (ICOUTrms).
VOUT u VINmax VOUT
ICOUTrms
12 u VINmax u L u fSW
(13)
8.2.2.3 Input Capacitor Selection
The TPS65268-Q1 device requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with at
least 10 µF of effective capacitance on the PVIN input voltage pins. In some applications, additional bulk
capacitance may also be required for the PVIN input. The effective capacitance includes any DC bias effects.
The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the TPS65268-Q1. Use
Equation 14 to calculate the input ripple current (IINrms ).
IINrms
IOUT u
V
VOUT
VOUT
u INmin
VINmin
VINmin
(14)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations because of temperature can be minimized by selecting a dielectric material
that is stable over temperature. Ceramic dielectric capacitors with type X5R and X7R are usually selected for
power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over
temperature. The DC bias must also be considered when selecting an output capacitor. The capacitance value of
a capacitor decreases as the DC bias across a capacitor increases. The input capacitance value determines the
input ripple voltage of the regulator. Use Equation 15 to calculate the input voltage ripple (ΔVIN).
I
u 0.25
'VIN OUT max
CIN u fSW
(15)
8.2.2.4 Loop Compensation
The TPS65268-Q1 device incorporates a peak current-mode control scheme. The error amplifier is a
transconductance amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a
phase margin from 40° to 90°. The Cb capacitor adds a high-frequency pole to attenuate high-frequency noise
when needed. To calculate the external compensation components, follow these steps:
1. Select a switching frequency, fSW, that is appropriate for the application depending on the inductor size,
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capacitor size, output ripple, EMI, and so forth. Selecting the switching frequency is a trade-off between
performance and cost. To achieve a smaller size and lower cost, a higher switching frequency is desired. To
optimize efficiency, a lower switching frequency is desired.
2. Set up the crossover frequency, fC, which is typically from 1/5 to 1/20 of fSW.
3. Use Equation 16 to calculate the value of RC.
2S u fC u VOUT u COUT
RC
Gm _ EA u Vref u GM _ PS
where
•
•
Gm_EA is the error amplifier gain (300 µS).
Gm_PS is the power stage voltage to current conversion gain (7.4 A/V).
(16)
4. Use Equation 17 to calculate the value Cc by placing a compensation zero at or before the dominant pole (
1
fp
COUT u RL u 2S ).
Cc
RL u COUT
RC
(17)
5. Optional: Use Equation 18 to calculate the value of CB capacitor to cancel the zero from the ESR associated
with CO.
Resr u COUT
Cb
RC
(18)
6. Optional: Implement type III compensation with the addition of one capacitor, C1. This implementation allows
for slightly higher loop bandwidths and higher phase margins. If used, used Equation 19 to calculate the
value of C1.
1
C1
2S u R1 u fC
(19)
LX
VOUT
IL
Resr
RL
C0
Current-Sense
I/V Converter
Gm_PS = 7.4 A/V
±
EA
+
COMP
R1
C1
VFB
Vref = 0.6 V
R2
RC
Cc
Cc
Gm_EA = 300 µS
Figure 33. DC-DC Loop Compensation
26
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8.2.3 Application Curves
IOUT = 3 A
IOUT = 2 A
Figure 34. BUCK1 Soft-Start
Figure 35. BUCK2 Soft-Start
IOUT = 3 A
IOUT = 2 A
Figure 36. BUCK3 Soft-Start
Figure 37. BUCK1 Output Voltage Ripple
IOUT = 2 A
IOUT = 2 A
Figure 38. BUCK2 Output Voltage Ripple
Figure 39. BUCK3 Output Voltage Ripple
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IOUT = 0.75 to 1.5 A
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SR = 0.25 A/µs
IOUT = 1.5 to 2.25 A
Figure 40. BUCK1 Load Transient
IOUT = 0.5 to 1 A
Figure 41. BUCK1 Load Transient
IOUT = 1 to 1.5 A
SR = 0.25 A/µs
SR = 0.25 A/µs
IOUT = 1 to 1.5 A
Figure 44. BUCK3 Load Transient
28
SR = 0.25 A/µs
Figure 43. BUCK2 Load Transient
Figure 42. BUCK2 Load Transient
IOUT = 0.5 to 1 A
SR = 0.25 A/µs
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Figure 45. BUCK3 Load Transient
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Figure 46. BUCK1 Hiccup and Recovery
Figure 47. BUCK2 Hiccup and Recovery
Figure 48. BUCK3 Hiccup and Recovery
Figure 49. PGOOD
Figure 50. 180° Out-of-Phase
Figure 51. Synchronization With External Clock
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VIN = 5 V, VOUT1 = 1.5 V/2 A, VOUT2 = 1.2 V/1.5 A,
VOUT3 = 2.5 V/1.5 A,
TA = 25°C EVM condition 4 layers, 75 mm × 75 mm
Figure 52. Thermal Signature of TPS65268-Q1EVM Operating
30
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 4 V to 8 V. This input power supply
should be well regulated. If the input supply is located more than a few inches from the TPS65268-Q1 converter,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 47 µF is a typical choice.
10 Layout
10.1 Layout Guidelines
Figure 53 shows the TPS65268-Q1 layout example on a 2-layer printed circuit board (PCB).
Layout is a critical portion of good power-supply design. The top layer contains the main power traces for PVIN,
VOx, and LX. The top layer also has connections for the remaining pins of the TPS65268-Q1 device and a large
top-side area filled with ground. The top-layer ground area should be connected to the bottom-layer ground using
vias at the input bypass capacitor, the output filter capacitor, and directly under the TPS65268-Q1 device to
provide a thermal path from the exposed thermal pad land to ground. The bottom layer acts as ground plane
connecting analog ground and power ground.
For operation at full rated load, the top-side ground area together with the bottom-side ground plane must
provide adequate heat dissipating area. Several signals paths conduct fast changing currents or voltages that
can interact with stray inductance or parasitic capacitance to generate noise or degrade the performance of the
power supplies. To help eliminate these problems, bypass the PVIN pin to ground with a low-ESR ceramic
bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass
capacitor connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to
ground using a low-ESR ceramic capacitor with X5R or X7R dielectric.
Because the LX connection is the switching node, the output inductor should be located close to the LXx pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter
capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize
this conductor length while maintaining adequate width. The small signal components should be grounded to the
analog ground path.
The FB and COMP pins are sensitive to noise so the resistors and capacitors should be located as close as
possible to the device and routed with minimal lengths of trace. The additional external components can be
placed approximately as shown in Figure 53.
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10.2 Layout Example
VO1
SS3
COMP3
FB3
PGOOD
ROSC
FB1
COMP1
SS1
VO3
BST3
BST1
LX3
LX1
PVIN3
VIN
PVIN2
PVIN
SS2
COMP2
FB2
BST2
AGND
LX2
EN2
AGND
PGND2
AGND
V7V
EN1
EN3
VIN
PGND3
PVIN1
AGND
PVIN
PGND1
VO2
TOPSIDE
GROUND
AREA
0.010-inch Diameter
Thermal VIA to Ground Plane
VIA to Ground Plane
Figure 53. PCB Layout
32
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65268QRHBRQ1
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
268-1Q
TPS65268QRHBTQ1
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
268-1Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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