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TPS65263-Q1
SLVSCS9C – DECEMBER 2014 – REVISED NOVEMBER 2015
TPS65263-Q1 4.0- to 18-V Input Voltage, 3-A/2-A/2-A Output Current Triple Synchronous
Step-Down Converter With I2C Controlled Dynamic Voltage Scaling
1 Features
3 Description
•
•
The TPS65263-Q1 incorporates triple-synchronous
buck converters with 4.0- to 18-V wide input voltage.
The converter with constant frequency peak current
mode is designed to simplify its application while
giving designers options to optimize the system
according to targeted applications. The switching
frequency of the converters is adjustable from 200
kHz to 2.3 MHz with an external resistor. 180° out-ofphase operation between buck1 and buck2, buck3
(buck2 and buck3 run in phase) minimizes the input
filter requirements.
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualification With the Following
Results:
– Device Temperature Grade 1: –40°C to 125°C
Operating Junction Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Operating Input Voltage Range 4.0- to 18-V
Maximum Continuous Output Current 3 A/2 A/2 A
I2C Controlled 7-Bits VID Programmable Output
Voltage from 0.68 to 1.95 V With 10-mV Voltage
Step for Buck2
I2C Controlled VID Voltage Transition Slew Rate
for Buck2
I2C Read Back Power Good Status, Overcurrent
Warning and Die Temperature Warning
I2C Compatible Interface With Standard Mode
(100 kHz) and Fast Mode (400 kHz)
Feedback Reference Voltage 0.6 V ±1%
Adjustable Clock Frequency from 200 kHz to
2.3 MHz
External Clock Synchronization
Dedicated Enable and Soft-Start Pins for Each
Buck
Output Voltage Power Good Indicator
Thermal Overloading Protection
Each buck in TPS65263-Q1 can be I2C controlled for
enabling/disabling output voltage, setting the pulse
skipping mode (PSM) or forced continuous current
(FCC) mode at light load condition and reading the
power-good status, overcurrent warning, and die
temperature warning.
The TPS65263-Q1 features overvoltage, overcurrent,
short-circuit, and overtemperature protection.
Device Information(1)
PART NUMBER
TPS65263-Q1
Automotive
Car Audio/Video
Home Gateway and Access Point Networks
Surveillance
Application Schematic
PVINx
LX1
100%
VIN
90%
TPS65263Q1
FB1
PGOOD
ENx
SSx
DVCC
80%
LX2
VOUT2
ROSC
FB2
Vout3
SDA
SCL
70%
Vout2
Efficiency
Vout2
BODY SIZE (NOM)
5.00 mm × 5.00 mm
Efficiency vs Output Load
Vout1
Vin
PACKAGE
VQFN (32)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
The initial startup voltage of each buck can be set
with external feedback resistors. The output voltage
of buck2 can be dynamically scaled from 0.68 to 1.95
V in 10-mV steps with I2C-controlled 7 bits VID. The
VID voltage transition slew rate is programmable with
3-bits control through I2C bus to optimize
overshoot/undershoot during VID voltage transition.
LX3
SDA
60%
50%
40%
30%
20%
SCL
FB3
AGND
PGND
VIN 12 V VOUT 3.3 V
VIN 5 V VOUT 3.3 V
10%
0
0.01
0.02
0.05
0.1
0.2 0.3 0.5 0.7 1
Output Load (A)
2
3
D002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65263-Q1
SLVSCS9C – DECEMBER 2014 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 24
7.5 Register Maps ........................................................ 26
8
Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Application ................................................. 29
9 Power Supply Recommendations...................... 37
10 Layout................................................................... 37
10.1 Layout Guidelines ................................................. 37
10.2 Layout Example .................................................... 38
11 Device and Documentation Support ................. 39
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
39
12 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2015) to Revision C
Page
•
Added more pin information for SDA and SCL ..................................................................................................................... 3
•
Added more information about SDA and SCL pins ............................................................................................................. 12
•
Added Community Resources ............................................................................................................................................. 39
Changes from Revision A (January 2015) to Revision B
•
Page
Updated device status to production data ............................................................................................................................. 1
Changes from Original (December 2014) to Revision A
Page
•
Changed feedback reference voltage from 0.6 V ±2% to 0.6 V ±1% in Features ................................................................. 1
•
Updated values for feedback voltage, PGOOD pin leakage, V7V LDO output voltage, buck1 low-side sink current
limit, and buck2/buck3 low-side sink current limit in Electrical Characteristics ...................................................................... 6
•
Updated current value in PSM, Equation 6, and Figure 30 ................................................................................................. 21
2
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SLVSCS9C – DECEMBER 2014 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
SS1
COMP1
FB1
ROSC
PGOOD
FB3
COMP3
SS3
RHB Package
32-Pin VQFN
Top View
24
23
22
21
20
19
18
17
BST1 25
16 BST3
LX1 26
15 LX3
14 PGND3
PGND1 27
13 PVIN3
PVIN1 28
Thermal Pad
VIN 29
12 PVIN2
V7V 30
11 PGND2
EN1 31
10 LX2
9
4
5
6
7
8
VOUT2
FB2
COMP2
SS2
SDA
3
AGND
2
SCL
1
EN3
EN2 32
BST2
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.
Pin Functions
PIN
NAME
DESCRIPTION
NO.
EN3
1
Enable for buck3. Float to enable. Can use this pin to adjust the input UVLO of buck3 with a resistor divider.
SDA
2
I2C interface data pin; float or connect to GND to disable I2C communication
SCL
3
I2C interface clock pin; float or connect to GND to disable I2C communication
AGND
4
Analog ground common to buck controllers and other analog circuits. It must be routed separately from high-current
power grounds to the (–) terminal of bypass capacitor of input voltage VIN.
VOUT2
5
Buck2 output voltage sense pin
FB2
6
Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
COMP2
7
Error amplifier output and loop compensation pin for buck2. Connect a series resistor and capacitor to compensate the
control loop of buck2 with peak current PWM mode.
SS2
8
Soft-start and tracking input for buck2. An internal 5.2-µA pullup current source is connected to this pin. The soft-start
time can be programmed by connecting a capacitor between this pin and ground.
BST2
9
Boot-strapped supply to the high-side floating gate driver in buck2. Connect a capacitor (recommend 47 nF) from BST2
pin to LX2 pin.
LX2
10
Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a
diode voltage below the ground up to PVIN2 voltage.
PGND2
11
Power ground connection of buck2. Connect PGND2 pin as close as practical to the (–) terminal of VIN2 input ceramic
capacitor.
PVIN2
12
Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
PVIN3
13
Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
PGND3
14
Power ground connection of buck3. Connect PGND3 pin as close as practical to the (–) terminal of VIN3 input ceramic
capacitor.
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Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
LX3
15
Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a
diode voltage below the ground up to PVIN3 voltage.
BST3
16
Boot-strapped supply to the high-side floating gate driver in buck3. Connect a capacitor (recommend 47 nF) from BST3
pin to LX3 pin.
SS3
17
Soft-start and tracking input for buck3. An internal 5.2-µA pullup current source is connected to this pin. The soft-start
time can be programmed by connecting a capacitor between this pin and ground.
COMP3
18
Error amplifier output and loop compensation pin for buck3. Connect a series resistor and capacitor to compensate the
control loop of buck3 with peak current PWM mode.
FB3
19
Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.
PGOOD
20
Output voltage supervision pin. When all bucks are in PGOOD monitor’s regulation range, PGOOD is asserted high.
ROSC
21
Clock frequency adjustment pin. Connect a resistor from this pin to ground to adjust the clock frequency. When
connected to an external clock, the internal oscillator synchronizes to the external clock.
FB1
22
Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.
COMP1
23
Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the
control loop of buck1 with peak current PWM mode.
SS1
24
Soft-start and tracking input for buck1. An internal 5.2-µA pullup current source is connected to this pin. The soft-start
time can be programmed by connecting a capacitor between this pin and ground.
BST1
25
Boot-strapped supply to the high-side floating gate driver in buck1. Connect a capacitor (recommend 47 nF) from BST1
pin to LX1 pin.
LX1
26
Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a
diode voltage below the ground up to PVIN1 voltage.
PGND1
27
Power ground connection of buck1. Connect PGND1 pin as close as practical to the (–) terminal of VIN1 input ceramic
capacitor.
PVIN1
28
Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
VIN
29
Buck controller power supply
V7V
30
Internal LDO for gate driver and internal controller. Connect a 1-µF capacitor from the pin to power ground.
EN1
31
Enable for buck1. Float to enable. Can use this pin to adjust the input UVLO of buck1 with a resistor divider.
EN2
32
Enable for buck2. Float to enable. Can use this pin to adjust the input UVLO of buck2 with a resistor divider.
PAD
—
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.
4
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SLVSCS9C – DECEMBER 2014 – REVISED NOVEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)
MIN
MAX
UNIT
PVIN1, PVIN2, PVIN3,VIN
–0.3
20
V
LX1, LX2, LX3 (Maximum withstand voltage transient < 20 ns)
–1.0
20
V
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively
–0.3
7
V
EN1, EN2, EN3, V7V, VOUT2, SCL, SDA, PGOOD
–0.3
7
V
FB1, FB2, FB3, COMP1 , COMP2, COMP3, ROSC, SS1, SS2, SS3
–0.3
3.6
V
AGND, PGND1, PGND2, PGND3
–0.3
0.3
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all -2000 2000 pins
(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PVIN1, PVIN2, PVIN3,VIN
TJ
MIN
MAX
4
18
UNIT
V
LX1, LX2, LX3 (Maximum withstand voltage transient 500 mV.
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The EN pin has a small pullup current, Ip, which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih after the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 2 and Equation 3.
R1
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
è VENRISING ø
=
æ
ö
V
IP ç 1 - ENFALLING ÷ + Ih
VENRISING ø
è
R2 =
(2)
R1 ´ VENFALLING
(
VSTOP - VENFALLING + R1 Ih + Ip
)
where
•
•
•
•
Ih = 3 µA
Ip = 3.9 µA
VENRISING = 1.2 V
VENFALLING = 1.15 V
(3)
VIN
PVIN
i
i
h
h
R1
R1
i
i
p
EN
p
EN
R2
R2
Figure 23. Adjustable VIN UVLO
Figure 24. Adjustable PVIN UVLO, VIN > 4 V
PVIN
VIN
i
h
R1
i
p
EN
R2
Figure 25. Adjustable VIN and PVIN UVLO
16
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7.3.3 Soft-Start Time
The voltage on the respective SS pin controls the startup of buck output. When the voltage on the SS pin is less
than the internal 0.6-V reference, The TPS65263-Q1 regulates the internal feedback voltage to the voltage on
the SS pin instead of 0.6 V. The SS pin can be used to program an external soft-start function or to allow output
of buck to track another supply during start-up. The device has an internal pullup current source of 5.2 µA
(typical) that charges an external soft-start capacitor to provide a linear ramping voltage at the SS pin. The
TPS65263-Q1 regulates the internal feedback voltage to the voltage on the SS pin, allowing VOUT to rise
smoothly from 0 V to its regulated voltage without inrush current. The soft-start time can be calculated
approximately by Equation 4.
Css(nF) ´ Vref( V)
Tss(ms) =
Iss(mA )
(4)
Many of the common power-supply sequencing methods can be implemented using the SSx and ENx pins.
Figure 26 shows the method implementing ratiometric sequencing by connecting the SSx pins of three buck
channels together. The regulator outputs ramp up and reach regulation at the same time. When calculating the
soft-start time, the pullup current source must be tripled in Equation 4.
EN
31
EN threshold = 1.2 V
EN1
32
EN2
1
EN3
Vout3 = 2.5 V
24
SS1
Vout1 1.5 V
8
SS2
Vout2 1.2 V
17
SS3
Css
t SS =
CSS × 0.6 V
15.6 µA
Figure 26. Ratiometric Power-Up Using SSx Pins
The user can implement simultaneous power-supply sequencing by connecting the capacitor to the SSx pin,
shown in Figure 27. Using Equation 4 and Equation 5, the capacitors can be calculated.
Css1
Css2
Css3
=
=
Vout1 Vout2 Vout3
(5)
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EN
31
EN1
EN threshold = 1.2 V
32
EN2
1
EN3
Vout3 = 2.5 V
24
SS1
Css1
Vout1 1.5 V
8
SS2
Css2
Vout2 1.2 V
17
SS3
Css3
t SS =
CSS 3 × 0.6 V
5.2 µA
Figure 27. Simultaneous Startup Sequence Using SSx Pins
7.3.4 Power-Up Sequencing
The TPS65263-Q1 has a dedicated enable pin and soft-start pin for each converter. The converter enable pins
are biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling
the converter with an active pulldown transistor on the ENx pin allows for predictable power-down timing
operation. Figure 28 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor
at the ENx pin.
A typical 1.4-µA current is charging the ENx pin from input supply. When the ENx pin voltage rises to typical 0.4
V, the internal V7V LDO turns on. A 3.9-µA pullup current is sourcing ENx. After the ENx pin voltage reaches the
ENx enabling threshold, a 3.0-µA hysteresis current sources to the pin to improve noise sensitivity. The internal
soft-start comparator compares the SS pin voltage to 1.2 V. When the SS pin voltage ramps up to 1.2 V,
PGOOD monitor is enabled. After PGOOD deglitch time, PGOOD is deasserted. The SS pin voltage is eventually
clamped around 2.1 V.
18
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VIN
V7V
EN Threshold
ENx Rise Time
Dictated by CEN
1.2 V
EN
Threshold
Charge CEN
with 6.9 µA
t = CSS × 0.6 V/5.2 µA
ENx
Soft Start Rise Time
Dictated by CSS
0.4 V
About 2.1 V
1.2 V
0.6 V
SSx
Pre-Bias Startup
VOUTx
PGOOD Deglitch Time
t = CENx × (1.2 ± 0.4) V/3.9 µA
t = CSS × 1.2 V/5.2 µA
t = CENx × 0.4 V/1.4 µA
PGOOD
Figure 28. Startup Power Sequence
7.3.5 V7V Low-Dropout Regulator and Bootstrap
Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V
pin. The internal built-in low-dropout linear regulator (LDO) supplies 6.3 V (typical) from VIN to V7V. The user
should connect a 1-µF ceramic capacitor from V7V pin to power ground.
If the input voltage, VIN, decreases to the UVLO threshold voltage, the UVLO comparator detects the V7V pin
voltage and forces the converter off.
Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in Figure 29, which is
normally recharged during each cycle through an internal low-side MOSFET or the body diode of a low-side
MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less
than VIN and BST-LX voltage is below regulation. TI recommends a 47-nF ceramic capacitor. TI recommends a
ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher because of the
stable characteristics over temperature and voltage. Each low-side MOSFET driver is powered from the V7V pin
directly.
To improve dropout, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage
is greater than the BST-LX UVLO threshold, which is typically 2.1 V. When the voltage between BST and LX
drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is
turned on allowing the boot capacitor to be recharged.
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VIN
PVINx
LDO
+
(VBSTx-VLXx)
±
+2.1 V
nBootUV
V7V
Cbias
1 uF
BSTx
UVLO
Bias
Buck Controller
High-side
MOSFET
nBootUV
CB
Gate Driver
PWM
LXx
Low-side
MOSFET
nBootUV
BootUV
Protection
PWM
Gate Driver
Clk
Figure 29. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram
7.3.6 Out-of-Phase Operation
To reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and buck3.
This enables the system having less input current ripple to reduce input capacitors’ size, cost, and EMI.
20
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7.3.7 Output Overvoltage Protection (OVP)
The device incorporates an OVP circuit to minimize output voltage overshoot. When the output is overloaded, the
error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower
than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum
output current. After the condition is removed, the regulator output rises and the error amplifier output transitions
to the steady-state voltage. In some applications with small output capacitance, the load can respond faster than
the error amplifier. This leads to the possibility of an output overshoot. Each buck compares the FB pin voltage to
the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET is turned off
preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower
than the OVP threshold, the high-side MOSFET turns on at the next clock cycle.
7.3.8 PSM
The TPS65263-Q1 can enter high-efficiency PSM operation at light load current. To disable PSM operation, set
the VOUTx_COM registers’ bit 1 to '1' through I2C interface.
When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 310-mA
current typically. Because the integrated current comparator catches the peak inductor current only, the average
load current entering PSM varies with the applications and external output filters. In PSM, the sensed peak
inductor current is clamped at 310 mA, shown in Figure 30.
When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current
comparator turns off the low-side MOSFET when the inductor current reaches 0, preventing it from reversing and
going negative.
Due to the delay in the circuit and current comparator, tdly (typical 50 nS at Vin = 12 V), the real peak inductor
current threshold to turn off high-side power MOSFET could shift higher depending on inductor inductance and
input/output voltages. Calculate the threshold of peak inductor current to turn off high-side power MOSFET with
Equation 6.
Vin - Vout
´ tdly
ILPEAK = 310 mA +
(6)
L
After the charge accumulated on the Vout capacitor is more than loading need, the COMP pin voltage drops to a
low voltage driven by the error amplifier. There is an internal comparator at COMP pin. If the comp voltage is
´
8 ´ ƒ sw Voripple
Ioripple
where
•
•
•
ƒsw is the switching frequency
Voripple is the maximum allowable output voltage ripple
Ioripple is the inductor ripple current
(13)
Equation 14 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification.
Voripple
Re sr <
Ioripple
(14)
Additional capacitance deratings for aging, temperature, and DC bias should be factored in, which increases this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. The user must specify an output capacitor that can support the inductor ripple current.
Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Use
Equation 15 to calculate the RMS ripple current the output capacitor needs to support.
Icorms =
Vout ´ (Vinmax - Vout )
12 ´ Vinmax ´ L ´ ƒ sw
(15)
8.2.2.3 Input Capacitor Selection
The TPS65263-Q1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 µF
of effective capacitance on the PVIN input voltage pins. In some applications, additional bulk capacitance may
also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of
the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple
current rating greater than the maximum input current ripple of the TPS65263-Q1. The input ripple current can be
calculated using Equation 16.
Iinrms = Iout ´
(Vinmin - Vout )
Vout
´
Vinmin
Vinmin
(16)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple
voltage of the regulator. Use Equation 17 to calculate the input voltage ripple.
I
´ 0.25
DVin = out max
Cin ´ ƒ sw
(17)
8.2.2.4 Loop Compensation
The TPS65263-Q1 incorporates a peak current mode control scheme. The error amplifier is a transconductance
amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase margin
between 40° and 90°. Cb adds a high-frequency pole to attenuate high-frequency noise when needed. To
calculate the external compensation components, follow these steps.
1. Select switching frequency, ƒsw, that is appropriate for application depending on L and C sizes, output ripple,
EMI, and so forth. Switching frequency between 500 kHz to 1 MHz gives best trade-off between performance
and cost. To optimize efficiency, lower switching frequency is desired.
2. Set up crossover frequency, ƒc, which is typically between 1/5 and 1/20 of ƒsw.
3. RC can be determined by:
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RC =
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2p ´ ƒc ´ Vo ´ Co
Gm-EA ´ Vref ´ Gm-PS
where
•
•
Gm_EA is the error amplifier gain (300 µS).
Gm_PS is the power stage voltage to current conversion gain (7.4 A/V).
(18)
æ
ç ƒp =
4. Calculate CC by placing a compensation zero at or before the dominant pole è
R ´ Co
CC = L
RC
1
Co ´ RL
ö
÷
´ 2p ø .
(19)
5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
R
´ Co
Cb = ESR
RC
(20)
6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly
higher loop bandwidths and higher phase margins. If used, calculate C1 from Equation 21.
C1 =
1
S î 51 u ¦C
(21)
LX
VOUT
iL
Current Sense
I/V Converter
RESR
RL
Gm _ PS
7.4 A / V
Co
C1
R1
±
COMP
FB
Vfb
EA
+
Vref
0.6 V
R2
Rc
Gm _ EA
300 uS
Cb
Cc
Figure 43. DC/DC Loop Compensation
32
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8.2.3 Application Curves
Iout = 3 A
Iout = 2 A
Figure 44. BUCK1, Soft-Start
Figure 45. BUCK2, Soft-Start
Iout = 2 A
Iout = 3 A
Figure 46. BUCK3, Soft-Start
Figure 47. BUCK1, Output Voltage Ripple
Iout = 2 A
Iout = 2 A
Figure 48. BUCK2, Output Voltage Ripple
Figure 49. BUCK3, Output Voltage Ripple
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0.75 to 1.5 A
SR = 0.25 A/µs
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1.5 to 2.25 A
Figure 50. BUCK1, Load Transient
0.5 to 1.0 A
SR = 0.25 A/µs
Figure 51. BUCK1, Load Transient
1.0 to 1.5 A
Figure 52. BUCK2, Load Transient
0.5 to 1.0 A
SR = 0.25 A/µs
SR = 0.25 A/µs
Figure 53. BUCK2, Load Transient
1.0 to 1.5 A
Figure 54. BUCK3, Load Transient
34
SR = 0.25 A/µs
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SR = 0.25 A/µs
Figure 55. BUCK3, Load Transient
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Figure 56. BUCK1, Hiccup and Recovery
Figure 57. BUCK2, Hiccup and Recovery
Figure 58. BUCK3, Hiccup and Recovery
Figure 59. PGOOD
Figure 60. VID2 from 00 to 7F, SR = 10 mV/Cycle
Figure 61. VID2 from 7F to 00, SR = 10 mV/Cycle
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Figure 62. 180° Out-of-Phase
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Figure 63. Synchronization With External Clock
VIN = 12 V, VOUT1 = 1.5 V/3 A, VOUT2 = 1.2 V/2 A,
VOUT3 = 2.5 V/2 A,
TA = 26.8°C EVM condition 4 layers, 75 mm × 75 mm
Figure 64. Operation at VIN Drop to 2.5 V
36
Figure 65. Thermal Signature of TPS65263-Q1EVM
Operating
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9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4 and 18 V. This input power
supply should be well regulated. If the input supply is located more than a few inches from the TPS65263-Q1
converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 47 µF is a typical choice.
10 Layout
10.1 Layout Guidelines
Figure 66 shows the TPS65263-Q1 on a 2-layer PCB.
Layout is a critical portion of good power-supply design. See Figure 66 for a PCB layout example. The top
contains the main power traces for PVIN, VOUT, and LX. The top layer also has connections for the remaining
pins of the TPS65263-Q1 and a large top-side area filled with ground. The top-layer ground area should be
connected to the bottom layer ground using vias at the input bypass capacitor, the output filter capacitor, and
directly under the TPS65263-Q1 device to provide a thermal path from the exposed thermal pad land to ground.
The bottom layer acts as ground plane connecting analog ground and power ground.
For operation at full rated load, the top-side ground area together with the bottom-side ground plane must
provide adequate heat dissipating area. Several signals paths conduct fast changing currents or voltages that
can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies'
performance. To help eliminate these problems, bypass the PVIN pin to ground with a low-ESR ceramic bypass
capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor
connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a
low-ESR ceramic capacitor with X5R or X7R dielectric.
Because the LX connection is the switching node, the output inductor should be located close to the LX pins, and
the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor
ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this
conductor length while maintaining adequate width. The small signal components should be grounded to the
analog ground path.
The FB and COMP pins are sensitive to noise so the resistors and capacitors should be located as close as
possible to the IC and routed with minimal lengths of trace. The additional external components can be placed
approximately as shown.
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10.2 Layout Example
VOUT1
SS3
FB3
COMP3
PGOOD
ROSC
FB1
SS1
COMP1
VOUT3
BST3
BST1
LX2
EN2
BST2
PVIN
SS2
PGND2
EN1
COMP2
V7V
FB2
PVIN2
VOUT2
PVIN3
VIN
AGND
PVIN1
SCL
PGND3
EN3
VIN
LX3
PGND1
SDA
PVIN
LX1
VOUT2
TOPSIDE
GROUND
AREA
0.010-inch Diameter
Thermal VIA to Ground Plane
VIA to Ground Plane
Figure 66. PCB Layout
38
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65263QRHBRQ1
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
65263Q
TPS65263QRHBTQ1
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
65263Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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