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TPS65631
SLVSBK1E – SEPTEMBER 2012 – REVISED MAY 2014
TPS65631 Dual-Output AMOLED Display Power Supply
1 Features
3 Description
•
•
•
•
•
The TPS65631 is designed to drive AMOLED (Active
Matrix Organic Light Emitting Diode) displays
requiring positive and negative supply rails. The
device integrates a boost converter for VPOS and an
inverting buck boost converter for VNEG and is
suitable for battery-operated products. The digital
control pin (CTRL) allows programming the negative
output voltage in digital steps. The TPS65631 uses a
novel technology enabling excellent line transient
performance.
1
•
•
•
•
•
2.9-V to 4.5-V Input Voltage Range
Fixed 4.6-V Positive Output Voltage
0.5% VPOS Accuracy from 25ºC to 85ºC
Separate VPOS Output Sense Pin
Negative Output Voltage Digitally Programmable
from –1.4 V to –4.4 V (–4 V Default)
Output Currents up to 250 mA Supported
Excellent Line Transient Regulation
Short-Circuit Protection
Thermal Shutdown
Available in 3.00-mm × 3.00-mm, 12-Pin QFN
Package
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS65631
QFN (12)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet
2 Applications
spacer
AMOLED Displays
spacer
spacer
spacer
spacer
4 Simplified Schematic
L1
4.7 µH
PVIN
SWP
AVIN
OUTP
C1
2×10 µF
FBS
TPS65631
80
CTRL
EN / Program VNEG
C4
100 nF
OUTN
CT
C3
2×10 µF
PGND
AGND
GND
90
VPOS
4.6 V, 300 mA
C2
10 µF
SWN
VNEG
±4.0 V, 300 mA
Efficiency (%)
VI
2.9 V to 4.5 V
Efficiency vs Output Current
100
70
60
50
40
30
L2
4.7 µH
20
VPOS = 4.6 V
VNEG = –4.0 V
10
0
0
50
VI = 3.7 V
100
150
200
Output Current (mA)
250
300
G000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65631
SLVSBK1E – SEPTEMBER 2012 – REVISED MAY 2014
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
6
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 12
9
Applications and Implementation ...................... 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
5 Revision History
2
DATE
REVISION
NOTES
May 2014
E
No legacy rev history for rev E – first public release
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SLVSBK1E – SEPTEMBER 2012 – REVISED MAY 2014
6 Pin Configuration and Functions
DPD PACKAGE
(TOP VIEW)
SWP
1
12
PVIN
PGND
2
11
AVIN
OUTP
3
10
SWN
FBS
4
9
OUTN
AGND
5
8
CT
GND
6
7
CTRL
DPD PACKAGE
(BOTTOM VIEW)
PVIN
12
1
SWP
AVIN
11
2
PGND
SWN
10
3
OUTP
OUTN
9
4
FBS
CT
8
5
AGND
CTRL
7
6
GND
Pin Functions
NAME
NO.
I/O
AGND
5
—
Analog ground.
DESCRIPTION
AVIN
11
—
Input supply voltage for internal analog circuits (both converters).
CT
8
I/O
Timing capacitor pin. Connect a capacitor between this pin and ground to
control the time it takes for the output of the inverting buck-boost converter to
ramp from one value of VNEG to another.
CTRL
7
I
Control pin. Combined device enable and inverting buck-boost converter output
voltage programming pin.
FBS
4
I
Feedback sense pin of the boost converter output voltage.
GND
6
—
Ground. (Note: it is possible to leave this pin floating without affecting device
performance.)
PGND
2
—
Power ground of the boost converter.
PVIN
12
—
Input supply voltage pin for the inverting buck-boost converter.
SWN
10
O
Switch pin of the inverting buck-boost converter.
SWP
1
O
Switch pin of the boost converter.
OUTN
9
O
Rectifier pin of the inverting buck-boost converter.
OUTP
3
O
Rectifier pin of the boost converter.
Exposed Thermal
Pad
13
—
Connect this pad to AGND and PGND.
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7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Input voltage
(2)
(1)
MIN
MAX
SWP, OUTP, FBS, PVIN, AVIN
–0.3
6
V
OUTN
–0.3
–6
V
SWN
–6
6
V
CTRL
–0.3
5.5
V
CT
–0.3
3.6
V
–40
150
°C
Operating junction temperature range, TJ
(1)
(2)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
With respect to GND pin.
7.2 Handling Ratings
TSTG
MIN
MAX
UNIT
–65
150
°C
–2
2
kV
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–500
500
V
Machine model (MM) ESD stress voltage
–200
200
V
Storage temperature range
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins (1)
VESD
(1)
(2)
Electrostatic discharge
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process..
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VI
Input supply voltage range
MIN
NOM
MAX
2.9
3.7
4.5
VPOS
UNIT
V
4.6
VO
Output voltage range
IO
Output current range
TA
Operating ambient temperature
–40
25
85
°C
TJ
Operating junction temperature
–40
85
125
°C
VNEG
–4.4
–4
V
–1.4
IPOS
300
INEG
300
mA
7.4 Thermal Information
THERMAL METRIC (1)
PD
12 PINS
RθJA
Junction-to-ambient thermal resistance
51.5
RθJCtop
Junction-to-case (top) thermal resistance
47.1
RθJB
Junction-to-board thermal resistance
25.0
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
25.2
RθJCbot
Junction-to-case (bottom) thermal resistance
4.4
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
VI = 3.7 V, V(CTRL) = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
II
Shutdown current into AVIN and
PVIN
VUVLO
Undervoltage lockout threshold
CTRL pin connected to ground.
0.1
µA
VI rising.
2.4
VI falling.
2.1
V
BOOST CONVERTER
Output voltage
VO
rDS(ON)
Output voltage tolerance
4.6
25°C ≤ TA ≤ 85°C, no load
–0.5%
–40°C ≤ TA < 85°C, no load
–0.8%
V
0.5%
0.8%
Switch (low-side) on-resistance
I(SWP) = 200 mA
200
Rectifier (high-side) on-resistance
I(SWP) = 200 mA
350
Switching frequency
IO = 200 mA
Switch current limit
Inductor valley current
Short-circuit threshold voltage in
operation
VO falling
mΩ
1.7
0.8
Short-circuit detection time during
operation
MHz
1
A
4.1
V
3
ms
Output sense threshold voltage
using OUTP
V(OUTP) - V(FBS) increasing
300
mV
Output sense threshold voltage
using FBS
V(OUTP) - V(FBS) decreasing
200
mV
Input resistance of FBS
Between FBS pin and ground
4
MΩ
Discharge resistance
CTRL pin connected to ground,
IO = 1 mA
30
Ω
Line regulation
IO = 200 mA
Load regulation
0.002
%/V
0.01
%/A
INVERTING BUCK-BOOST CONVERTER
Output voltage default
VO
–4.0
Output voltage range
–4.4
Output voltage tolerance
rDS(ON)
–0.05
I(SWN) = 200 mA
200
Rectifier (low-side) on-resistance
I(SWN) = 200 mA
300
Switching frequency
IO = 10 mA
Switch current limit
VI = 2.9 V
1.5
Short-circuit threshold voltage during
start-up
V
0.05
Switch (high-side) on-resistance
Short-circuit threshold voltage during
Voltage drop from nominal VO
operation
tSCP
–1.4
mΩ
1.7
MHz
2.2
A
500
mV
180
200
230
Short-circuit detection time during
start-up
10
ms
Short-circuit detection time during
operation
3
ms
150
Ω
Discharge resistance
CTRL pin connected to ground,
IO = 1 mA
Line regulation
IO = 200 mA
Load regulation
0.006
%/V
0.31
%/A
CTRL
High-level threshold voltage
1.2
Low-level threshold voltage
0.4
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V
5
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Electrical Characteristics (continued)
VI = 3.7 V, V(CTRL) = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless
otherwise noted)
MIN
TYP
MAX
UNIT
Pull-down resistance
PARAMETER
TEST CONDITIONS
150
400
860
kΩ
R(CT)
CT pin output resistance
150
300
500
kΩ
tINIT
Initialization time
300
400
µs
tOFF
Shut-down time
30
80
µs
tSTORE
Data storage time
30
TSD
Thermal shutdown temperature
OTHER
80
145
µs
°C
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
CTRL Interface
tHIGH
High-level pulse duration
2
10
25
µs
tLOW
Low-level pulse duration
2
10
25
µs
6
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7.7 Typical Characteristics
4.0
0.50
3.5
0.45
3.0
0.40
2.5
0.35
Resistance (Ω)
Current (µA)
At TA = 25°C, unless otherwise noted.
2.0
1.5
1.0
0.5
0.30
0.25
0.20
0.15
0.0
0.10
−0.5
0.05
−1.0
−50
−25
0
25
50
75
Junction Temperature (°C)
100
0.00
−50
125
0.9
0.45
0.8
0.40
0.7
0.35
0.6
0.5
0.4
0.3
0.15
0.05
125
0.00
−50
−25
G003
Figure 3. Boost Converter Rectifier rDS(ON)
G002
0.20
0.10
100
125
0.25
0.1
0
25
50
75
Junction Temperature (°C)
100
0.30
0.2
−25
0
25
50
75
Junction Temperature (°C)
Figure 2. Boost Converter Switch rDS(ON)
0.50
Resistance (Ω)
Resistance (Ω)
Figure 1. Shutdown Current into AVIN and PVIN
1.0
0.0
−50
−25
G001
0
25
50
75
Junction Temperature (°C)
100
125
G004
Figure 4. Inverting Buck-Boost Converter Switch rDS(ON)
0.50
0.45
Resistance (Ω)
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
−50
−25
0
25
50
75
Junction Temperature (°C)
100
125
G005
Figure 5. Inverting Buck-Boost Converter Rectifier rDS(ON)
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8 Detailed Description
8.1 Overview
The TPS65631 consists of a boost converter and an inverting buck boost converter. The VPOS output is fixed at
4.6 V and VNEG output is programmable via a digital interface in the range of -1.4 V ~ -4.4 V, the default is -4 V.
The transition time of VNEG output is adjustable by the CT pin capacitor.
8.2 Functional Block Diagram
SWP
OUTP
1
3
DCHG
VPOS
Short-Circuit
Protection
Gate Driver
FBS
PGND
SWP
PWM Control
+
11
±
AVIN
VI
Output Sense
Control
CTRL
Oscillator
4
VREF
Short-Circuit
Protection
±
CT
CT
Control
8
+
DAC
+
Constant Off-Time
Controller
Gate
Drive
±
Digital
Interface
50 mV
DCHG
PVIN
OUTN
12
9
6
GND
5
AGND
10
SWN
7
CTRL
2
VNEG
PGND
8.3 Feature Description
8.3.1 Boost Converter
The boost converter uses a fixed-frequency current-mode topology, and its output voltage (VPOS) is fixed at 4.6 V
For the highest output voltage accuracy, connect the output sense pin (FBS) directly to the positive pin of the
output capacitor. If not used, the FBS pin can be left floating or connected to ground. If the FBS pin is not used,
the boost converter senses its output voltage using the OUTP pin.
8
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Feature Description (continued)
8.3.2 Inverting Buck-Boost Converter
The inverting buck-boost converter uses a constant-off-time peak-current mode topology. The converter's default
output voltage (VNEG) is –4 V, but it can be programmed to any voltage in the range –1.4 V to –4.4 V (see
Programming VNEG).
8.3.2.1 Programming VNEG
The output voltage of the inverting buck-boost converter (VNEG) can be programmed using the CTRL pin. If
output voltage programming is not required, the CTRL pin can be used as a standard enable pin (see Enable
(CTRL)).
ttINIT
tLOWt
ttHIGH
ttSTORE
ttOFF
CTRL
4.6 V
VPOS
ttSCPt
ttSET
VNEG
±4.0 V
±4.2 V
Figure 6. Programming VNEG Using the CTRL Pin
When the CTRL pin is pulled high, the inverting buck-boost converter starts up with its default voltage of –4V.
The device now counts the rising edges applied to the CTRL pin and sets the output voltage (VNEG) according to
Table 1. For the timing diagram shown in Figure 6, VNEG is programmed to –4.2 V, since three rising edges are
detected.
The CTRL interface is designed to work with pulses whose duration is between 2 µs and 25 µs. Pulses shorter
than 2 µs or longer than 25 µs are not ensured to be recognized.
Table 1. Programming Table for VNEG
Number of Rising Edges
VNEG
Number of Rising Edges
VNEG
0 / no pulses
–4 V
16
–2.9 V
1
–4.4 V
17
–2.8 V
2
–4.3 V
18
–2.7 V
3
–4.2 V
19
–2.6 V
4
–4.1 V
20
–2.5 V
5
–4.0 V
21
–2.4 V
6
–3.9 V
22
–2.3 V
7
–3.8 V
23
–2.2 V
8
–3.7 V
24
–2.1 V
9
–3.6 V
25
–2.0 V
10
–3.5 V
26
–1.9 V
11
–3.4 V
27
–1.8 V
12
–3.3 V
28
–1.7 V
13
–3.2 V
29
–1.6 V
14
–3.1 V
30
–1.5 V
15
–3.0 V
31
–1.4 V
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8.3.2.2 Controlling the VNEG Transition Time
The transition time (tset) is the time required to move VNEG from one voltage level to the next. Users can control
the transition time by connecting a capacitor between the CT pin and ground. When the CT pin is left open or is
connected to ground, the transition time is as short as possible. When a capacitor is connected to the CT pin, the
transition time is determined by the time constant (τ) of the external capacitor (C(CT)) and the internal resistance
of the CT pin (R(CT)). The output voltage VNEG reaches 70% of its programmed value after 1τ.
An example is given below for the case when using 100 nF for C(CT).
τ ≈ tset(70%) = R(CT) × C(CT) = 300 kΩ × 100 nF = 30 ms
(1)
The output voltage VNEG reaches its programmed value after approximately 3τ.
The external capacitor connected to the CT pin has no effect on the first programming of VNEG, when the
inverting buck-boost converter ramps its output to the default voltage as fast as possible. Figure 7 shows the
detail of programming of the VNEG transition time with the CT pin during start-up.
CTRL
4.6 V
VPOS
t10 mst
±3.8 V
VNEG
±4.0 V (Default)
±4.1 V (Initial)
tNot programmable
tby CT capacitor
tProgrammable by
tCT capacitor (3×Tau)
tNot programmable
tby CT capacitor
Figure 7. Programming the Transition Time of VNEG
8.3.3 Soft-Start and Start-Up Sequence
The TPS65631 features a soft-start function to limit inrush current. When the device is enabled by a high-level
signal applied to the CTRL pin, the boost converter starts switching with a reduced switch current limit. Ten
milliseconds after the CTRL pin goes high, the inverting buck-boost converter starts with a default value of –4 V.
A typical start-up sequence is shown in Figure 8.
CTRL
VPOS
10 ms (typ.)
VNEG
Figure 8. Typical Start-Up Sequence
10
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8.3.4 Enable (CTRL)
The CTRL pin serves two functions. One is to enable and disable the device, and the other is to program the
output voltage (VNEG) of the inverting buck-boost converter (see Programming VNEG). If the digital interface is not
required, the CTRL pin can be used as a standard enable pin for the device, which will come up with its default
value on VNEG of –4 V. When CTRL is pulled high, the device is enabled. The device is shut down with CTRL
low.
8.3.5 Undervoltage Lockout
The TPS65631 features an undervoltage lockout function that disables the device when the input supply voltage
is too low for normal operation.
8.3.6 Short Circuit Protection
The TPS65631 is protected against short-circuits of VPOS and VNEG to ground and to each other.
8.3.6.1 Short-Circuits During Normal Operation
During normal operation an error condition is detected if VPOS falls below 4.1 V for more than 3 ms or VNEG is
pulled above the programmed nominal output by 500 mV for longer than 3 ms. In either case the device enters
shutdown mode: the converters are disabled and their outputs are disconnected from the input. To resume
normal operation either cycle the input supply voltage or toggle the CTRL pin low and then high again.
8.3.6.2 Short-Circuits During Start-Up
During start up an error condition is detected if:
• VPOS is not in regulation 10 ms after a high-level is applied to the CTRL pin.
• VNEG is higher than threshold level 10 ms after a high-level is applied to the CTRL pin.
• VNEG is not in regulation 20 ms after a high-level is applied to the CTRL pin.
To resume normal operation either cycle the input supply voltage or toggle the CTRL pin low and then high
again.
8.3.7 Output Discharge During Shutdown
The TPS65631 actively discharges its outputs during shutdown. Figure 9 shows the output discharge control.
VI
tVUVLO
tVUVLO
CTRL
VPOS
VNEG
Discharge
Discharge
Discharge
Discharge
Discharge
Discharge
t10 ms (typ.)
t10 ms (typ.)
Figure 9. Active Discharge of VPOS and VNEG During Shutdown
8.3.8 Thermal Shutdown
The TPS65631 enters thermal shutdown mode if its junction temperature exceeds 145°C (typical). During
thermal shutdown mode none of the device functions are available. To resume normal operation, either cycle the
input supply voltage or toggle the CTRL pin low and then high again.
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8.4 Device Functional Modes
8.4.1 Operation with VI < 2.9 V
The recommended minimum input supply voltage for full performance is 2.9 V. The device continues to operate
with input supply voltages below 2.9 V; however, full performance is not guaranteed. The device does not
operate with input supply voltages below the UVLO threshold.
8.4.2 Operation with VI ≈ VPOS (Diode Mode)
The TPS65631 features a "diode" mode that enables it to regulate its output voltage even when the input supply
voltage is close to VPOS (that is, too high for normal boost operation). When operating in diode mode the
converter's high-side switch stops switching and its body diode is used as the rectifier. Boost converter efficiency
is reduced when operating in diode mode. At low output currents (≈2 mA and below), the boost converter
automatically transitions from pulse-width modulation to pulse-skip mode. This ensures that VPOS stays in
regulation but increases the output voltage ripple on VPOS.
8.4.3 Operation with CTRL
When a low-level signal is applied to the CTRL pin the device is disabled and switching is inhibited. When the
input supply voltage is above the UVLO threshold and a high-level signal is applied to the CTRL pin the device is
enabled and its start-up sequence begins.
9 Applications and Implementation
9.1 Application Information
Figure 10 shows a typical application circuit suitable for supplying AMOLED displays in smartphone applications.
The circuit is designed to operate from a single-cell Li-Ion battery and generates a positive output voltage VPOS of
4.6 V and a negative output voltage of –4 V. Both outputs are capable of supplying up to 300 mA of output
current.
9.2 Typical Application
L1
4.7 µH
VI
2.9 V to 4.5 V
PVIN
SWP
AVIN
OUTP
C1
2×10 µF
FBS
TPS65631
VPOS
4.6 V, 300 mA
C2
10 µF
CTRL
EN / Program VNEG
C4
100 nF
OUTN
CT
C3
2×10 µF
PGND
VNEG
±4.0 V, 300 mA
AGND
GND
SWN
L2
4.7 µH
Figure 10. Typical Application Schematic
12
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the following input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE
Input voltage range
2.9 V to 4.5 V
Output voltage
VPOS = 4.6V, VNEG = –4 V
Switching frequency
1.7 MHz
9.2.2 Detailed Design Procedure
In order to maximize performance, the TPS65631 has been optimized for use with a relatively narrow range of
component values, and customers are strongly recommended to use the application circuit shown in Figure 10
with the components listed in Table 3 and Table 4.
9.2.2.1 Inductor Selection
The boost converter and inverting buck-boost converter have been optimized for use with 4.7 µH inductors, and it
is recommended that this value be used in all applications. Customers using other values of inductor are strongly
recommended to characterize circuit performance on a case-by-case basis.
Table 3. Inductor Selection
PARAMETER
L1, L2
VALUE
4.7 µH
MANUFACTURER
PART NUMBER
Coilmaster
MMPP252012-4R7N
Toko
1239AS-H-4R7M
ABCO
LPP252012-4R7N
Coilcraft
XFL4020-4R7ML
9.2.2.2 Capacitor Selection
The recommended capacitor values are shown in Table 4. Applications using less than the recommended
capacitance (e.g. to save PCB area) may experience increased voltage ripple. In general, the lower the output
power, the lower the necessary capacitance.
Table 4. Capacitor Selection
PARAMETER
VALUE
MANUFACTURER
PART NUMBER
C1
2 × 10 µF
Murata
GRM21BR71A106KE51
C2
10 µF
Murata
GRM21BR71A106KE51
C3
2 × 10 µF
Murata
GRM21BR71A106KE51
C4
100 nF
Murata
GRM21BR71E104KA01
9.2.2.3 Stability
Applications using component values that differ significantly from those recommended in Table 3 and Table 4
should be checked for stability over the full range of operating conditions.
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9.2.3 Application Curves
90
5 V/div
100
V(CTRL)
2 V/div
The performance shown in the following graphs was obtained using the circuit shown in Figure 10 and the
external components shown in Table 3 and Table 4. The output voltage settings for these measurements were
VPOS = 4.6 V and VNEG = –4 V.
VPOS
70
60
50
30
20
10
0
L1 = L2 = Coilcraft XFL4020−4R7ML
0
50
100
150
200
Output Current (mA)
2 V/div
40
VI = 4.3 V
VI = 3.7 V
VI = 3.2 V
VI = 2.9 V
250
300
200 mA/div
Efficiency (%)
80
VNEG
IIN
G000
Time = 2 ms/div
Figure 12. Start-Up Waveforms
10 mV/div (ac)
10 mV/div (ac)
Figure 11. Efficiency vs. Output Current
VPOS
VPOS
5 V/div
5 V/div
V(SWP)
200 mA/div
200 mA/div
V(SWP)
I(L3)
I(L3)
Time = 400 ns/div
Time = 400 ns/div
Figure 14. VPOS Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 300 mA)
10 mV/div (ac)
V(SWN)
I(L1)
VNEG
5 V/div
VNEG
V(SWN)
500 mA/div
500 mA/div
5 V/div
10 mV/div (ac)
Figure 13. VPOS Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 100 mA)
I(L1)
Time = 400 ns/div
Time = 400 ns/div
Figure 15. VNEG Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 100 mA)
14
Figure 16. VNEG Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 300 mA)
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4.610
−4.390
4.605
−4.395
Output Voltage (V)
Output Voltage (V)
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4.600
4.595
4.590
TJ = –40°C
TJ = 25°C
TJ = 85°C
4.585
IOUT = 100 mA
4.580
2.9
3.1
3.3
3.5
3.7
3.9
Input Voltage (V)
4.1
4.3
−4.405
−4.410
IOUT = 100 mA
−4.420
2.9
4.5
−4.395
Output Voltage (V)
4.605
4.600
4.595
4.590
TJ = –40°C
TJ = 25°C
TJ = 85°C
VI = 3.7 V
0
50
100
150
200
Output Current (mA)
250
4.1
4.3
4.5
G000
−4.405
−4.410
TJ = –40°C
TJ = 25°C
TJ = 85°C
−4.415
VI = 3.7 V
−4.420
300
0
G000
50
100
150
200
Output Current (mA)
250
300
G000
Figure 20. Inverting Buck-Boost Converter Load
Regulation
VI
100 mA/div
IPOS
VPOS
100 mV/div (ac)
500 mV/div
3.5
3.7
3.9
Input Voltage (V)
−4.400
Figure 19. Boost Converter Load Regulation
50 mV/div (ac) 20 mV/div (ac)
3.3
Figure 18. Inverting Buck-Boost Converter Line Regulation
−4.390
4.580
3.1
G000
4.610
4.585
TJ = –40°C
TJ = 25°C
TJ = 85°C
−4.415
Figure 17. Boost Converter Line Regulation
Output Voltage (V)
−4.400
VNEG
VPOS
Time = 40 µs/div
Time = 200 µs/div
Figure 21. Line Transient Response
Figure 22. Boost Converter Load Transient Response
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INEG
VNEG
Time = 400 µs/div
Figure 23. Inverting Buck-Boost Converter Load Transient Response
10 Power Supply Recommendations
The TPS65631 is designed to operate from an input voltage supply range between 2.9 V and 4.5 V. If the input
supply is located more than a few centimeters from the TPS65631 additional bulk capacitance may be required.
The 2×10 µF shown in the schematics in this data sheet are a typical choice for this function.
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11 Layout
11.1 Layout Guidelines
No PCB layout is perfect, and compromises are always necessary. However, following the basic principles listed
below (in order of importance) should go a long way to achieving good performance:
• Route switching currents on the top layer using short, wide traces. Do not route these signals through vias,
which have relatively high parasitic inductance and resistance.
• Place C1 as close as possible to pin 12.
• Place C2 as close as possible to pin 3.
• Place C3 as close as possible to pin 9.
• Place L1 as close as possible to pin 1.
• Place L2 as close as possible to pin 10.
• Use the thermal pad to join GND, AGND and PGND.
• Connect the FBS pin directly to the positive pin of C2, that is, keep this connection separate from the
connection between OUTP and C2.
• Use a copper pour on layer 2 as a thermal spreader and connect the thermal pad to it using a number of
thermal vias.
Figure 24 illustrates how a PCB layout following the above principles may be realized in practice.
11.2 Layout Example
Figure 24 shows the above principles implemented for the circuit of Figure 10.
L1
C2
C1
SWP
1
12
PVIN
PGND
2
11
AVIN
OUTP
3
10
SWN
FBS
4
9
OUTN
AGND
5
8
CT
GND
6
7
L2
C3
C4
CTRL
Via to signal layer on internal or bottom layer.
Thermal via to copper pour on internal or bottom layer.
Figure 24. PCB Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65631DPDR
ACTIVE
WSON
DPD
12
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SDS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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