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TPS65632
SLVSCY2A – MARCH 2015 – REVISED JANUARY 2016
TPS65632 Triple-Output AMOLED Display Power Supply
1 Features
•
•
1
•
•
•
•
•
•
2 Applications
AMOLED Displays
2.9-V to 4.5-V Input Voltage Range
Boost Converter 1 (VPOS)
– 4.6-V Output Voltage
– 0.5% Accuracy (25°C to 85°C )
– Dedicated Output Sense Pin
– 300-mA Output Current
Inverting Buck-Boost Converter (VNEG)
– –1.5-V to –5.4-V Programmable Output
Voltage
– –4-V Default Output Voltage
– 300-mA Output Current
Boost Converter 2 (AVDD)
– 5.8-V or 7.7-V Output Voltage
– 30-mA Output Current
Excellent Line Transient Regulation
Short-Circuit Protection
Thermal Shutdown
3-mm × 3-mm, 16-Pin WQFN Package
3 Description
The TPS65632 is designed to drive AMOLED
displays (Active Matrix Organic Light Emitting Diode)
requiring three supply rails, VPOS, VNEG and AVDD.
The device integrates a boost converter for VPOS, an
inverting buck-boost converter for VNEG, and a boost
converter for AVDD, all of which are suitable for
battery operated products. The digital control pin
(CTRL) allows programming the negative output
voltage in digital steps. The TPS65632 uses a novel
technology enabling excellent line and load
regulation.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS65632
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
spacer
spacer
spacer
Simplified Schematic
Efficiency vs Output Current
L1
4.7 µH
90
PVIN
AVIN
C2
10 µF
TPS65632
SWP2
AVDD
7.7 V / 30 mA
C6
10 µF
VNEG
±4.0 V / 300 mA
OUTN
C3
2×10 µF
EN
CTRL
AVDD
VPOS & VNEG
80
VPOS
4.6 V / 300 mA
OUTP1
FBS
C5
100 nF
L2
10 µH
Enable AVDD
Enable / Program VNEG
SWP1
Efficiency (%)
VI
2.9 V to 4.5 V
C1
3×10 µF
100
70
60
50
40
30
OUTP2
SELP2
AGND
PGND1
PGND2
L3
4.7 µH
20
10
SWN
CT
C4
100 nF
0
1m
VPOS = 4.6 V, VNEG = –4.0 V, AVDD = 7.7 V
10m
Output Current (A)
100m
300m
G000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65632
SLVSCY2A – MARCH 2015 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
12 Mechanical, Packaging, and Ordering
Information ........................................................... 20
4 Revision History
Changes from Original (March 2015) to Revision A
•
2
Page
Changed Load regulation (0.18 TYP) UNIT value in the Electrical Characteristics From: %/mA To: %/A ........................... 6
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5 Pin Configuration and Functions
AVIN
SWP2
PGND2
OUTP2
15
14
13
8
4
EN
FBS
7
3
AGND
OUTP1
Exposed
Thermal
Pad
6
2
CT
PGND1
5
1
SELP2
SWP1
16
RTE Package
16-Pin WQFN with Thermal Pad
Top View
12
PVIN
11
SWN
10
OUTN
9
CTRL
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
AGND
7
GND
Analog ground.
AVIN
16
PWR
Supply voltage for the device.
CT
6
I/O
CTRL
9
I
Boost converter 1 (VPOS) inverting buck-boost converter (VNEG) enable/program.
EN
8
I
Boost converter 2 (AVDD) enable.
FBS
4
I
Boost converter 1 (VPOS) sense input.
OUTN
10
O
Inverting buck-boost converter output (VNEG).
OUTP
3
O
Boost converter 1 output (VPOS).
OUTP2
13
O
Boost converter 2 output (AVDD).
PGND1
2
GND
Boost converter 1 power ground.
PGND2
14
GND
Boost converter 2 power ground.
PVIN
12
PWR
Inverting buck-boost converter power stage supply voltage.
SELP2
5
I
SWN
11
I/O
SWP1
1
I
Boost converter 1 switch pin.
SWP2
15
I
Boost converter 2 switch pin.
Exposed thermal pad
(1)
—
A capacitor connected between this pin and ground sets the transition time for VNEG
when programmed to a new value.
Boost converter 2 output voltage selection pin. AVDD = 7.7 V when SELP2 = low and
5.8 V when SELP2 = high.
Inverting buck-boost converter switch pin.
Connect this pad to AGND, PGND1 and PGND2.
GND = Ground, PWR = Power, I = Input, O = Output, I/O = Input/Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
SWP1, OUTP1, FBS, PVIN, AVIN
–0.3
5
V
SWP2
–0.3
12
V
OUTP2
–0.3
8.5
V
OUTN
–6.0
0.3
V
SWN
–6.5
4.8
V
CTRL, EN, SELP2
–0.3
5.5
V
CT
–0.3
3.6
V
Operating virtual junction, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Input supply voltage (2)
(1)
(2)
UNIT
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
With respect to GND pin.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
INPUT
VI
Input supply voltage range
2.9
3.7
4.5
V
TJ
Operating junction temperature
–40
85
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
RTE [WQFN]
16 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
14.2
ψJT
Junction-to-top characterization parameter
0.6
ψJB
Junction-to-board characterization parameter
14.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.3
(1)
4
UNIT
42.9
44
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
VI = 3.7 V, CTRL = 3.7 V, EN = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, AVDD = 7.7 V, TJ = –40°C to 85°C, typical values are at TJ
= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.9
3.7
4.5
V
0.25
5
µA
SUPPLY CURRENT AND THERMAL PROTECTION
VI
ISD
VUVLO
Input voltage range
Shutdown current
Under-voltage lockout threshold
CTRL = GND, EN = GND, sum of current flowing into
AVIN and PVIN
VI falling
1.8
2.1
V
VI rising
2.1
2.5
V
BOOST CONVERTER 1 (VPOS)
Positive output 1 voltage
VPOS
Positive output 1 voltage
variation
rDS(on)1A Switch on-resistance
rDS(on)1B Rectifier on-resistance
4.6
25°C ≤ TA ≤ 85°C, No load
–0.5%
–30°C ≤ TA ≤ 85°C, No load
–0.8%
Switching frequency
IPOS = 200mA
ISW1
Switch current limit
Inductor valley current
VSCP1
Short-circuit threshold in
operation
VPOS falling
tSCP1
Short-circuit detection time in
operation
VT
Output voltage sense threshold
R(FBS)
FBS pin pull-down resistance
RDCHG1
Discharge resistance
CTRL = GND, I(SWP1) = 1mA
Line regulation
IPOS = 200mA
Load regulation
1 mA ≤ IPOS ≤ 300 mA
0.5%
0.8%
200
I(SWP1) = 200 mA
fSW1
V
mΩ
350
mΩ
1.7
MHz
0.8
1
1.4
A
3.95
4.10
4.28
V
3
ms
V(OUTP1) – V(FBS) increasing
200
300
550
V(OUTP1) – V(FBS) decreasing
100
200
450
mV
mV
2
4
6
MΩ
10
30
70
Ω
0.01
%/V
0.007
%/A
INVERTING BUCK-BOOST CONVERTER (VNEG)
Output voltage default
VNEG
–4.0
Output voltage range
Output voltage accuracy
–1.4
–5.4
25°C ≤ TA ≤ 85°C, no load
–50
50
–30°C ≤ TA ≤ 85°C, no load
–60
60
rDS(on)2A SWN MOSFET on-resistance
V
mV
200
mΩ
300
mΩ
rDS(on)2B
SWN MOSFET rectifier onresistance
I(SWN) = 200 mA
fSW2
SWN Switching frequency
INEG = 10 mA
ISW2
SWN switch current limit
VI = 2.9 V
1.5
2.2
3
Voltage increase from nominal VNEG
VSCP2
Short circuit threshold in
operation
300
500
700
mV
180
200
230
mV
Short circuit threshold in start up
tSCP2
RDCHG2
1.7
MHz
A
Short circuit detection time in
start up
10
ms
Short circuit detection time in
operation
3
ms
Discharge resistance
CTRL = GND, I(SWN) = 1 mA
Line regulation
INEG = 200 mA
Load regulation
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130
150
170
Ω
0.004
%/V
0.1
%/A
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Electrical Characteristics (continued)
VI = 3.7 V, CTRL = 3.7 V, EN = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, AVDD = 7.7 V, TJ = –40°C to 85°C, typical values are at TJ
= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BOOST CONVERTER 2 (AVDD)
Output voltage
AVDD
Output voltage accuracy
rDS(on)3A SWP2 switch on-resistance
rDS(on)3B SWP2 rectifier on-resistance
SELP2 = Low
7.7
SELP2 = High
5.8
25°C ≤ TA ≤ 85°C, no load
–1%
–30°C ≤ TA ≤ 85°C, no load
Switching frequency
IAVDD = 0 mA
ILIM3
Switch current limit
Inductor valley current
RDCHG3
Discharge resistance
EN = GND, I(SWP2) = 1 mA
Line regulation
IAVDD = 30 mA
1%
–1.3%
1.3%
400
I(SWP2) = 200 mA
fSW3
V
mΩ
650
1.7
MHz
0.25
0.35
0.45
A
10
30
70
Ω
Load regulation
0.02
%/V
0.18
%/A
CTRL INTERFACE (CTRL, EN, SELP2)
VIH
Logic input high level voltage
1.2
V
VIL
Logic input low level voltage
0.4
V
R
Pull-down resistance
150
400
860
kΩ
RCT
CT pin resistance
150
300
500
kΩ
tINIT
Initialization time
300
400
µs
tSTORE
Data storage/accept time period
30
80
µs
tSDN
Shutdown time period
30
80
µs
TSD
Thermal shutdown temperature
OTHER
Temperature rising
145
°C
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
CTRL INTERFACE
tLOW
Low-level pulse duration
2
10
25
µs
tHIGH
High-level pulse duration
2
10
25
µs
tOFF
Shutdown pulse duration (CTRL = low)
6
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200
µs
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6.7 Typical Characteristics
TJ = 25°C, VI = 3.7 V, unless otherwise stated.
600
10
500
Resistance (mΩ)
Current (µA)
1
0.1
400
300
200
0.01
100
0.001
−50
−25
0
25
50
Temperature (°C)
75
100
0
−50
125
Low−Side
High−Side
−25
G000
Figure 1. Shutdown Current into AVIN and PVIN Pins
0
25
50
75
Junction Temperature (°C)
100
125
G000
Figure 2. Boost Converter 1 (VPOS) rDS(ON)
600
1000
900
800
Resistance (mΩ)
Resistance (mΩ)
500
400
300
200
600
500
400
300
200
100
0
−50
700
Low−Side
High−Side
−25
0
25
50
75
Junction Temperature (°C)
100
125
G000
Figure 3. Inverting Buck-Boost Converter (VNEG) rDS(ON)
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Low−Side
High−Side
100
0
−50
−25
0
25
50
75
Junction Temperature (°C)
100
125
G000
Figure 4. Boost Converter 2 (AVDD) rDS(ON)
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7 Detailed Description
7.1 Overview
The TPS65632 consists of two boost converters and an inverting buck-boost converter. The VPOS output is fixed
at 4.6 V and VNEG is programmable via a digital interface in the range of –1.4 V to –5.4 V; the default is –4 V.
AVDD can be selected between 7.7 V and 5.8 V, using the SELP2 pin. The transition time of VNEG output is
adjustable by the CT pin capacitor.
7.2 Functional Block Diagram
VI
SWP2
15
AVDD
AVIN
16
SWP1
1
OUTP2
13
OUTP1
VPOS
3
Short-Circuit
Protection
Gate Driver
Gate Driver
PGND2
PGND1
Output Sense
Control
4
FBS
SELP2
±
PWM
Control
5
VREF
+
AVIN
SWP2
AVIN
SWP1
±
PWM
Control
+
VREF
EN
8
Oscillator
CTRL
+
DAC
6
CTRL
Digital
Interface
9
CT
Control
6
±
CT
±
Constant
Off-Time
Controller
VI
+
50 mV
PVIN
12
OUTN
10
7
11
AGND
8
Gate Driver
Short-Circuit
Protection
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2
SWN
VNEG
14
PGND1
PGND2
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7.3 Feature Description
7.3.1 Boost Converter 1 (VPOS)
Boost converter 1 uses a fixed-frequency current-mode topology. Its output voltage (VPOS) is programmed at the
factory to 4.6 V and cannot be changed by the user.
For highest output voltage accuracy, connect the output sense pin (FBS) directly to the positive terminal of the
main output capacitor. If not used, the FBS pin can be left floating or connected to ground, in which case the
boost converter senses the output voltage via the OUTP1 pin.
7.3.1.1 V(POS) Boost Output Sense (FBS Pin)
V(POS) boost has a dedicated output sense pin (FBS). If FBS is floating or connected to ground, V(POS) boost
senses the output through OUTP1 pin.
7.3.2 Inverting Buck-Boost Converter (VNEG)
The inverting buck-boost converter uses a constant-off-time current-mode topology. The converter's default
output voltage (VNEG) is –4.0 V, but it can be programmed from –1.4 V to –5.4 V (see Programming VNEG ).
7.3.2.1 Programming VNEG
The digital interface allows programming of VNEG in discrete steps. If the output voltage setting function is not
required then the CTRL pin can also be used as a standard enable pin. The digital output voltage programming
of VNEG is implemented using a simple digital interface with the timing shown in Figure 5.
ttINIT
tLOWt
ttHIGH
ttSTORE
CTRL
ttSDN
ttOFFt
4.6 V
VPOS
ttSCP2t
VNEG
±4.0 V
ttSET
±5.2 V
Figure 5. Digital Interface Using CTRL
When CTRL is pulled high the device starts up with its default voltage of –4 V. The device includes a 6-bit DAC
that generates the output voltages shown in Table 1. The interface counts the rising edges applied to the CTRL
pin once the device is enabled. According toTable 1, VNEG is programmed to –5.2 V since 3 rising edges are
detected.
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Feature Description (continued)
Table 1.
Bit / Rising Edges
VNEG
DAC Value
Bit / Rising Edges
VNEG
DAC Value
0 / no pulse
–4.0 V
000000
21
–3.4 V
010101
1
–5.4 V
000001
22
–3.3 V
010110
2
–5.3 V
000010
23
–3.2 V
010111
3
–5.2 V
000011
24
–3.1 V
011000
4
–5.1 V
000100
25
–3.0 V
011001
5
–5.0 V
000101
26
–2.9 V
011010
6
–4.9 V
000110
27
–2.8 V
011011
7
–4.8 V
000111
28
–2.7 V
011100
8
–4.7 V
001000
29
–2.6 V
011101
9
–4.6 V
001001
30
–2.5 V
011110
10
–4.5 V
001010
31
–2.4 V
011111
11
–4.4 V
001011
32
–2.3 V
100000
12
–4.3 V
001100
33
–2.2 V
100001
13
–4.2 V
001101
34
–2.1 V
100010
14
–4.1 V
001110
35
–2.0 V
100011
15
–4.0 V
001111
36
–1.9 V
100100
16
–3.9 V
010000
37
–1.8 V
100101
17
–3.8 V
010001
38
–1.7 V
100110
18
–3.7 V
010010
39
–1.6 V
100111
19
–3.6 V
010011
40
–1.5 V
101000
20
–3.5 V
010100
41
–1.4 V
101001
7.3.2.2 Controlling VNEG Transition Time
The transition time (tSET) is the time required to move VNEG from one voltage level to the next. Users can control
the transition time with a capacitor connected between the CT pin and ground. When the CT pin is left open or
connected to ground the transition time is as short as possible. When a capacitor is connected to the CT pin the
transition time is determined by the time constant (τ) of the external capacitor (C(CT)) and the internal resistance
of the CT pin (RCT). The output voltage reaches 70% of its programmed value after 1τ.
An example is given when using 100 nF for C(CT).
τ = 300 kΩ × 100 nF = 30 ms
(1)
The output voltage is at 70% of its final value after 1τ (i.e. 30 ms in this case) and at its final value after
approximately 3τ (90 ms in this case).
7.3.3 Boost Converter 2 (AVDD)
Boost converter 2 uses a fixed-frequency current-mode topology. The TPS65632 device supports fixed output
voltages of 5.8 V and 7.7 V, selected by the SELP2 pin. AVDD = 7.7 V when SELP2 is low or left floating, and
AVDD = 5.8 V when SELP2 is high.
7.3.4 Soft Start and Start-Up Sequence
The devices feature a soft-start function to limit inrush current. Boost converter 2 (AVDD) is enabled when EN
goes high. When CTRL goes high, boost converter 1 starts with a reduced switch current limit and 10 ms later
the inverting buck-boost converter (VNEG) starts with its default value of –4 V. The typical start-up sequence is
shown in Figure 6. The two boost converters operate independently and boost converter 1 (VPOS) does not
require boost converter 2 (AVDD) to be in regulation in order for it to start..
10
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EN
CTRL
AVDD
VPOS
10 ms (typ.)
VNEG
Figure 6. Start-Up Sequence
7.3.5 Enable (CTRL)
The CTRL pin serves two functions: one is to enable and disable the device, and the other is to program the
output voltage (VNEG) of the inverting buck-boost converter (see Programming VNEG). If the VNEG programming
function is not required the CTRL pin can be used as a standard enable pin for the device, which will start up
with its default value of –4.0 V on VNEG. The device is enabled when CTRL is pulled high and disabled when
CTRL is pulled low.
Note that to ensure proper start up CTRL must be pulled low for a minimum of 200 µs before being pulled high
again.
7.3.6 Undervoltage Lockout
The device features an undervoltage lockout function that disables it when the input supply voltage is too low for
proper operation.
7.3.7 Short-Circuit Protection
7.3.7.1 Short Circuits During Operation
The device is protected against short circuits of VPOS and VNEG to ground and short circuit of these two outputs to
each other. During normal operation an error condition is detected if VPOS falls below 4.1 V for longer than 3 ms
or VNEG is pulled above the programmed nominal output by 500 mV for longer than 3 ms. In either case the
device goes into shutdown and the outputs are disconnected from the input. This state is latched, and to resume
normal operation, VI has to cycle below the undervoltage lockout threshold, or CTRL has to toggle LOW and then
HIGH.
7.3.7.2 Short Circuits During Start Up
During start up an error condition is detected in the following cases:
• VPOS is not in regulation 10 ms after CTRL goes HIGH
• VNEG is higher than threshold level 10 ms after CTRL goes HIGH
• VNEG is not in regulation 20 ms after CTRL goes HIGH
whitespace
If any of the above conditions is met the device goes into shutdown and the outputs are disconnected from the
input. This state is latched, and to resume normal operation VI has to cycle below the undervoltage threshold, or
CTRL has to toggle LOW and HIGH.
7.3.8 Output Discharge During Shut Down
The device discharges outputs during shutdown. Figure 7 shows the discharge control.
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tVUVLO
tVUVLO
EN
CTRL
Discharge
Discharge
Discharge
Discharge
Discharge
Discharge
Discharge
Discharge
Discharge
AVDD
VPOS
VNEG
t10 ms (typ.)
t10 ms (typ.)
Figure 7. Outputs Discharge During Shut Down
7.3.9 Thermal Shutdown
The TPS65632 device enters thermal shutdown if its junction temperature exceeds 145°C (typical). During
thermal shutdown none of the device's functions are available. To resume normal operation VI has to cycle below
the undervoltage threshold, or CTRL has to toggle LOW and then HIGH.
7.4 Device Functional Modes
7.4.1 Operation with VI < 2.9 V
The recommended minimum input supply voltage for full-performance is 2.9 V. The device continues to operate
with input supply voltages below 2.9 V, however, full performance is not guaranteed. The TPS65632 device does
not operate with input supply voltages below the UVLO threshold.
7.4.2 Operation with VI ≈ VPOS (Diode Mode)
The TPS65632 device features a "diode" mode that enables it to regulate its VPOS output even when the input
supply voltage is close to VPOS (that is, too high for normal boost operation). When operating in diode mode the
VPOS boost converter's high-side switch is disabled and its body diode used as the rectifier. Note that a minimum
load of ≈2 mA is required to proper output regulation in diode mode.
7.4.3 Operation with CTRL
When a low-level signal is applied to the CTRL pin the device is disabled and switching is inhibited. When the
input supply voltage is above the UVLO threshold and a high-level signal is applied to the CTRL pin the device is
enabled and its start-up sequence begins.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS65632 device is intended to supply the main analog supplies required by AMOLED displays. VPOS is
fixed at 4.6 V, but VNEG can be programmed using the CTRL pin to voltages in the range –1.4 V to –5.4 V. The
SELP2 pin can be used to set AVDD to either 5.8 V or 7.7 V. The device is highly integrated and requires few
external components.
8.2 Typical Application
Figure 8 shows a typical application circuit suitable for supplying AMOLED displays in smartphone applications.
The circuit is designed to operate from a single-cell Li-Ion battery and generates a positive output voltage VPOS of
4.6 V, a negative output voltage VNEG of –4.0 V, and a positive output voltage AVDD of 5.8 V or 7.7 V. The VPOS
and VNEG outputs are each capable of supplying up to 300 mA of current, and the AVDD output of up to 30 mA.
L1
4.7 µF
VI
2.9 V to 4.5 V
C1
3 × 10 µF
PVIN
AVIN
SWP1
C2
10 µF
TPS65632
L2
10 µH
SWP2
Enable AVDD
Enable / Program VNEG
AVDD Select
VPOS
4.6 V / 300 mA
OUTP1
FBS
C5
100 nF
VNEG
±4.0 V / 300 mA
OUTN
C3
2×10 µF
EN
CTRL
SELP2
AVDD
5.8 V, 7.7 V / 30 mA
OUTP2
C6
10 µF
AGND
PGND1
PGND2
L3
4.7 µH
SWN
CT
C4
100 nF
Figure 8. Typical Application Circuit
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 2
Table 2. Design Parameters
PARAMETER
VALUE
Input voltage range
2.9 V to 4.5 V
Output voltage
VPOS = 4.6 V
VNEG = –4.0 V
AVDD = 7.7 V
Current
I(VPOS) = 300 mA
I(VNEG) = 300 mA
I(AVDD) = 30 mA
Switching Frequency
f(SWP1) = 1.7 MHz
f(SWN) = 1.7 MHz
f(SWP2) = 1.7 MHz
8.2.2 Detailed Design Procedure
In order to maximize performance, the TPS65632 device has been optimized for use with a relatively narrow
range of component values, and customers are strongly recommended to use the application circuits shown in
Figure 8 with the components listed in Table 3 and Table 4.
8.2.2.1 Inductor Selection
The VPOS and VNEG converters have been optimized for use with 4.7-µH inductors and the AVDD boost converter
has been optimized for use with 10-µH inductors. For optimum performance it is recommended that these values
be used in all applications. Customers using different inductors than the ones in Table 3 are strongly
recommended to characterize circuit performance fully before finalizing their design. Customers should pay
particular attention to the inductors' saturation current and ensure it is adequate for their application's worst-case
conditions (which may also be during start-up).
Table 3. Inductor Selection
REFERENCE
DESIGNATOR
VALUE
L1, L3
4.7 µH
Coilcraft
XFL4020-4R7ML
L2
10 µH
Coilmaster
MMPP252012-100N
MANUFACTURER
PART NUMBER
8.2.2.2 Capacitor Selection
The recommended capacitor values are shown in Table 4. Applications using less than the recommended
capacitance (e.g. to save PCB area) may exhibit increased voltage ripple. In general, the lower the output
current, the lower the necessary capacitance. Customers should be aware that ceramic capacitors of the kind
typically used with the TPS65632 device exhibit dc bias effects, which means their effective capacitance under
normal operating conditions may be significantly lower than their nominal capacitance value. Customers must
ensure that the effective capacitance is sufficient for their application's performance requirements.
Table 4. Capacitor Selection
14
REFERENCE
DESIGNATOR
VALUE
MANUFACTURER
PART NUMBER
C1
3 × 10 µF
Murata
GRM21BR71A106KE51
C2, C6
10 µF
Murata
GRM21BR71A106KE51
C3
2 × 10 µF
Murata
GRM21BR71A106KE51
C4, C5
100 nF
Murata
GRM155B11A104KA01
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8.2.3 Application Curves
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Unless otherwise stated: TA = 25°C, VI = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, AVDD = 7.7 V; L1 = L3 = XFL40204R7ML, and L2 = MMPP252012-100N.
60
50
40
30
50
40
30
VI = 2.9 V
VI = 3.7 V
VI = 4.3 V
20
10
0
60
0
50m
100m
150m
200m
Output Current (A)
250m
VI = 2.9 V
VI = 3.7 V
VI = 4.3 V
20
10
0
300m
0
5m
4.62
−3.98
4.61
−3.99
4.60
4.59
4.58
4.57
IO = 10 mA
IO = 100 mA
IO = 300 mA
4.56
3.1
3.3
3.5
3.7
3.9
Input Voltage (V)
4.1
4.3
−4.02
−4.03
−4.04
INEG = 10 mA
INEG = 100 mA
INEG = 300 mA
−4.05
−4.06
2.9
4.5
7.75
4.61
Output Voltage (V)
Output Voltage (V)
4.62
7.74
7.73
7.72
IO = 10 mA
IO = 40 mA
IO = 80 mA
3.3
3.5
3.7
3.9
Input Voltage (V)
4.1
Figure 13. AVDD Line Regulation
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3.1
3.3
3.5
3.7
3.9
Input Voltage (V)
4.1
4.3
4.5
G000
Figure 12. VNEG Line Regulation
7.76
3.1
G000
−4.01
Figure 11. VPOS Line Regulation
7.70
2.9
30m
−4.00
G000
7.71
25m
Figure 10. AVDD Efficiency
Output Voltage (V)
Output Voltage (V)
Figure 9. VPOS and VNEG Combined Efficiency
4.55
2.9
10m
15m
20m
Output Current (A)
G000
4.3
4.60
4.59
4.58
4.57
VI = 2.9 V
VI = 3.7 V
VI = 4.3 V
4.56
4.5
G000
4.55
0
50m
100m
150m
200m
Output Current (A)
250m
300m
G000
Figure 14. VPOS Load Regulation
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−3.98
7.76
7.75
−4.00
Output Voltage (V)
Output Voltage (V)
−3.99
−4.01
−4.02
−4.03
−4.04
7.73
7.72
VI = 2.9 V
VI = 3.7 V
VI = 4.3 V
−4.05
−4.06
7.74
0
50m
100m
150m
200m
Output Current (A)
250m
VI = 2.9 V
VI = 3.7 V
VI = 4.3 V
7.71
7.70
300m
0
5m
CTRL
Figure 15. VNEG Load Regulation
G000
5 V/div
AVDD
SW(AVDD)
V(POS)
IIN
2 V/div
V(NEG)
30m
5 V/div
2 V/div
IIN
200 mA /div
5 V/div
200 mA /div
2 ms/div
Figure 17. Start-Up: VPOS and VNEG
Figure 18. Start-Up: AVDD
V(POS)
2 ms/div
5 V/div
SW(BOOST)
10 mV/div
200 mA /div
IL(BOOST)
V(POS)
SW(BOOST)
IL(BOOST)
25m
Figure 16. AVDD Load Regulation
EN
5 V/div
10 mV/div
5 V/div
200 mA /div
500 ns/div
IPOS = 100 mA
Figure 19. Switch Pin, Inductor Current and Output
Voltage Waveforms: VPOS
16
10m
15m
20m
Output Current (A)
G000
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500 ns/div
IPOS = 300 mA
Figure 20. Switch Pin, Inductor Current and Output
Voltage Waveforms: VPOS
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SW(BUCKBOOST)
10 mV/div
5 V/div
500 mA /div
500 ns/div
INEG = 100 mA
IL(BUCKBOOST)
IL(BUCKBOOST)
SW(BUCKBOOST)
V(NEG)
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500 mA /div
500 ns/div
SW(AVDD)
AVDD
10 mV/div
Figure 22. Switch Pin, Inductor Current and Output
Voltage Waveforms: VNEG
5 V/div
IL(AVDD)
AVDD
SW(AVDD)
5 V/div
INEG = 300 mA
Figure 21. Switch Pin, Inductor Current and Output
Voltage Waveforms: VNEG
IL(AVDD)
10 mV/div
200 mA /div
10 mV/div
5 V/div
200 mA /div
500 ns/div
IAVDD = 10 mA
Figure 23. Switch Pin, Inductor Current and Output
Voltage Waveforms: AVDD
VI = 3.0 V to 4.2 V in 50 µs
IPOS = 100 mA
Figure 25. VPOS Line Transient Response
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500 ns/div
IAVDD = 30 mA
Figure 24. Switch Pin, Inductor Current and Output
Voltage Waveforms: AVDD
VI = 3.0 V to 4.2 V in 50 µs
INEG = 100 mA
Figure 26. VNEG Line Transient Response
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IPOS = 10 mA to 100 mA in 100 ns
VI = 3.0 V to 4.2 V in 50 µs
IAVDD = 30 mA
Figure 28. VPOS Load Transient Response
Figure 27. AVDD Line Transient Response
INEG = 10 mA to 100 mA in 100 ns
IAVDD = 10 mA to 30 mA in 100 ns
Figure 29. VNEG Load Transient Response
Figure 30. AVDD Load Transient Response
2.0
Frequency (MHz)
1.9
1.8
1.7
f(SWP1)
f(SWN)
f(SWP2)
1.6
1.5
2.9
IPOS = 100 mA
3.1
3.3
3.5
3.7
3.9
Input Voltage (V)
4.1
4.3
INEG = 100 mA
4.5
G000
IAVDD = 30 mA
Figure 31. Switching Frequency
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9 Power Supply Recommendations
The TPS65632 device is designed to operate with input supply voltages in the range 2.9 V to 4.5 V. If the input
supply voltage is located more than a few centimeters away from the device, additional bulk capacitance may be
required. The three 10-µF capacitors shown in Figure 8 are suitable for typical applications.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
Place the input capacitor on PVIN and the output capacitor on OUTN as close as possible to device. Use
short and wide traces to connect the input capacitor on PVIN and the output capacitor on OUTN.
Place the output capacitor on OUTP1 and OUTP2 as close as possible to device. Use short and wide traces
to connect the output capacitor on OUTP1 and OUTP2.
Connect the ground of CT capacitor with AGND, pin 7, directly.
Connect input ground and output ground on the same board layer, not through via hole.
Connect AGND, PGND1 and PGND2 with exposed thermal pad.
10.2 Layout Example
VIN
GND
C1c
L2
C6
GND
AVIN
SWP2
PGND2
OUTP2
C1b
15
14
13
L1
16
C5
C1a
AVDD
SWP1
1
12
PVIN
PGND1
2
11
SWN
OUTP1
3
10
OUTN
C3a
FBS
4
9
CTRL
C3b
L3
VNEG
C4
7
8
AGND
EN
6
CT
Via to GND plane on layer 2
Via to other layer
5
VPOS
SELP2
C2
Figure 32. Recommended PCB Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Ordering Information
The following pages include mechanical, packaging, and ordering information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS65632RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PC6I
Samples
TPS65632RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PC6I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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