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TPS74401
SBVS066R – DECEMBER 2005 – REVISED APRIL 2017
TPS74401 3.0-A, Ultra-LDO with Programmable Soft-Start
1 Features
3 Description
•
•
The TPS74401 low-dropout (LDO) linear regulators
provide an easy-to-use robust power-management
solution for a wide variety of applications. The userprogrammable soft-start minimizes stress on the input
power source by reducing capacitive inrush current
on start-up. The soft-start is monotonic and wellsuited for powering many different types of
processors and application-specific integrated circuits
(ASICs). The enable input and power-good output
allow easy sequencing with external regulators. This
complete flexibility lets the user configure a solution
that meets the sequencing requirements of fieldprogrammable gate arrays (FPGAs), digital signal
processors (DSPs), and other applications with
specific start-up requirements.
Input Voltage Range: 1.1 V to 5.5 V
Soft-Start (SS) Pin Provides a Linear Startup With
Ramp Time Set by External Capacitor
1% Accuracy Over Line, Load, and Temperature
Supports Input Voltages as Low as 0.9 V With
External Bias Supply
Adjustable Output: 0.8 V to 3.6 V
Ultra-Low Dropout: 115 mV at 3.0 A (typical)
Stable With Any or No Output Capacitor
Excellent Transient Response
Open-Drain Power-Good (VQFN Only)
Packages: 5-mm × 5-mm × 1-mm VQFN (RGW),
3.5-mm × 3.5-mm VQFN (RGR), and DDPAK
1
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
FPGA Applications
DSP Core and I/O Voltages
Post-Regulation Applications
Applications With Special Start-Up Time or
Sequencing Requirements
Hot-Swap and Inrush Controls
•
A precision reference and error amplifier deliver 1%
accuracy over load, line, temperature, and process.
The TPS74401 family of LDOs is stable without an
output capacitor or with ceramic output capacitors.
The device family is fully specified from TJ = –40°C to
125°C. The TPS74401 is offered in two 20-pin small
VQFN packages (a 5-mm × 5-mm RGW and a
3.5-mm × 3.5-mm RGR package), yielding a highly
compact total solution size. For applications that
require additional power dissipation, the DDPAK
(KTW) package is also available.
Device Information(1)
PART NUMBER
TPS74401
PACKAGE
BODY SIZE (NOM)
TO-263 (7)
10.10 mm × 8.89 mm
VQFN, RGW (20)
5.00 mm × 5.00 mm
VQFN, RGR (20)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
SPACE
SPACE
SPACE
SPACE
Typical Application Circuit
VIN
IN
CIN
1mF
Turn-On Response
VPG
PG
R1
SS
CBIAS
1mF
GND
FB
CSS
CSS = 0.001mF
VOUT
OUT
BIAS TPS74401
VBIAS
CSS = 0mF
RPULLUP
EN
COUT
Optional
VOUT
CSS = 0.0047mF
500mV/div
R2
1.1V
V
R1 = OUT - 1 ´ R2
VREF
1V/div
VEN
0V
Time (1ms/div)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS74401
SBVS066R – DECEMBER 2005 – REVISED APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6
6
6
7
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
7.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
14
14
14
15
16
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 20
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Power Dissipation .................................................
Thermal Considerations ........................................
25
25
25
26
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Q (April 2015) to Revision R
Page
•
Added RGR package to document ........................................................................................................................................ 1
•
Changed TPS744xx to TPS74401 throughout document ..................................................................................................... 1
•
Changed Packages Features bullet ...................................................................................................................................... 1
•
Changed second paragraph of Description section: added RGR package and changed second to last sentence............... 1
•
Deleted fixed voltage version of Typical Application Circuit diagram..................................................................................... 1
•
Added RGR package to Pin Configuration and Functions section ........................................................................................ 5
•
Changed FB/SNS to FB in both pin out drawings, deleted TPS744xx from VQFN package ............................................... 5
•
Changed Surface Mount to Top View in KTW pin out drawing .............................................................................................. 5
•
Changed input capacitor to bias capacitor in BIAS pin description ....................................................................................... 5
•
Deleted (adjustable version only) from description of FB pin in Pin Functions table ............................................................ 5
•
Changed I/O column value to — from O for NC pins of Pin Functions table ........................................................................ 5
•
Deleted SNS pin from Pin Functions table ............................................................................................................................ 5
•
Added RGR package to Thermal Information table .............................................................................................................. 7
•
Deleted (adjustable version) from VREF parameter name in Electrical Characteristics table ................................................ 7
•
Deleted SNS pin reference from IFB, ISNS parameter: changed symbol from IFB, ISNS to IFB, deleted sense from
parameter name ..................................................................................................................................................................... 7
•
Deleted adjustable from footnote 1 and deleted ISNS from footnote 4 of Electrical Characteristics table .............................. 7
•
Changed conditions of R1, R2 in Noise Spectral Density figure ........................................................................................... 11
•
Deleted Fixed Voltage Versions figure from Functional Block Diagram section .................................................................. 14
•
Changed first paragraph of Application Information section: deleted and tracking capabilities from first sentence and
changed very low input and output voltages to very low output voltages with low VIN to VOUT headroom in last sentence 18
•
Changed title of first typical application from Adjustable Voltage Part and Setting to Setting the TPS74401 ..................... 20
•
Deleted reference to adjustable version in first sentence and Typical Application Circuit for the TPS74401 figure in
first typical application section .............................................................................................................................................. 20
•
Changed Because VIN ≥ VOUT + 1.62 V to Because VIN is less than VOUT plus the VBIAS dropout and VBIAS = VIN to
2
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Revision History (continued)
VBIAS = VOUT in last paragraph of Detailed Design Procedure in first typical application section ......................................... 21
•
Deleted Fixed Voltage and Sense Pin section ..................................................................................................................... 23
•
Deleted BIAS recommendation from Layout Guidelines section.......................................................................................... 25
•
Changed RGW Package to VQFN Packages in caption of Layout Schematic figure.......................................................... 25
•
Added RGR package to VQFN description in Power Dissipation section............................................................................ 26
•
Added RGR package to Thermal Considerations section ................................................................................................... 27
Changes from Revision P (January 2015) to Revision Q
Page
•
Changed QFN to VQFN throughout document ...................................................................................................................... 1
•
Changed TPS744xx to TPS74401 throughout document ..................................................................................................... 1
•
Deleted fixed output Features bullet....................................................................................................................................... 1
•
Changed VBIAS minimum value in Recommended Operating Conditions table...................................................................... 6
•
Changed footnote 1 for Recommended Operating Conditions table...................................................................................... 6
•
Added second row to VOUT accuracy parameter ................................................................................................................... 7
•
Added last four rows to VDO, VBIAS dropout voltage parameter .............................................................................................. 7
•
Added Timing Requirements table ......................................................................................................................................... 8
•
Added Device Functional Modes section ............................................................................................................................. 15
•
Changed third paragraph of Dropout Voltage ...................................................................................................................... 19
•
Changed first sentence of Without an Auxiliary Bias section ............................................................................................... 24
•
Changed Power Dissipation section location; moved to after Layout Example section....................................................... 25
•
Added Development Support section ................................................................................................................................... 29
•
Added information about reference design TIDU421 and user guide SLVU143 to Related Documentation section ......... 29
Changes from Revision O (March 2013) to Revision P
Page
•
Deleted Active High Enable bullet from Features list ............................................................................................................ 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 6
•
Changed footnote 3c for Thermal Information table .............................................................................................................. 7
•
Changed y-axis in Figure 1, Figure 2, Figure 4, and Figure 7 from abbreviation (IOUT) to text (Output Current) .................. 9
•
Added "V" to VIN = 1.8 V condition in Figure 9, Figure 10, and Figure 11 ............................................................................ 9
•
y-axis and graph title in Figure 15 from abbreviation (IOUT) to text (Output Current) .......................................................... 10
•
Changed Figure 25; made VOUT trace red to show data trend separation .......................................................................... 12
•
Changed Overview section text............................................................................................................................................ 14
•
Changed second paragraph of Dropout Voltage ................................................................................................................. 19
•
Changed Figure 27; updated equation in figure .................................................................................................................. 20
Changes from Revision N (December 2012) to Revision O
•
Page
Changed RGW and KTW values in Thermal Information table.............................................................................................. 7
Changes from Revision M (November 2010) to Revision N
•
Page
Changed TJ max value from 125 to 150 in Absolute Maximum Ratings table ....................................................................... 6
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SBVS066R – DECEMBER 2005 – REVISED APRIL 2017
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Changes from Revision L (August, 2010) to Revision M
•
Page
Corrected equation for Table 2 ............................................................................................................................................ 17
Changes from Revision K (December, 2009) to Revision L
Page
•
Replaced the Dissipation Ratings table with the Thermal Information table .......................................................................... 7
•
Revised Layout Recommendations and Power Dissipation section .................................................................................... 25
•
Revised Thermal Considerations section ............................................................................................................................. 26
4
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SBVS066R – DECEMBER 2005 – REVISED APRIL 2017
5 Pin Configuration and Functions
IN
NC
NC
NC
OUT
5
4
3
2
1
RGW, RGR Package
5-mm × 5-mm and 3.5-mm × 3.5-mm, 20-Pin VQFN
Top View
IN
6
20
OUT
IN
7
19
OUT
IN
8
18
OUT
PG
9
17
NC
BIAS
10
16
FB
11
12
13
14
15
EN
GND
NC
NC
SS
GND
KTW Package
7-Pin DDPAK
Top View
1 2 3 4 5 6 7
SS
OUT IN EN
FB GND BIAS
Pin Functions
PIN
RGW,
RGR
I/O
KTW
BIAS
6
10
I
Bias input voltage for error amplifier, reference, and internal control circuits.
A 1-µF or larger bias capacitor is recommended for optimal performance.
If IN is connected to BIAS, use a 4.7 µF or larger capacitor.
EN
7
11
I
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the
regulator into shutdown mode. This pin must not be left floating.
FB
2
16
I
This pin is the feedback connection to the center tap of an external resistor divider
network that sets the output voltage. This pin must not be left floating.
GND
4
12
—
IN
5
5–8
I
NC
N/A
2–4, 13,
14, 17
—
No connection. This pin can be left floating or connected to GND to allow better thermal
contact to the top-side plane.
OUT
3
1, 18–20
O
Regulated output voltage. No capacitor is required on this pin for stability, but is
recommended for optimal performance.
PAD/TAB
—
—
—
Must be soldered to the ground plane for increased thermal performance.
Internally connected to ground.
NAME
DESCRIPTION
Ground
Unregulated input to the device.
An input capacitor of 1 µF or greater is recommended for optimal performance.
PG
N/A
9
O
Power-good (PG) is an open-drain, active-high output that indicates the status of VOUT.
When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state.
When VOUT is below this threshold, the pin is driven to a low-impedance state. Connect
a pullup resistor from 10 kΩ to 1 MΩ from this pin to a supply up to 5.5 V. The supply
can be higher than the input voltage.
Alternatively, the PG pin can be left floating if output monitoring is not necessary.
SS
1
15
—
Soft-start pin. A capacitor connected on this pin to ground sets the start-up time.
If this pin is left floating, the regulator output soft-start ramp time is typically 100 µs.
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SBVS066R – DECEMBER 2005 – REVISED APRIL 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN, VBIAS
Input voltage
–0.3
6
V
VEN
Enable voltage
–0.3
6
V
VPG
Power-good voltage
–0.3
6
V
IPG
PG sink current
0
1.5
mA
VSS
SS pin voltage
–0.3
6
V
VFB
Feedback pin voltage
–0.3
6
V
VOUT
Output voltage
–0.3
VIN + 0.3
V
IOUT
Maximum output current
Internally limited
Output short-circuit duration
Indefinite
PDISS
Continuous total power dissipation
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
See Thermal Information
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
±2000
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input supply voltage range
VEN
Enable supply voltage range
VBIAS (1)
BIAS supply voltage range
IOUT
NOM
MAX
UNIT
1.1
5.5
V
0
5.5
V
VOUT + VDO (VBIAS)
5.5
V
Output current
0
3
A
COUT
Output capacitor
0
µF
CIN (2)
Input capacitor
1
µF
CBIAS
Bias capacitor
1
µF
TJ
Operating junction temperature
(1)
(2)
6
–40
125
°C
BIAS supply is required when VIN is below VOUT + VDO (VBIAS).
If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 µF.
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6.4 Thermal Information
TPS74401 (3)
THERMAL METRIC (1) (2)
RGW
(VQFN)
RGR
(VQFN)
KTW
(DDPAK)
20 PINS
20 PINS
7 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
35.4
39.1
26.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.4
29.3
41.7
°C/W
RθJB
Junction-to-board thermal resistance
14.7
10.2
12.5
°C/W
ψJT
Junction-to-top characterization parameter
0.4
0.4
4.0
°C/W
ψJB
Junction-to-board characterization parameter
14.8
10.1
7.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.9
2.0
0.3
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
Thermal data for the RGW, RGR, and KTW packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. RGW and RGR: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array.
- ii. KTW: The exposed pad is connected to the PCB ground layer through a 6x6 thermal via array.
(b) Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, refer to the Thermal Considerations section.
6.5 Electrical Characteristics
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CIN = CBIAS = 0.1 μF, COUT = 10 μF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = –40°C to 125°C,
unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN
Input voltage range
VBIAS
Bias pin voltage range
VREF
Internal reference
TJ = 25°C
Output voltage range
VIN = 5 V, IOUT = 1.5 A, VBIAS = 5 V
VREF
2.97 V ≤ VBIAS ≤ 5.25 V, VOUT + 1.62 V ≤ VBIAS,
50 mA ≤ IOUT ≤ 3.0 A (1)
–1%
±0.2%
1%
VOUT + VDO BIAS ≤ VBIAS ≤ 5.25 V,
100 mA ≤ IOUT ≤ I VDO BIAS , VQFN (2)
–1%
±0.2%
1%
VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V, VQFN
0.0005
0.05
VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V, DDPAK
0.0005
0.06
VOUT
ΔVOUT(ΔVIN)
Accuracy
Line regulation
ΔVOUT(ΔIOUT) Load regulation
VIN dropout voltage (3)
VDO
VBIAS dropout voltage
(3)
UNIT
VOUT + VDO
5.5
V
2.375
5.25
V
0.804
V
3.6
V
0.796
0.8
0 mA ≤ IOUT ≤ 50 mA
0.013
50 mA ≤ IOUT ≤ 3.0 A
0.03
IOUT = 3.0 A, VBIAS – VOUT(nom) ≥ 1.62 V, VQFN
115
195
IOUT = 3.0 A, VBIAS – VOUT(nom) ≥ 1.62 V, DDPAK
120
240
%/mA
%/A
IOUT = 3.0 A, VIN = VBIAS
1.62
IOUT = 3.0 A
1.62
IOUT = 1.0 A
1.35
IOUT = 500 mA
1.27
IOUT = 100 mA
%/V
mV
V
1.16
VOUT = 80% × VOUT(nom), VQFN
3.8
6.0
VOUT = 80% × VOUT(nom), DDPAK
3.5
6.0
ICL
Current limit
IBIAS
Bias pin current
IOUT = 0 mA to 3.0 A
2
4
ISHDN
Shutdown supply current (VIN)
VEN ≤ 0.4 V
1
100
μA
IFB
Feedback pin current (4)
IOUT = 50 mA to 3.0 A
95
250
nA
(1)
(2)
(3)
(4)
–250
A
mA
Devices tested at 0.8 V; external resistor tolerance is not taken into account.
VOUT is set to 1.5 V to avoid minimum VBIAS restrictions.
Dropout is defined as the voltage from the input to VOUT when VOUT is 2% below nominal.
IFB current flow is out of the device.
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Electrical Characteristics (continued)
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CIN = CBIAS = 0.1 μF, COUT = 10 μF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = –40°C to 125°C,
unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power-supply rejection
(VIN to VOUT)
1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V
73
800 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V
42
Power-supply rejection
(VBIAS to VOUT)
1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V
62
800 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V
50
Vn
Output noise voltage
100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 0.001 µF
16 × VOUT
µVRMS
VTRAN
%VOUT droop during load
transient
IOUT = 100 mA to 3.0 A at 1 A/µs, COUT = 0 µF
4
%VOUT
ISS
Soft-start charging current
VSS = 0.4 V
VEN(high)
Enable input high level
VEN(low)
Enable input low level
VEN(hys)
Enable pin hysteresis
IEN
Enable pin current
VEN = 5 V
VIT
PG trip threshold
VOUT decreasing
VHYS
PG trip hysteresis
VPG(low)
PG output low voltage
IPG = 1 mA (sinking), VOUT < VIT
IPG(lkg)
PG leakage current
VPG = 5.25 V, VOUT > VIT
TJ
Operating junction temperature
PSRR (5)
TSD
(5)
Thermal shutdown temperature
0.5
dB
dB
1
μA
1.1
0.73
5.5
V
0
0.4
50
86.5
0.1
1
90
93.5
3
–40
155
Reset, temperature decreasing
140
μA
%VOUT
%VOUT
0.03
Shutdown, temperature increasing
V
mV
0.3
V
1
μA
125
°C
°C
See Figure 8 to Figure 11 for PSRR at different conditions.
6.6 Timing Requirements
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CIN = CBIAS = 0.1 μF, COUT = 10 μF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = –40°C to 125°C,
unless otherwise noted. Typical values are at TJ = 25°C.
MIN
tSTR
Minimum startup time (IOUT = 1.5 A, CSS = open)
VEN(dg)
Enable pin de-glitch time
8
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NOM
MAX
UNIT
100
μs
20
μs
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6.7 Typical Characteristics
At TJ = 25°C, VOUT = 1.5 V, VIN = VOUT(nom) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 μF, CBIAS = 1 μF, CSS = 0.01 μF, and
COUT = 10 μF, unless otherwise noted.
1.0
0.050
Referred to IOUT = 50mA
0.9
Referred to IOUT = 50mA
0.025
0.7
0.6
-40°C
0.5
0.4
+25°C
0.3
0.2
0.1
0
Change in VOUT (%)
Change in VOUT (%)
0.8
-0.025
-40°C
-0.075
+125°C
-0.100
+125°C
0
+25°C
-0.050
-0.125
-0.150
-0.1
0
10
20
30
40
50
50
500
1000
Output Current (mA)
1500
2000
2500
3000
Output Current (mA)
Figure 1. Load Regulation
Figure 2. Load Regulation
0.05
200
0.04
0.02
TJ = -40°C
0.01
0
-0.01
TJ = +25°C
TJ = +125°C
-0.02
150
Dropout Voltage (mV)
Change in VOUT (%)
0.03
+125°C
100
50
-0.03
-40°C
-0.04
0
-0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
500
1000
VIN - VOUT (V)
2000
2500
3000
Figure 4. VIN Dropout Voltage vs IOUT and Temperature (TJ)
200
IOUT = 3.0A
IOUT = 1.5A
180
250
160
Dropout Voltage (mV)
+125°C
200
+25°C
150
1500
Output Current (mA)
Figure 3. Line Regulation
300
Dropout Voltage (mV)
+25°C
100
140
120
+125°C
100
+25°C
80
60
40
50
-40°C
-40°C
20
0
0
0.9
1.4
1.9
2.4
2.9
3.4
3.9
0.9
1.4
1.9
2.4
2.9
3.4
3.9
VBIAS - VOUT (V)
VBIAS - VOUT (V)
Figure 5. VIN Dropout Voltage vs VBIAS – VOUT and
Temperature (TJ)
Figure 6. VIN Dropout Voltage vs VBIAS – VOUT and
Temperature (TJ)
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Typical Characteristics (continued)
At TJ = 25°C, VOUT = 1.5 V, VIN = VOUT(nom) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 μF, CBIAS = 1 μF, CSS = 0.01 μF, and
COUT = 10 μF, unless otherwise noted.
1400
+125°C
1200
Power-Supply Rejection Ratio (dB)
Dropout Voltage (mV)
80
VIN = VBIAS
1300
+25°C
1100
1000
-40°C
900
800
700
600
500
IOUT = 3.0A
70
60
50
40
30
20
10
0
0
500
1000
1500
2000
2500
3000
10
100
1k
Output Current (mA)
Figure 7. VBIAS Dropout Voltage vs IOUT and Temperature
(TJ)
VIN = 1.8V, VOUT = 1.5V, IOUT = 100mA
90
80
COUT = 100mF C
OUT = 10mF
70
60
50
40
30
20
COUT = 0mF
10
100
0
100
1k
70
COUT = 100mF
60
COUT = 10mF
50
40
30
20
10
COUT = 0mF
100k
1M
10
10M
100
1k
10k
1M
Figure 9. VIN PSRR vs Frequency
Figure 10. VIN PSRR vs Frequency
80
70
60
COUT = 100mF
50
COUT = 10mF
40
30
20
10
COUT = 0mF
0
1kHz
80
70
700kHz
60
50
40
300kHz
30
1k
10k
100k
1M
10M
100kHz
20
COUT = 22mF
IOUT = 1.5A
10
0
100
10M
90
Power-Supply Rejection Ratio (dB)
VIN = 1.8V, VOUT = 1.5V, IOUT = 3A
10
100k
Frequency (Hz)
90
10M
80
Frequency (Hz)
100
Power-Supply Rejection Ratio (dB)
10k
1M
VIN = 1.8V, VOUT = 1.5V, IOUT = 1.5A
90
0
10
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
Frequency (Hz)
VIN - VOUT (V)
Figure 11. VIN PSRR vs Frequency
10
100k
Figure 8. VBIAS PSRR vs Frequency
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100
10k
Frequency (Hz)
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Figure 12. VIN PSRR vs VIN – VOUT
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Typical Characteristics (continued)
1
IOUT = 3A
VOUT = 1.1V
CSS = 1nF
CSS = 0nF
0.1
CSS = 10nF
0.01
100
1k
10k
1
Output Spectral Noise Density (mV/ÖHz)
Output Spectral Noise Density (mV/ÖHz)
At TJ = 25°C, VOUT = 1.5 V, VIN = VOUT(nom) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 μF, CBIAS = 1 μF, CSS = 0.01 μF, and
COUT = 10 μF, unless otherwise noted.
VOUT = 3.3 V
VOUT = 2.5 V
0.1
VOUT = 1.5 V
VOUT = 1.1 V
VOUT = 0.8 V
0.01
100
100k
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 13. Noise Spectral Density
Figure 14. Noise Spectral Density
2.85
3.0
+125°C
2.8
2.65
TJ = +125°C
2.6
2.45
Bias Current (mA)
Bias Current (mA)
VBIAS: VOUT + 1.62 V
IOUT: 3 A
CIN: 1 mF (Ceramic)
COUT: 1 mF (Ceramic)
R1, R2: (1% Resistors)
2.25
2.05
+25°C
1.85
1.65
-40°C
2.4
2.2
2.0
TJ = +25°C
1.8
1.6
TJ = -40°C
1.4
1.45
1.2
1.25
1.0
0
500
1000
1500
2000
2500
3000
2.0
2.5
3.0
3.5
Output Current (mA)
4.0
4.5
5.0
VBIAS (V)
Figure 15. IBIAS vs Output Current and Temperature
Figure 16. IBIAS vs VBIAS and VOUT
765
0.45
0.40
VBIAS = 2.375V
750
735
0.30
VBIAS = 5.5V
0.25
ISS (nA)
Bias Current (mA)
0.35
0.20
720
705
0.15
0.10
690
0.05
0
-40
675
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Junction Temperature (°C)
Junction Temperature (°C)
Figure 17. IBIAS Shutdown vs Temperature
Figure 18. Soft-Start Charging Current (ISS) vs Temperature
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Typical Characteristics (continued)
At TJ = 25°C, VOUT = 1.5 V, VIN = VOUT(nom) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 μF, CBIAS = 1 μF, CSS = 0.01 μF, and
COUT = 10 μF, unless otherwise noted.
VOL Low-Level PG Voltage (V)
1.0
0.9
50mV/div
0.8
50mV/div
0.7
50mV/div
0.6
0.5
50mV/div
0.4
COUT = 2 x 470mF (OSCON)
COUT = 100mF Cer.
COUT = 10mF Cer.
COUT = 0mF
0.3
3.0A
1A/ms
0.2
2A/div
0.1
100mA
0
Time (50ms/div)
0
2
6
4
8
10
12
PG Current (mA)
Figure 20. Load Transient Response
Figure 19. Low-Level PG Voltage vs PG Current
COUT = 2 x 470mF
COUT = 2 x 470mF (OSCON)
10mV/div
COUT = 100mF (Cer.)
10mV/div
COUT = 100mF (Cer.)
10mV/div
COUT = 10mF (Cer.)
10mV/div
COUT = 10mF (Cer.)
10mV/div
COUT = 0mF
10mV/div
COUT = 0mF
10mV/div
2.5V
4.3V
1V/ms
1V/ms
500mV/div
500mV/div
3.3V
1.5V
Time (50ms/div)
Time (50ms/div)
Figure 21. VBIAS Line Transient (3 A)
CSS = 0mF
CSS = 0.001mF
Figure 22. VIN Line Transient (3 A)
VOUT
VIN = VBIAS = VEN
CSS = 0.0047mF
1V/div
500mV/div
1.1V
1V/div
VPG (500mV/div)
VEN
0V
Time (1ms/div)
VOUT
Time (20ms/div)
Figure 23. Turn-On Response
12
VOUT = 1.2V
(OSCON)
10mV/div
Figure 24. Power-Up, Power-Down
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Typical Characteristics (continued)
At TJ = 25°C, VOUT = 1.5 V, VIN = VOUT(nom) + 0.3 V, VBIAS = 3.3 V, IOUT = 50 mA, CIN = 1 μF, CBIAS = 1 μF, CSS = 0.01 μF, and
COUT = 10 μF, unless otherwise noted.
VOUT = 0.8V
IOUT
1A/div
VOUT
50mV/div
Output Shorted
Output Open
Time (20ms/div)
Figure 25. Output Short-Circuit Recovery
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7 Detailed Description
7.1 Overview
The TPS74401 family of low-dropout regulators (LDOs) incorporates many features to ensure a wide range of
uses. Hysteresis and de-glitch on the EN input improve the ability to sequence multiple devices without worrying
about false start-up. The soft-start is fully programmable and allows the user to control the startup time of the
LDO output. Hysteresis is also available on the PG comparator to ensure no false PG signals. The TPS74401
family of LDOs is ideal for FPGAs, DSPs, and any other device that requires linear supply and sequencing.
7.2 Functional Block Diagram
IN
Current
Limit
BIAS
UVLO
OUT
Thermal
Limit
0.73mA
VOUT
R1
SS
CSS
Soft-Start
Discharge
VOUT = 0.8 x (1 +
0.8V
Reference
R1
)
R2
FB
PG
EN
Hysteresis
and De-Glitch
R2
0.9 ´ VREF
GND
7.3 Feature Description
7.3.1 Enable, Shutdown
The enable (EN) pin is active high and compatible with standard digital signaling levels. VEN lower than 0.4 V
turns the regulator off, whereas VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable
circuitry has hysteresis and de-glitching for use with relatively slow-ramping analog signals. This configuration
allows the TPS74401 to be enabled by connecting the output of another supply to the EN pin. The enable
circuitry typically has 50 mV of hysteresis and a de-glitch circuit to help avoid on-off cycling resulting from small
glitches in the VEN signal.
The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature
variation is approximately –1 mV/°C; therefore, process variation accounts for most of the variation in the enable
threshold. If precise turn-on timing is required, use a fast rise-time signal to enable the TPS74401.
If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, connect EN as close as possible
to the largest capacitance on the input to prevent voltage droops on that line from triggering the enable circuit.
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Feature Description (continued)
7.3.2 Power-Good (VQFN Package Only)
The power-good (PG) pin is an open-drain output and can be connected to any 5.5 V or lower rail through an
external pullup resistor. This pin requires at least 1.1 V on VBIAS in order to have a valid output. The PG output is
high-impedance when VOUT is greater than (VIT + VHYS). If VOUT drops below VIT or if VBIAS drops below 1.9 V, the
open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled.
The recommended operating condition of the PG pin sink current is up to 1 mA, thus the pullup resistor for PG
must be in the range of 10 kΩ to 1 MΩ. PG is only provided on the VQFN package. If output voltage monitoring
is not needed, the PG pin can be left floating.
7.3.3 Internal Current Limit
The TPS74401 features a factory-trimmed, accurate current limit that is flat over temperature and supply voltage.
The current limit allows the device to supply surges of up to 3.5 A and maintain regulation. The current limit
responds in approximately 10 μs to reduce the current during a short-circuit fault. Recovery from a short-circuit
condition is well-controlled and results in very little output overshoot when the load is removed. See Figure 25 in
the Typical Characteristics section for short-circuit recovery performance.
The internal current limit protection circuitry of the TPS74401 is designed to protect against overload conditions.
This circuitry is not intended to allow operation above the rated current of the device. Continuously running the
TPS74401 above the rated current degrades device reliability.
7.3.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 155°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit can
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For
reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety in a complete
design (including heatsink), increase the ambient temperature until thermal protection is triggered; use worstcase loads and signal conditions. For good reliability, trigger thermal protection at least 30°C above the
maximum expected ambient condition of the application. This condition produces a worst-case junction
temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS74401 is designed to protect against overload conditions. This circuitry
is not intended to replace proper heatsinking. Continuously running the TPS74401 into thermal shutdown
degrades device reliability.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
•
•
The input voltage and bias voltage are both at least at the respective minimum specifications.
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
The output current is less than the current limit.
The device junction temperature is less than the maximum specified junction temperature.
The device is not operating in dropout.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout can result in large output voltage deviations.
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Device Functional Modes (continued)
7.4.3 Disabled
The device is disabled under the following conditions:
• The input or bias voltages are below the respective minimum specifications.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
VBIAS
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO (VIN)
VEN > VEN(high)
VBIAS ≥ VOUT + 1.62 V
I OUT < ICL
T J < 125°C
Dropout mode
VIN < VOUT(nom) + VDO (VIN)
VEN > VEN(high)
VBIAS < VOUT + 1.62 V
—
TJ < 125°C
VIN < VIN(min)
VEN < VEN(low)
VBIAS < VBIAS(min)
—
TJ > 155°C
Disabled mode
(any true condition disables
the device)
7.5 Programming
7.5.1 Programmable Soft-Start
The TPS74401 features a programmable, monotonic, voltage-controlled soft-start that is set with an external
capacitor (CSS). This feature is important for many applications to eliminate power-up initialization problems when
powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush
current during start-up, minimizing start-up transients to the input power bus.
To achieve a linear and monotonic soft-start, the TPS74401 error amplifier tracks the voltage ramp of the
external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on
the soft-start charging current (ISS), the soft-start capacitance (CSS), and the internal reference voltage (VREF),
and can be calculated using Equation 1:
VREF u CSS
t SS
ISS
(1)
If large output capacitors are used, the device current limit (ICL) and the output capacitor can set the start-up
time. In this case, the start-up time is given by Equation 2:
(V
´ COUT)
tSSCL = OUT(nom)
ICL(min)
where
•
•
•
VOUT(nom) is the nominal set output voltage as set by the user,
COUT is the output capacitance,
and ICL(min) is the minimum current limit for the device.
(2)
In applications where monotonic startup is required, the soft-start time given by Equation 1 must be set to be
greater than Equation 2.
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Programming (continued)
The maximum recommended soft-start capacitor is 0.015 μF. Larger soft-start capacitors can be used and do not
damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the softstart capacitor when re-enabled. Soft-start capacitors larger than 0.015 μF can be a problem in applications
where the user must rapidly pulse the enable pin and also require the device to soft-start from ground. CSS must
be low-leakage; X7R, X5R, or C0G dielectric materials are preferred. Table 2 lists suggested soft-start capacitor
values.
Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1)
tSS(s) =
(1)
CSS
SOFT-START TIME
Open
0.1 ms
470 pF
0.5 ms
1000 pF
1 ms
4700 pF
5 ms
0.01 μF
10 ms
0.015 μF
16 ms
VREF × CSS 0.8V × CSS(F)
=
0.73mA
ISS
where tSS(s) = soft-start time in seconds.
7.5.2 Sequencing Requirements
The device can have VIN, VBIAS, and VEN sequenced in any order without causing damage to the device.
However, for the soft-start function to work as intended, certain sequencing rules must be applied. Enabling the
device after VIN and VBIAS are present is preferred, and can be accomplished using a digital output from a
processor or supply supervisor. An analog signal from an external RC circuit, as shown in Figure 26, can also be
used as long as the delay time is long enough for VIN and VBIAS to be present.
VIN
IN
VOUT
OUT
CIN
1mF
R1
BIAS TPS74401
FB
R2
R
VBIAS
CBIAS
1mF
EN
GND
SS
C
CSS
Figure 26. Soft-Start Delay Using an RC Circuit on Enable
If a signal is not available to enable the device after IN and BIAS, simply connecting EN to IN is acceptable for
most applications as long as VIN is greater than 1.1 V and the ramp rate of VIN and VBIAS is faster the set softstart ramp rate. If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the
slower supply less the dropout voltage until the set output voltage is reached. If EN is connected to BIAS, the
device soft-starts as programmed, provided that VIN is present before VBIAS. If VBIAS and VEN are present before
VIN is applied and the set soft-start time has expired, then VOUT tracks VIN.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS74401 belongs to a family of ultra-low dropout regulators that feature soft-start. These regulators use a
low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very
low output voltages with low VIN to VOUT headroom.
The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology
device, the output capacitor has little affect on loop stability. This architecture allows the TPS74401 to be stable
with any or even no output capacitor. Transient response is also superior to PMOS topologies, particularly for low
VIN applications.
The TPS74401 features a programmable, voltage-controlled soft-start circuit that provides a smooth, monotonic
start-up and limits startup inrush currents that can be caused by large capacitive loads. A power-good (PG)
output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with
hysteresis and de-glitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply
voltages often present in processor intensive systems.
8.1.1 Input, Output, and Bias Capacitor Requirements
The TPS74401 does not require any output capacitor for stability. If an output capacitor is needed, the device is
designed to be stable for all available types and values of output capacitance. The device is also stable with
multiple capacitors in parallel, of any type or value. This flexibility is a result of an innovative control loop that
ensures the device is stable independent of the output capacitance.
The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To
counteract any inductance in the input, the minimum recommended capacitor for VIN and VBIAS is 1 μF. If VIN and
VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7 μF. Use good
quality, low-ESR capacitors on the input; ceramic X5R and X7R capacitors are preferred. Place these capacitors
as close to the pins as possible for optimum performance and to help ensure stability.
8.1.2 Transient Response
The TPS74401 is designed to have transient response within 5% for most applications without an output
capacitor. In some cases, the transient response can be limited by the transient response of the input supply.
This limitation is especially true in applications where the difference between the input and output is less than
300 mV. In this case, adding additional input capacitance improves the transient response much more than just
adding additional output capacitance. With a solid input supply, adding additional output capacitance reduces
undershoot and overshoot during a transient at the expense of a slightly longer VOUT recovery time; see
Figure 20 in the Typical Characteristics section. Because the TPS74401 is stable without an output capacitor,
many applications can allow for little or no capacitance at the LDO output. For these applications, local bypass
capacitance for the device under power can be sufficient to meet the transient requirements of the application.
This design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the
LDO output.
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Application Information (continued)
8.1.3 Dropout Voltage
The TPS74401 offers industry-leading dropout performance, making the device well-suited for high-current, low
VIN and low VOUT applications. The extremely low dropout of the TPS74401 also allows the device to be used in
place of a dc/dc converter and also achieve good efficiencies. Equation 3 provides a quick estimate of the
efficiencies.
VOUT ´ IOUT
V
» OUT at IOUT >> IQ
Efficiency »
VIN
VIN ´ (IIN + IQ)
(3)
This efficiency allows users to redesign the power architecture for their applications to achieve the smallest,
simplest, and lowest cost solution.
There are two different specifications for dropout voltage with the TPS74401. The first specification (see
Figure 38) is referred to as VIN Dropout and is for users who wish to apply an external bias voltage to achieve
low dropout. This specification assumes that VBIAS is at least 1.62 V above VOUT; for example, when VBIAS is
powered by a 3.3-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than (3.3 V × 0.95) or VOUT is
less than 1.5 V, VIN dropout is less than specified.
The second specification (see Figure 39) is referred to as VBIAS Dropout and is for users who wish to have VBIAS
< VIN + 1.62 V. This option allows the device to be used in applications where an auxiliary bias voltage is not
available or low dropout is not required. Dropout is limited by BIAS in these applications because VBIAS provides
the gate drive to the pass FET and therefore must be greater than VOUT + VDO (VBIAS). Because of this usage, IN
and BIAS tied together easily consume excessive power. Pay attention and do not exceed the power rating of
the IC package.
8.1.4 Output Noise
The TPS74401 provides low output noise when a soft-start capacitor is used. When the device reaches the end
of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001-μF
soft-start capacitor, the output noise is reduced by half and is typically 19 μVRMS for a 1.2-V output (100 Hz to
100 kHz). Noise is a function of the set output voltage because most of the output noise is generated by the
internal reference. The RMS noise with a 0.001-μF soft-start capacitor is given in Equation 4.
§ µV
·
VN µVRMS
16 ¨ RMS ¸ u VOUT (V)
V
©
¹
(4)
The low output noise of the TPS74401 makes the device a good choice for powering transceivers, PLLs, or other
noise-sensitive circuitry.
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8.2 Typical Applications
8.2.1 Setting the TPS74401
Figure 27 shows a typical application circuit for the TPS74401.
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 27. Table 3 lists sample
resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2 must be
≤ 4.99 kΩ.
VIN
IN
CIN
1mF
VPG
PG
RPULLUP
EN
VOUT
OUT
BIAS TPS74401
VBIAS
R1
SS
CBIAS
1mF
GND
FB
CSS
COUT
Optional
R2
R1 =
VOUT
- 1 ´ R2
VREF
Figure 27. Typical Application Circuit for the TPS74401
Table 3. Standard 1% Resistor Values for Programming the Output Voltage (1)
(1)
R1 (kΩ)
R2 (kΩ)
VOUT (V)
Short
Open
0.8
0.619
4.99
0.9
1.13
4.53
1.0
1.37
4.42
1.05
1.87
4.99
1.1
2.49
4.99
1.2
4.12
4.75
1.5
3.57
2.87
1.8
3.57
1.69
2.5
3.57
1.15
3.3
VOUT = 0.8 × (1 + R1 / R2).
NOTE
When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately
50 μA of current from OUT. Although this condition does not cause any damage to the
device, the output current can charge up the OUT node if total resistance between OUT
and GND (including external feedback resistors) is greater than 10 kΩ.
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8.2.1.1 Design Requirements
The design goals are VIN = 1.8 V, VOUT = 1.5 V, and IOUT = 2 A max. The design optimizes transient response
while meeting a 1-ms startup time with a startup dominated by the soft-start feature. The input supply comes
from a supply on the same circuit board. The available system rails for VBIAS are 2.7 V, 3.3 V, and 5 V.
The design space consists of CIN, COUT, CBIAS, CSS, VBIAS, R1, R2, and R3, and the circuit is from Figure 27.
This example uses a VIN of 1.8 V, with a VBIAS of 2.5 V.
8.2.1.2 Detailed Design Procedure
The first step for this design is to examine the maximum load current along with the input and output voltage
requirements, to determine if the device thermal and dropout voltage requirements can be met. At 3 A, the input
dropout voltage of the TPS74401 family is a maximum of 240 mV over temperature. As a result, the dropout
headroom is sufficient for operation over both input and output voltage accuracy.
The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass element
from the input to the output multiplied by the maximum load current. In this example, the maximum voltage drop
across in the pass element is (1.8 V – 1.5 V), giving a VDROP = 300 mV. The power dissipated can than be
estimated by the equation PDISS = IL(max) × VDROP = ~600 mW. This calculation gives an efficiency of nearly
83.3% by using Equation 3.
When the power dissipated in the linear regulator is known, the corresponding junction temperature increase can
be calculated. To estimate the junction temperature increase above ambient, the power dissipated must be
multiplied by the junction-to-ambient thermal resistance. For thermal resistance information, refer to the Thermal
Information table. For this example, using the KTW package, the junction temperature rise is calculated to be
21.2°C. The maximum junction temperature increase is calculated by adding the junction temperature rise to the
maximum ambient temperature. In this example, the maximum junction temperature is 46.2°C. Keep in mind that
the junction temperature must be less than 125°C for reliable operation. Additional ground planes, added thermal
vias, and air flow all help to improve the thermal transfer characteristics of the system.
The next step is to determine the bias voltage or if a separate source is needed for the bias voltage. Because VIN
is less than VOUT plus the VBIAS dropout, VBIAS must be an independent supply. VBIAS = VOUT + 1.62 V = 3.12 V;
the system has a 3.3-V rail to use for this supply and also to provide some limited headroom for VBIAS. The 5-V
rail is a better choice to improve the performance of the LDO, so the 5-V rail is used.
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8.2.1.3 Application Curves
CSS = 0mF
VOUT
CSS = 0.001mF
VIN = VBIAS = VEN
CSS = 0.0047mF
VPG (500mV/div)
1V/div
500mV/div
1.1V
1V/div
VEN
VOUT
0V
Time (1ms/div)
Time (20ms/div)
Figure 28. Turn-On Response
50mV/div
50mV/div
50mV/div
50mV/div
Figure 29. Power-Up, Power-Down
COUT = 2 x 470mF
COUT = 2 x 470mF (OSCON)
COUT = 100mF Cer.
10mV/div
COUT = 10mF Cer.
10mV/div
COUT = 0mF
10mV/div
VOUT = 1.2V
(OSCON)
10mV/div
COUT = 100mF (Cer.)
COUT = 10mF (Cer.)
COUT = 0mF
2.5V
1A/ms
2A/div
1V/ms
3.0A
500mV/div
100mA
1.5V
Time (50ms/div)
Time (50ms/div)
Figure 30. Load Transient Response
10mV/div
10mV/div
10mV/div
10mV/div
Figure 31. VIN Line Transient (3 A)
VOUT = 0.8V
COUT = 2 x 470mF (OSCON)
COUT = 100mF (Cer.)
COUT = 10mF (Cer.)
COUT = 0mF
IOUT
1A/div
VOUT
50mV/div
Output Shorted
4.3V
1V/ms
500mV/div
Output Open
3.3V
Time (50ms/div)
Time (20ms/div)
Figure 32. VBIAS Line Transient (3 A)
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300
200
IOUT = 3.0A
+125°C
100
50
-40°C
+125°C
Dropout Voltage (mV)
Dropout Voltage (mV)
250
150
200
100
50
+25°C
-40°C
0
0
0
500
1000
1500
2000
2500
0.9
3000
1.4
1.9
2.4
2.9
3.4
3.9
Output Current (mA)
VBIAS - VOUT (V)
Figure 34. VIN Dropout Voltage vs IOUT and Temperature
(TJ)
Figure 35. VIN Dropout Voltage vs VBIAS – VOUT and
Temperature (TJ)
200
1400
IOUT = 1.5A
180
VIN = VBIAS
1300
Dropout Voltage (mV)
160
Dropout Voltage (mV)
+25°C
150
140
120
+125°C
100
+25°C
80
60
40
-40°C
20
+125°C
1200
+25°C
1100
1000
-40°C
900
800
700
600
0
500
0.9
1.4
1.9
2.4
2.9
3.4
3.9
0
500
VBIAS - VOUT (V)
1000
1500
2000
2500
3000
Output Current (mA)
Figure 36. VIN Dropout Voltage vs VBIAS – VOUT and
Temperature (TJ)
Figure 37. VBIAS Dropout Voltage vs IOUT and Temperature
(TJ)
8.2.2 Using an Auxiliary Bias Rail
Figure 38 shows a typical application of the TPS74401 using an auxiliary bias rail. The auxiliary bias rail allows
for the designer to specify the system to have a low VDO. The bias rail supplies the error amplifier with a higher
supply voltage, increasing the voltage that can be applied to the gate of the pass device.
VBIAS must be at least VOUT + 1.62 V.
BIAS
Reference
IN
VBIAS = 5V ± 5%
VIN = 1.8V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 83%
OUT
VOUT
FB
Simplified Block Diagram
Figure 38. Typical Application of the TPS74401 Using an Auxiliary Bias Rail
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8.2.3 Without an Auxiliary Bias
The TPS74401 family is capable of operating without a bias rail if VIN ≥ VOUT + VDO (VBIAS). Additional
capacitance is advised for this scenario, with at least 4.7 µF of capacitance near the input pin. Figure 39 shows a
typical application of the TPS74401 without an auxiliary bias.
If using the TPS74401 in this situation and under high load conditions, ensure that the printed circuit board (PCB)
provides adequate thermal handling capabilities to keep the device in its recommended operating range. See the
Power Supply Recommendations section for more information.
VIN
BIAS
Reference
IN
VBIAS = 3.3V ± 5%
VIN = 3.3V ± 5%
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 45%
OUT
VOUT
FB
Simplified Block Diagram
Figure 39. Typical Application of the TPS74401 Without an Auxiliary Bias
9 Power Supply Recommendations
The TPS74401 is designed to operate from an input voltage between 1.1 V to 5.5 V, provided the bias rail is at
least 1.62 V higher than the input supply. The bias rail and the input supply must both provide adequate
headroom and current for the device to operate normally.
Connect a low output impedance power supply directly to the IN pin of the TPS74401. This supply must have at
least 1 µF of capacitance near the IN pin for stability. A supply with similar requirements must also be connected
directly to the bias rail with a separate 1 µF or larger capacitor.
If the IN pin is tied to the bias pin, a minimum 4.7 µF of capacitance is needed for stability.
To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or ferrite bead before the input
capacitor.
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10 Layout
10.1 Layout Guidelines
An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop
on the input of the device during load transients, connect the capacitance on IN and BIAS as close as possible to
the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source
and can therefore improve stability. To achieve optimal transient performance and accuracy, connect the top side
of R1 in Figure 27 as close as possible to the load. This connection minimizes the voltage droop on BIAS during
transient conditions and can improve the turn-on response.
10.2 Layout Example
Input GND Plane
IN
NC
NC
NC
OUT
Cin
5
4
3
2
1
Vin Plane
R(pull-up)
Vout Plane
IN
6
20 OUT
IN
7
19 OUT
IN
8
PG
9
17
NC
BIAS
10
16
FB/
SNS
18 OUT
Thermal Pad
Cout
11
12
13
14
14
15
GND
NC
NC
SS
Cbias
EN
R1
R1 & R2 should be
connected close to the load,
Cout should be as near to
the LDO as possible
R2
Css
Keep the ground planes on
the same side of the PCB if
possible to improve thermal
disappation
Output GND Plane
Figure 40. Layout Schematic (VQFN Packages)
10.3 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions, and can be calculated using
Equation 5:
PD = (VIN - VOUT ) ´ IOUT
(5)
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Power Dissipation (continued)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the VQFN (RGW, RGR) packages, the primary conduction path for heat is through the exposed pad to the
PCB. The pad can be connected to ground or left floating; however, the pad must be attached to an appropriate
amount of copper PCB area to ensure the device does not overheat. On the DDPAK (KTW) package, the
primary conduction path for heat is through the tab to the PCB. Connect that tab to ground. The maximum
junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction
temperature, and power dissipation of the device and can be estimated using Equation 6:
( +125°C - TA )
RqJA =
PD
(6)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 41.
120
100
qJA (°C/W)
80
60
qJA (RGW)
40
20
qJA (KTW)
0
0
1
2
3
4
5
7
6
8
9
10
2
Board Copper Area (in )
Note:
2
θJA value at board size of 9 in (that is, 3 in × 3 in) is a JEDEC standard.
Figure 41. θJA versus Board Size
Figure 41 shows the variation of θJA as a function of ground plane copper area in the board. Figure 41 is
intended only as a guideline to demonstrate the affects of heat spreading in the ground plane; do not use
Figure 41 to estimate actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, TI strongly recommends using ΨJT
and ΨJB, as explained in the section.
10.4 Thermal Considerations
A better method of estimating the thermal measure comes from using the thermal metrics ΨJT and ΨJB, as shown
in Thermal Information . These metrics are a more accurate representation of the heat transfer characteristics of
the die and the package than RθJA. The junction temperature can be estimated with the corresponding formulas
given in Equation 7.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 5,
TT is the temperature at the center-top of the IC package, and
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (see Figure 42).
(7)
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Thermal Considerations (continued)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
(1)
TT on top of IC
TB on PCB
TT on top of IC
1mm
TB on PCB
surface
(2)
1mm
(a) Example RGW (QFN) Package Measurement
(1)
TT is measured at the center of both the X- and Y-dimensional axes.
(2)
TB is measured below the package lead on the PCB surface.
(b) Example KTW (DDPAK) Package Measurement
Figure 42. Measuring Points for TT and TB
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Compared with θJA, the thermal metrics ΨJT and ΨJB are less independent of board size, but do have a small
dependency on board size and layout. Figure 43 shows characteristic performance of ΨJT and ΨJB versus board
size.
Referring to Figure 43, the RGW package thermal performance has negligible dependency on board size. The
KTW package, however, does have a measurable dependency on board size. This dependency exists because
the package shape is not point symmetric to an IC center. In the KTW package, for example (see Figure 42),
silicon is not beneath the measuring point of TT which is the center of the X and Y dimension, so that ΨJT has a
dependency. Also, because of that non-point symmetry, device heat distribution on the PCB is not point
symmetric either, so that ΨJB has a greater dependency on board size and layout.
12
YJT and YJB (°C/W)
10
YJB (RGW)
8
YJB (KTW)
6
4
YJT (KTW)
2
YJT (RGW)
0
0
2
4
6
8
10
2
Board Copper Area (in )
Figure 43. ΨJT and ΨJB versus Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
refer to the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com. Also,
refer to the application note IC Package Thermal Metrics (SPRA953) (also available on the TI website) for further
information.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS74401. The TPS74401EVM-118 evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS74401 is available through the product folders under
Tools & Software.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• 6A Current-Sharing Dual LDO reference design
• Using New Thermal Metrics application report
• IC Package Thermal Metrics application report
• TPS74401EVM-118 Evaluation Module User Guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS74401KTWR
ACTIVE
DDPAK/
TO-263
KTW
7
500
RoHS & Green
Call TI | SN
Level-3-245C-168 HR
-40 to 125
TPS74401
TPS74401KTWRG3
ACTIVE
DDPAK/
TO-263
KTW
7
500
RoHS & Green
SN
Level-3-245C-168 HR
-40 to 125
TPS74401
TPS74401RGRR
ACTIVE
VQFN
RGR
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
12KA
TPS74401RGRT
ACTIVE
VQFN
RGR
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
12KA
TPS74401RGWR
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
74401
TPS74401RGWRG4
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
74401
TPS74401RGWT
ACTIVE
VQFN
RGW
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
74401
TPS74401RGWTG4
ACTIVE
VQFN
RGW
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
74401
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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