TPS793475DBVRG4Q1

TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 ULTRALOW-NOISE, HIGH-PSRR, FAST RF 200-mA LOW-DROPOUT LINEAR REGULATORS FEATURES • • • • • • • • • • • • • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) 200-mA Low-Dropout Regulator With EN Available in 1.8 V, 2.5 V, 2.8 V, 2.85 V, 3 V, 3.3 V, 4.75 V, and Adjustable High PSRR (70 dB at 10 kHz) Ultralow Noise (32 µV) Fast Start-Up Time (50 µs) Stable With a 2.2-µF Ceramic Capacitor Excellent Load/Line Transient Very Low Dropout Voltage (112 mV at Full Load, TPS79330) 5-Pin SOT23 (DBV) Package APPLICATIONS • • • (1) VCOs RF Bluetooth™, Wireless LAN Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over specified temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DBV PACKAGE (TOP VIEW) IN 1 GND 2 EN 3 5 OUT 4 BYPASS Fixed Option DBV PACKAGE (TOP VIEW) IN 1 6 OUT GND 2 5 FB EN 3 4 BYPASS Adjustable Option DESCRIPTION The TPS793xx family of low-dropout (LDO) low-power linear voltage regulators features high power-supply rejection ratio (PSRR), ultralow noise, fast start-up, and excellent line and load transient responses in a small-outline SOT23 package. Each device in the family is stable, with a small 2.2-µF ceramic capacitor on the output. The TPS793xx family uses an advanced, proprietary, BiCMOS fabrication process to yield extremely low dropout voltages (e.g., 112 mV at 200 mA, TPS79330). Each device achieves fast start-up times (approximately 50 µs with a 0.001-µF bypass capacitor), while consuming very low quiescent current (170 µA typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 µA. The TPS79328 exhibits approximately 32 µVRMS of output voltage noise with a 0.1-µF bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR and low-noise features, as well as the fast response time. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a trademark of Bluetooth SIG, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2006, Texas Instruments Incorporated TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 TPS79328 TPS79328 RIPPLE REJECTION vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY Hz 100 90 µ V/ IO = 200 mA Output Spectral Noise Density − Ripple Rejection − dB 80 70 60 50 40 IO = 10 mA 30 20 VI = 3.8 V Co = 10 µF C(byp) = 0.01 µF 10 0 10 100 1k 10 k 100 k 1M 10 M 0.3 VI = 3.8 V Co = 2.2 µF C(byp) = 0.1 µF 0.25 0.2 0.15 IO = 1 mA 0.1 IO = 200 mA 0.05 0 100 f − Frequency − Hz 1k 10 k f − Frequency − Hz 100 k AVAILABLE OPTIONS TJ –40°C to 125°C –55°C to 125°C (1) (2) 2 VOLTAGE PACKAGE PART NUMBER SYMBOL 1.2 to 5.5 V TPS79301DBVREP (1) 1.8 V TPS79318DBVREP (1) PHHE 2.5 V TPS79325DBVREP (1) PGWE TPS79328DBVREP (1) (2) PGXE 2.8 V SOT23 (DBV) PGVE TPS793285DBVREP (1) (2) PHIE 3V TPS79330DBVREP (1) (2) PGYE 3.3 V TPS793333DBVREP (1) PHUE 4.75 V TPS793475DBVREP (1) PHJE 1.2 to 5.5 V TPS79301MDBVREP (1) PMBM 2.85 V The DBVR indicates tape and reel of 3000 parts. Product preview Submit Documentation Feedback TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Input voltage range (2) Voltage range at EN Voltage on OUT MIN MAX –0.3 6 V –0.3 VI + 0.3 V 6 V –0.3 Peak output current UNIT Internally limited Human-Body Model (HBM) ESD rating Changed-Device Model (CDM) 2 kV 500 V See Dissipation Rating Table Continuous total power dissipation TJ Operating virtual junction temperature range –55 125 °C Tstg Storage temperature range –65 150 °C (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal Dissipation Ratings BOARD PACKAGE RθJC RθJA DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING Low K (1) DBV 63.75°C/W 256°C/W 3.906 mW/°C 391 mW 215 mW 156 mW K (2) DBV 63.75°C/W 178.3°C/W 5.609 mW/°C 561 mW 308 mW 224 mW High (1) (2) The JEDEC low K (1s) board design used to derive this data was a 3-in × 3-in, two layer board with 2-oz copper traces on top of the board. The JEDEC high K (2s2p) board design used to derive this data was a 3-in × 3-in, multilayer board with 1-oz internal power and ground planes and 2-oz copper traces on top and bottom of the board. Submit Documentation Feedback 3 TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, EN = VI, TJ = –55 to 125°C and TJ = –40 to 125°C, VI = VO(typ) + 1 V, IO = 1 mA, Co = 10 µF, C(byp) = 0.01 µF (unless otherwise noted) PARAMETER TEST CONDITIONS VI Input voltage (1) IO Continuous output current (2) TJ Operating junction temperature TPS79301 TPS79318 TPS79325 Output voltage TPS79328 TPS793285 TPS79330 TPS79333 TPS793475 Quiescent current (GND current) MIN TYP V 0 200 mA –55 125 °C 0 µA < IO < 200 mA, 1.22 V ≤ VO ≤ 5.2 V (3) TJ = –40 to 125°C, 0.98 Vo 1.02 Vo 0 µA < IO < 200 mA, 1.22 V ≤ VO ≤ 5.2 V (3) TJ = –55 to 125°C, 0.97 Vo 1.025 Vo TJ = 25°C 0 µA < IO < 200 mA, 1.8 2.8 V < VI < 5.5 V 1.764 TJ = 25°C 0 µA < IO < 200 mA, 3.5 V < VI < 5.5 V 2.45 3.8 V < VI < 5.5 V 2.744 3.85 V < VI < 5.5 V 2.793 Output voltage line regulation (∆VO/VO) (4) 4 V < VI < 5.5 V 2.907 2.94 3.06 3.3 4.3 V < VI < 5.5 V 3.234 TJ = 25°C 3.366 4.75 0 µA < IO < 200 mA, 5.25 V < VI < 5.5 V 0 µA < IO < 200 mA, TJ = 25°C 4.655 4.845 170 Output noise voltage (TPS79328) TJ = 25°C 5 VO + 1 V < VI ≤ 5.5 V, TJ = 25°C 0.05 VO + 1 V < VI ≤ 5.5 V RL = 14 Ω, Co = 1 µF, TJ = 25°C Time, start-up (TPS79328) 220 0 µA < IO < 200 mA, BW = 200 Hz to 100 kHz, IO = 200 mA, TJ = 25°C Output current limit VO = 0 V (3) Standby current EN = 0 V, High-level enable input voltage 2.7 V < VI < 5.5 V Low-level enable input voltage 2.7 V < VI < 5.5 V Input current (EN) EN = 0 V 3 TJ = 25°C 0 µA < IO < 200 mA, 2.856 2.85 TJ = 25°C 0 µA < IO < 200 mA, 2.55 2.8 TJ = 25°C 0 µA < IO < 200 mA, 1.836 2.5 TJ = 25°C 0 µA < IO < 200 mA, UNIT 5.5 0 µA < IO < 200 mA Load regulation MAX 2.7 mV 0.12 C(byp) = 0.001 µF 55 C(byp) = 0.0047 µF 36 C(byp) = 0.01 µF 33 C(byp) = 0.1 µF 32 C(byp) = 0.001 µF 50 C(byp) = 0.0047 µF µs 100 285 2.7 V < VI < 5.5 V (1) %/V µVRMS 70 C(byp) = 0.01 µF µA 0.07 600 mA 1 µA 2 –1 V 0.7 V 1 µA To calculate the minimum input voltage for your maximum output current, use the following formula: VI(min) = VO(max) + VDO (max load) (2) Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. (3) The minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. The maximum IN voltage is 5.5 V. The maximum output current is 200 mA. (4) If VO ≤ 2.5 V, then VImin = 2.7 V, VImax = 5.5 V: V V * 2.7 V O Imax Line Reg. (mV) + ǒ%ńVǓ 1000 100 If VO ≥ 2.5 V, then VImin = VO + 1 V, VImax = 5.5 V. ǒ 4 Ǔ Submit Documentation Feedback TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range, EN = VI, TJ = –55 to 125°C and TJ = –40 to 125°C, VI = VO(typ) + 1 V, IO = 1 mA, Co = 10 µF, C(byp) = 0.01 µF (unless otherwise noted) PARAMETER Input current (FB) (TPS79301) Power-supply ripple rejection TPS79328 TPS79328 TPS793285 Dropout voltage (5) TPS79330 TPS79333 TPS793475 TEST CONDITIONS TYP IO = 10 mA 70 f = 100 Hz, TJ = 25°C, IO = 200 mA 68 f = 10 Hz, TJ = 25°C, IO = 200 mA 70 f = 100 Hz, TJ = 25°C, IO = 200 mA 43 IO = 200 mA, TJ = 25°C 120 TJ= 25°C 120 TJ = 25°C 112 IO = 200 mA IO = 200 mA, TJ = 25°C 102 TJ = 25°C 77 VCC rising TJ = 25°C mV 180 IO = 200 mA UVLO hysteresis dB 200 IO = 200 mA IO = 200 mA, µA 200 IO = 200 mA IO = 200 mA, UNIT 200 IO = 200 mA IO = 200 mA, MAX 1 f = 100 Hz, TJ = 25°C, UVLO threshold (5) MIN FB = 1.8 V 125 2.25 VCC rising 2.65 100 V mV IN voltage equals VO(typ)– 100 mV; The TPS79325 dropout voltage is limited by the input voltage range limitations. Submit Documentation Feedback 5 TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM – ADJUSTABLE VERSION VOUT VIN Current Sense UVLO SHUTDOWN ILIM _ GND R1 + FB EN R2 UVLO Thermal Shutdown External to the Device 250 kΩ Bandgap Reference VIN Vref Bypass FUNCTIONAL BLOCK DIAGRAM – FIXED VERSION VIN VOUT UVLO Current Sense GND SHUTDOWN ILIM _ R1 + EN UVLO R2 Thermal Shutdown Bandgap Reference VIN 250 kΩ Vref Bypass TERMINAL FUNCTIONS TERMINAL NAME 6 I/O DESCRIPTION ADJ FIXED BYPASS 4 4 EN 3 3 I Enable input that enables or shuts down the device. When EN goes to a logic high, the device is enabled. When the device goes to a logic low, the device is in shutdown mode. FB 5 N/A I Feedback input voltage for the adjustable device GND 2 2 IN 1 1 I Input to the device OUT 6 5 O Regulated output of the device An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise. Regulator ground Submit Documentation Feedback TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS TPS79328 TPS79328 TPS79328 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs JUNCTION TEMPERATURE GROUND CURRENT vs JUNCTION TEMPERATURE 2.805 2.805 VI = 3.8 V Co = 10 µF TJ = 25° C 250 VI = 3.8 V Co = 10 µF 2.802 2.801 2.8 2.799 2.798 2.797 IO = 1 mA 2.795 2.79 IO = 200 mA 2.785 2.775 0 50 100 150 200 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 2. Figure 3. TPS79328 TPS79328 TPS79328 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 0.3 Hz 1.6 µ V/ 1.4 0.25 µ V/ VI = 3.8 V Co = 2.2 µF C(byp) = 0.1 µF 0.2 0.15 IO = 1 mA 0.1 IO = 200 mA 0.05 0 100 1k 10 k f − Frequency − Hz 100 k VI = 3.8 V Co = 10 µF C(byp) = 0.1 µF 0.25 0.2 IO = 1 mA 0.15 0.1 IO = 200 mA 0.05 0 100 1k 10 k 100 k C(byp) = 0.001 µF 1 C(byp) = 0.0047 µF 0.8 C(byp) = 0.01 µF 0.6 C(byp) = 0.1 µF 0.4 0.2 0 100 1k TPS79328 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 2.5 Z o − Output Impedance − Ω VO = 2.8 V IO = 200 mA Co = 10 µF 40 30 20 10 0.1 2 VI = 3.8 V Co = 10 µF TJ = 25° C 180 160 1.5 IO = 1 mA 1 IO = 100 mA 0.5 0 10 VI = 2.7 V Co = 10 µF 140 120 IO = 200 mA 100 80 60 40 IO = 10 mA 20 100 100 k Figure 6. OUTPUT IMPEDANCE vs FREQUENCY 60 10 k f − Frequency − Hz Figure 5. ROOT MEAN SQUARED OUTPUT NOISE vs BYPASS CAPACITANCE BW = 100 Hz to 100 0 kHz 0.001 0.01 C(byp) − Bypass Capacitance − µF VI = 3.8 V IO = 200 mA Co= 10 µF 1.2 f − Frequency − Hz Figure 4. 50 Output Spectral Noise Density − Hz 0.3 Output Spectral Noise Density − Hz µ V/ 100 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 Figure 1. Output Spectral Noise Density − IO = 200 mA 150 VI = 3.8 V Co = 10 µF IO − Output Current − mA RMS − Root Mean Squared Output Noise − µ V (RMS) IO = 1 mA 200 50 2.78 2.796 2.795 Ground Current − µ A 2.8 V DO − Dropout Voltage − mV V O − Output Voltage − V 2.803 V O − Output Voltage − V 2.804 1k 10 k 100 k f − Frequency − Hz 1M 10 M 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 7. Figure 8. Submit Documentation Feedback Figure 9. 7 TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) TPS79328 TPS79328 TPS79328 RIPPLE REJECTION vs FREQUENCY RIPPLE REJECTION vs FREQUENCY RIPPLE REJECTION vs FREQUENCY 100 90 90 IO = 200 mA Ripple Rejection − dB Ripple Rejection − dB 80 70 60 50 40 IO = 10 mA 30 20 VI = 3.8 V Co = 10 µF C(byp) = 0.01 µF 10 0 10 100 1k 100 VI = 3.8 V Co = 2.2 µF C(byp) = 0.01 µF 80 IO = 200 mA 70 60 50 80 IO = 10 mA 40 30 100 k 1M 60 50 IO = 10 mA 40 30 20 20 10 10 0 10 10 M IO = 200 mA 70 0 10 k VI = 3.8 V Co = 2.2 µF C(byp) = 0.1 µF 90 Ripple Rejection − dB 100 100 1k 10 k 100 k 1M 10 M 10 100 f − Frequency − Hz f − Frequency − Hz Figure 10. 1k 10 k 100 k 1M 10 M f − Frequency − Hz Figure 11. Figure 12. VI = 3.8 V VO = 2.8 V IO = 200 mA Co = 2.2 µF TJ = 25°C 0 V − Output Voltage − V O C(byp) = 0.001 µF 3 2 C(byp) = 0.0047 µF 1 C(byp) = 0.01 µF 0 0 20 40 3.8 IO = 200 mA Co = 2.2 µF C(byp) = 0.01 µF 20 dv 0.4 V + µs dt 0 -20 0 10 20 30 40 50 60 70 80 90 100 I O − Output Current − mA 2 V I − Input Voltage − mV 4 4.8 ∆ V − Change In O Output Voltage − mV TPS79328 LOAD TRANSIENT RESPONSE V O − Output Voltage − mV TPS79328 LINE TRANSIENT RESPONSE Enable Voltage − V TPS79328 OUTPUT VOLTAGE, ENABLE VOLTAGE vs TIME (START-UP) VI = 3.8 V Co = 10 µF 20 0 −20 −40 di 0.02A + µs dt 300 200 1mA 100 0 0 50 100 150 200 250 300 350 400 450 500 t − Time − µs t − Time − µs 60 80 100 120 140 160 180 200 t − Time − µs Figure 13. Figure 14. Figure 15. TPS79301 DC DROPOUT VOLTAGE vs OUTPUT CURRENT POWER UP / POWER DOWN VO = 3 V RL = 15 Ω DROPOUT VOLTAGE vs INPUT VOLTAGE 250 VO 200 TJ = 125°C 150 TJ = 25°C 100 TJ = −55°C 50 1s/div V DO − Dropout Voltage − mV VI DC Dropuoy Voltage − mV 500 mV/div 200 TJ = 125°C 150 TJ = 25°C 100 50 TJ = −40°C 0 0 20 40 60 80 100 120 140 160 180 200 IO − Output Current − mA IO = 200 mA 0 2.5 3 3.5 4 VI − Input Voltage − V Figure 16. 8 Figure 17. Submit Documentation Feedback Figure 18. 4.5 5 TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) TJ = 125°C TJ = 25°C TJ = −40°C 3 2.8 2 1.5 1.75 2 2.25 2.5 2.75 3 VO − Output Voltage − V 3.25 3.5 100 Co = 2.2 µF VI = 5.5 V, VO ≥ 1.5 V TJ = −40°C to 125°C Ω Ω IO = 200 mA 10 Region of Instability 1 0.1 Region of Stability 0.01 0 0.02 0.04 0.06 0.08 IO − Output Current − A Figure 19. TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT ESR − Equivalent Series Resistance − 4 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT ESR − Equivalent Series Resistance − V I − Minimum Required Input Voltage − V MINIMUM REQUIRED INPUT VOLTAGE vs OUTPUT VOLTAGE Figure 20. Submit Documentation Feedback 0.2 100 Co = 10 µF VI = 5.5 V TJ = −40°C to 125°C 10 Region of Instability 1 0.1 Region of Stability 0.01 0 0.02 0.04 0.06 0.08 0.2 IO − Output Current − A Figure 21. 9 TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 APPLICATION INFORMATION The TPS793xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (170 µA typically), and enable-input to reduce supply currents to less than 1 µA when the regulator is turned off. A typical application circuit is shown in Figure 22. TPS793xx 1 VI IN BYPASS OUT 0.1 µF 4 5 VO 3 0.01 µF EN + GND 2.2 µF 2 Figure 22. Typical Application Circuit External Capacitor Requirements A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS793xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source. Like all LDOs, the TPS793xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance is 2.2-µF. Any 2.2-µF or larger ceramic capacitor is suitable, provided the capacitance does not vary significantly over temperature. The internal voltage reference is a key source of noise in an LDO regulator. The TPS793xx has a BYPASS pin that is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current flow out of the BYPASS pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor, thus, creating an output error. Therefore, the bypass capacitor must have minimal leakage current. For example, the TPS79328 exhibits only 32 µVRMS of output voltage noise using a 0.1-µF ceramic bypass capacitor and a 2.2-µF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the BYPASS pin that is created by the internal 250-kΩ resistor and external capacitor. Board Layout Recommendation to Improve PSRR and Noise Performance To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. 10 Submit Documentation Feedback TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 APPLICATION INFORMATION (continued) Power Dissipation and Junction Temperature Specified regulator operation is ensured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum power dissipation limit is determined using the following equation: T max * T A P + J D(max) R θJA (1) Where: TJmax = Maximum allowable junction temperature RθJA = Thermal resistance, junction to ambient, for the package, see the dissipation rating table TA = Ambient temperature The regulator dissipation is calculated using: P D ǒ + V *V I O Ǔ I O (2) Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit. Programming the TPS79301 Adjustable LDO Regulator The output voltage of the TPS79301 adjustable regulator is programmed using an external resistor divider as shown in Figure 23. The output voltage is calculated using: V O +V ref ǒ1 ) R1 Ǔ R2 (3) Where: Vref = 1.2246 V typical (the internal reference voltage) Submit Documentation Feedback 11 TPS79301-EP,, TPS79318-EP,, TPS79325-EP,, TPS79328-EP TPS793285-EP, TPS79330-EP, TPS79333-EP, TPS793475-EP www.ti.com SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006 APPLICATION INFORMATION (continued) Programming the TPS79301 Adjustable LDO Regulator (continued) Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower-value resistors can be used for improved noise performance, but the solution consumes more power. Higher resistor values should be avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially increases/decreases the feedback voltage and, thus, erroneously decreases/increases VO. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA, C1 = 15 pF for stability, and then calculate R1 using: R1 + ǒ Ǔ V V O *1 ref R2 (4) In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. For voltages 1.8 V, the approximate value of this capacitor can be calculated as: (3 x 10 –7) x (R1 ) R2) C1 + (R1 x R2) (5) The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is not used (such as in a unity-gain configuration) or if an output voltage