TPS7A13
SBVS399A – DECEMBER 2021 – REVISED MAY 2022
TPS7A13 300-mA, Low VIN, Low VOUT, Ultra-Low Dropout Regulator
1 Features
3 Description
•
•
The TPS7A13 is a small, low-dropout regulator (LDO)
with excellent transient response. This device can
source 300 mA with outstanding ac performance (load
and line transient responses). The input voltage range
is from 0.7 V to 2.2 V, and the output range is from
0.5 V to 2.05 V with a very high accuracy of 1% over
load, line, and temperature.
•
•
•
•
•
•
•
Ultra-low input voltage range: 0.7 V to 2.2 V
High efficiency:
– Dropout at 300 mA: 65 mV (max)
– Specified for VIN = VOUT + 100 mV
Excellent load transient response:
– 20 mV for ILOAD 1 mA to 250 mA in 10 μs
Accuracy over load, line, and temperature: 1%
High PSRR: 80 dB at 1 kHz
Available in fixed-output voltages:
– 0.5 V to 2.05 V (in 25-mV steps)
VBIAS range:
– 2.2 V to 5.5 V
Package:
– 6-pin, 1-mm × 0.71-mm DSBGA
Active output discharge
The primary power path is through the IN pin and can
be connected to a power supply as low as 50 mV
above the output voltage. All electrical characteristics
(including excellent output voltage tolerance, transient
response, and PSRR) are specified for input voltages
100 mV greater than the output voltage, thereby
yielding high practical efficiency. This regulator
supports very low input voltages with the use of a
higher, externally supplied V BIAS rail that is used to
power the internal circuitry of the LDO. For example,
the supply voltage to the IN pin can be the output
of a high-efficiency, DC/DC step-down regulator and
the BIAS pin supply voltage can be a rechargeable
battery.
2 Applications
•
•
•
•
•
•
Camera modules
Wireless headphones and earbuds
Smart watches, fitness trackers
Smart phones and tablets
Portable medical devices
Solid state drives (SSDs)
The TPS7A13 is equipped with an active pulldown
circuit to quickly discharge the output when disabled,
and provides a known start-up state.
The TPS7A13 is available in an ultra-small 0.71-mm
× 1.0-mm, 6-bump DSBGA package that makes the
device suitable for space-constrained applications.
Device Information(1)
PART NUMBER
TPS7A13
(1)
PACKAGE
DSBGA (6)
BODY SIZE (NOM)
0.71 mm × 1.0 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
CBIAS
OUT
Standalone
DC/DC Converter
Or PMU
BIAS
IN
IN
COUT
TPS7A13
EN
GND
VOUT
OUT
CIN
SENSE
GND
Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A13
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................ 7
7 Detailed Description......................................................12
7.1 Overview................................................................... 12
7.2 Functional Block Diagram......................................... 12
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................15
8 Application and Implementation.................................. 16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 20
9 Power Supply Recommendations................................21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Device Support........................................................23
11.2 Documentation Support.......................................... 23
11.3 Receiving Notification of Documentation Updates.. 23
11.4 Support Resources................................................. 23
11.5 Trademarks............................................................. 23
11.6 Electrostatic Discharge Caution.............................. 23
11.7 Glossary.................................................................. 23
12 Mechanical, Packaging, and Orderable
Information.................................................................... 24
12.1 Mechanical Data..................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2021) to Revision A (May 2022)
Page
• Changed Functional Block Diagram image...................................................................................................... 12
2
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5 Pin Configuration and Functions
1
2
A
OUT
IN
B
SENSE
EN
C
GND
BIAS
Not to scale
Figure 5-1. YCK Package, 6-Pin WCSP, 0.35-mm Pitch (Top View)
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
A1
OUT
Output
A2
IN
Input
Input pin. A 0.75-µF or greater capacitance is required from IN to ground for stability. For good
transient response, use a 2.2-µF or larger ceramic capacitor from IN to ground. Place the input
capacitor as close to input of the device as possible.
B1
SENSE
Input
SENSE input. This pin is a feedback input to the regulator for SENSE connections. Connecting
SENSE to the load helps eliminate voltage errors resulting from trace resistance between OUT
and the load.
B2
EN
Input
Enable pin. Driving this pin to logic high enables the LDO. Driving this pin to logic low disables the
LDO. If enable functionality is not required, this pin must be connected to IN or BIAS.
C1
GND
—
C2
BIAS
Input
Regulated output pin. A 1-µF or greater capacitance is required from OUT to ground for stability.
For best transient response, use a 2.2-µF or larger ceramic capacitor from OUT to ground. Place
the output capacitor as close to OUT as possible.
Ground pin. This pin must be connected to ground.
BIAS pin. This pin enables the use of low-input voltage, low-output voltage (LILO) conditions. For
best performance, use a 0.1-µF or larger ceramic capacitor from BIAS to ground. Place the bias
capacitor as close to BIAS as possible.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted.(1)
Voltage
Current
(2)
MAX
–0.3
2.4
Enable, VEN
–0.3
6.0
Bias, VBIAS
–0.3
6.0
Sense, VSENSE
–0.3
VIN + 0.3 (2)
Output, VOUT
–0.3
VIN + 0.3 (2)
Maximum output
Temperature
(1)
MIN
Input, VIN
UNIT
V
Internally limited
A
Operating junction, TJ
–40
150
°C
Storage, Tstg
–65
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
The absolute maximum rating is 2.4 V or (VIN + 0.3 V), whichever is less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted). (1)
MIN
MAX
UNIT
VIN
Input voltage
0.7
2.2
V
VBIAS
Bias voltage
Greater of 2.2 or VOUT + 1.4
5.5
V
VOUT
Output voltage
0.5
2.05
V
IOUT
Peak output current
0
300
mA
CIN
Input capacitance(2)
0.75
capacitance(3)
CBIAS
Bias
COUT
Output capacitance
ESR
Output capacitor series resistance
TJ
Operating junction temperature
(1)
(2)
(3)
4
NOM
µF
0.1
1
–40
µF
47
µF
100
mΩ
125
℃
All voltages are with respect to GND.
An input capacitor is required to counteract the effect of source resistance and inductance, which may in some cases cause symptoms
of system level instability such as ringing or oscillation, especially in the presence of load transients. A larger input capacitor may be
necessary depending on the source impedance and system requirements.
A BIAS input capacitor is not required for LDO stability. However, a capacitor with a derated value of at least 0.1 µF is recommended to
maintain transient, PSRR, and noise performance.
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6.4 Thermal Information
TPS7A13
THERMAL METRIC(1)
YCK (DSBGA)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
148.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.3
°C/W
RθJB
Junction-to-board thermal resistance
42.1
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
42.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
specified at TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.1 V, VBIAS = greater of 2.2 V or VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN =
1.0 V, CIN = 1 μF, COUT = 1 μF, and CBIAS = 0.1 μF, unless otherwise noted; all typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Accuracy over temperature
VOUT(NOM) + 0.1 V ≤
TJ = –40°C to +85°C
VIN ≤ 2.2 V,
greater of 2.2 V or
VOUT(NOM) + 1.4 V ≤
TJ = –40°C to +125°C
VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 300 mA
ΔVOUT / ΔVIN
VIN line regulation
VOUT(NOM) + 0.1 V ≤ VIN ≤ 2.2 V
–2.5
0.013
2.5
mV
ΔVOUT / ΔVBIAS
VBIAS line regulation
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V
–2.5
0.02
2.5
mV
ΔVOUT / ΔIOUT
Load regulation
1 mA ≤ IOUT ≤ 300 mA
IQ(BIAS)
Bias pin current
IOUT = 0 mA
IOUT = 300 mA
–1
1
–1.4
1
UNIT
0.49
%/A
TJ = –40°C to +85°C
30
TJ = –40°C to +125°C
40
TJ = –40°C to +125°C
%
5
TJ = –40°C to +85°C
5.7
TJ = –40°C to +125°C
17
µA
mA
IQ(IN)
Input pin current(1)
IOUT = 0 mA
IGND
Ground pin current(1)
IOUT = 300 mA
320
500
µA
ISHDN(BIAS)
VBIAS shutdown current
VIN = 2.2 V, VBIAS = 5.5 V, VEN ≤ 0.2 V
0.264
12
µA
VIN shutdown current
VIN = 1.8 V, VBIAS = 5.5 V, VEN ≤ 0.2 V,
TJ = –40°C to +85°C
0.5
5.7
VIN = 1.8 V, VBIAS = 5.5 V, VEN ≤ 0.2 V
0.5
22
510
750
ISHDN(IN)
ICL
Output current limit
VOUT = 0.95 × VOUT(NOM)
ISC
Short-circuit current limit
VOUT = 0 V
voltage(2)
VDO(IN)
VIN dropout
VDO(BIAS)
VBIAS dropout voltage(2)
VIN = 0.95 × VOUT(nom), IOUT = 300 mA,
VOUT ≥ 0.6 V
VBIAS = greater of 1.7 V or VOUT(nom) + 0.6 V,
VSENSE = 0.95 × VOUT(nom), IOUT = 300 mA
320
177
30
µA
µA
mA
mA
65
mV
0.9
V
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6.5 Electrical Characteristics (continued)
specified at TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.1 V, VBIAS = greater of 2.2 V or VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN =
1.0 V, CIN = 1 μF, COUT = 1 μF, and CBIAS = 0.1 μF, unless otherwise noted; all typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
f = 100 Hz
f = 1 kHz
f = 10 kHz
VIN power-supply rejection
ratio
VIN PSRR
f = 100 kHz
f = 1 MHz
f = 1 MHz,
VIN = VOUT + 150 mV
MIN
TYP
IOUT = 3 mA
90
IOUT = 300 mA
73
IOUT = 3 mA
84
IOUT = 300 mA
75
IOUT = 3 mA
70
IOUT = 300 mA
60
IOUT = 3 mA
53
IOUT = 300 mA
43
IOUT = 3 mA
65
IOUT = 300 mA
27
IOUT = 3 mA
65
IOUT = 300 mA
42
f = 1 kHz,
VBIAS power-supply rejection
ratio
VBIAS PSRR
Vn
Output voltage noise
VUVLO(BIAS)
Bias supply UVLO
VUVLO_HYST(BIAS)
Bias supply hysteresis
f = 100 kHz
UNIT
dB
65
IOUT = 300 mA
47
f = 1 MHz
26
Bandwidth = 10 Hz to 100 kHz,
VOUT = 0.8 V, IOUT = 300 mA
7.2
dB
µVRMS
VBIAS rising
1.15
1.42
1.7
VBIAS falling
1.0
1.3
1.64
VIN rising
584
603
623
VIN falling
530
552
566
VBIAS hysteresis
VUVLO(IN)
Input supply UVLO
VUVLO_HYST(IN)
Input supply hysteresis
tSTR
Start-up time(3)
VHI(EN)
EN pin logic high voltage
VLO(EN)
EN pin logic low voltage
IEN
EN pin current
EN = 5.5 V
RPULLDOWN
Pulldown resistor
VIN = 0.9 V, VOUT(nom) = 0.8 V, VBIAS = 1 V,
VEN = 0 V, P version only
TSD
Thermal shutdown
temperature
(1)
(2)
(3)
MAX
95
VIN hysteresis
V
mV
mV
55
mV
200
µs
0.6
V
–20
10
0.25
V
30
nA
36
Shutdown, temperature rising
165
Reset, temperature falling
140
Ω
°C
This current flowing from VIN to GND.
Dropout is not measured for VOUT < 0.6 V. VBIAS must be 2.2 V or greater for specified dropout value.
Startup time = time from EN assertion to 0.95 × VOUT(NOM).
6.6 Switching Characteristics
specified at TJ = –40°C to +85°C, VIN = VOUT(NOM) + 0.1 V, VBIAS = greater of 2.2 V or VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN =
1.0 V, CIN = 1 μF, COUT = 1 μF, and CBIAS = 0.1 μF (unless otherwise noted); all typical values are at TJ = 25°C; all transient
numbers are over multiple load and line pulses. 100µs on (high load) / 100µs off (low load)
PARAMETER
ΔVOUT
ΔVOUT
(1)
6
Line transient(1)
Load transient(1)
TEST CONDITIONS
MIN
VIN = (VOUT(NOM) + 0.1 V) Transition time, tR = 1 V / µs
to 2.1 V
UNIT
%VOUT
–1
IOUT = 1 mA to 250 mA
–5
Transition time, tR = 10 µs, tF = 10 µs, tOFF =
200 µs, tON = 1 ms, CIN = 2 μF, COUT = 2 μF
MAX
1
VIN = 2.1 V to (VOUT(NOM) Transition time, tF = 1 V / µs
+ 0.1 V)
IOUT = 250 mA to 1 mA
TYP
5
%VOUT
This specification is verified by design.
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6.7 Typical Characteristics
at operating temperature TJ = 25°C, VOUT(NOM) = 0.9 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 1 µF, COUT = 1 µF, and CBIAS = 0.1 µF (unless otherwise noted)
Figure 6-1. Output Voltage Accuracy vs VIN
Figure 6-2. Output Voltage Accuracy vs VBIAS
Figure 6-3. Output Voltage Accuracy vs IOUT
Figure 6-4. VIN Dropout Voltage vs IOUT
Figure 6-5. VBIAS Dropout Voltage vs IOUT
Figure 6-6. VBIAS Input Current vs VBIAS
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6.7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VOUT(NOM) = 0.9 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 1 µF, COUT = 1 µF, and CBIAS = 0.1 µF (unless otherwise noted)
IOUT = 300 mA
IOUT = 0 mA
Figure 6-7. VBIAS Input Current vs VBIAS
Figure 6-8. VIN Shutdown IQ vs VIN
IOUT = 0 mA
8
Figure 6-9. VBIAS Shutdown IQ vs VBIAS
Figure 6-10. Foldback Current Limit vs IOUT
Figure 6-11. Enable Threshold vs Temperature
Figure 6-12. VIN UVLO vs Temperature
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6.7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VOUT(NOM) = 0.9 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 1 µF, COUT = 1 µF, and CBIAS = 0.1 µF (unless otherwise noted)
tr = 1 μs
Figure 6-13. VBIAS UVLO vs Temperature
Figure 6-14. Start-Up With VBIAS Before VIN
tr = 1 μs
tr = 1 μs
Figure 6-15. Start-Up With VIN Before VBIAS and VEN
Figure 6-16. Start-Up With VIN and VBIAS Before VEN
tr = tf = 1 μs
tr = 1 μs
Figure 6-18. Line Transient From 1 V to 2.2 V
Figure 6-17. Start-Up With VIN and VEN Before VBIAS
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6.7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VOUT(NOM) = 0.9 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 1 µF, COUT = 1 µF, and CBIAS = 0.1 µF (unless otherwise noted)
tr = tf = 1 μs
tr = tf = 1 μs, IOUT = 300 mA
Figure 6-19. Line Transient From 1 V to 2.2 V
Figure 6-20. Load Transient From 100 μA to 320 mA
tr = tf = 20 μs
CBIAS = 0 μF, IOUT = 300 mA
Figure 6-21. Load Transient From 100 μA to 320 mA
Figure 6-22. VIN PSRR vs Frequency and VIN – VOUT
CBIAS = 0 μF, IOUT = 300 mA
CBIAS = 0 μF
Figure 6-23. VIN PSRR vs Frequency and COUT
10
Figure 6-24. VIN PSRR vs Frequency and IOUT
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6.7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VOUT(NOM) = 0.9 V, VIN = VOUT(NOM) + 0.1 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN
= VIN, CIN = 1 µF, COUT = 1 µF, and CBIAS = 0.1 µF (unless otherwise noted)
CBIAS = 0 μF
Figure 6-25. VBIAS PSRR vs Frequency and VBIAS – VOUT
Figure 6-26. Output Noise vs Frequency and IOUT
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7 Detailed Description
7.1 Overview
The TPS7A13 is a low-input, ultra-low dropout, low-quiescent-current linear regulator that is optimized
for excellent transient performance. These characteristics make the device ideal for most battery-powered
applications. The low operating VIN – V OUT combined with the BIAS pin dramatically improve the efficiency of
low-voltage output applications by powering the voltage reference and control circuitry and allowing the use of
a pre-regulated, low-voltage input supply (IN) for the main power path. This low-dropout regulator (LDO) offers
foldback current limit, shutdown, thermal protection, and active discharge.
7.2 Functional Block Diagram
Current
Limit
IN
OUT
+
Overshoot
Pull-Down
–
BIAS
Bandgap
SENSE
+
–
Active Discharge
P-Version Only
UVLO
Internal
Controller
EN
GND
Thermal
Shutdown
12
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7.3 Feature Description
7.3.1 Excellent Transient Response
The TPS7A13 responds quickly to a change on the input supply (line transient) or the output current (load
transient) given the device high input impedance and low output impedance across frequency. This same
capability also means that this LDO has a high power-supply rejection ratio (PSRR) and, when coupled with
a low internal noise-floor (en), the LDO approximates an ideal power supply with outstanding line and load
transient performance.
The choice of external component values optimizes the transient response; see the Input, Output, and Bias
Capacitor Requirements section for proper capacitor selection.
7.3.2 Global Undervoltage Lockout (UVLO)
The TPS7A13 uses two undervoltage lockout circuits: one on the BIAS pin and one on the IN pin to prevent the
device from turning on before both VBIAS and VIN rise above their lockout voltages. The two UVLO signals are
connected internally through an AND gate, as shown in Figure 7-1, that turns off the device when the voltage on
either input is below their respective UVLO thresholds.
UVLO(IN)
Global UVLO
UVLO(BIAS)
Figure 7-1. Global UVLO Circuit
7.3.3 Enable Input
The enable input (EN) is active high. Applying a voltage greater than VEN(HI) to EN enables the regulator output
voltage, and applying a voltage less than VEN(LOW) to EN disables the regulator output. If independent control of
the output voltage is not needed, connect EN to either IN or BIAS.
7.3.4 Internal Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions from a
brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with
the output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL).
When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 60% × VOUT(nom).
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
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Figure 7-2 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
IOUT
0V
0 mA
ISC
IRATED
ICL
Figure 7-2. Foldback Current Limit
7.3.5 Active Discharge
The active discharge function uses an internal MOSFET that connects a resistor (RPULLDOWN) to ground when
the LDO is disabled in order to actively discharge the output voltage. The active discharge circuit is activated by
driving EN to logic low to disable the device, when the voltage at IN or BIAS is below the UVLO threshold, or
when the regulator is in thermal shutdown.
The discharge time after disabling the device depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the pulldown resistor.
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow
can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current.
7.3.6 Thermal Shutdown
The internal thermal shutdown protection circuit disables the output when the thermal junction temperature (TJ)
of the pass transistor rises to the thermal shutdown temperature threshold, TSD(shutdown) (typical). The thermal
shutdown circuit hysteresis ensures that the LDO resets (turns on) when the temperature falls to TSD(reset)
(typical).
The thermal time constant of the semiconductor die is fairly short; thus, the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
14
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7.4 Device Functional Modes
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
VBIAS
VEN
IOUT
TJ
Normal mode
VIN ≥ VOUT (nom) + VDO
and VIN ≥ VIN(min)
VBIAS ≥ VOUT + VDO(BIAS)
VEN ≥ VHI(EN)
IOUT < ICL
TJ < TSD for
shutdown
Dropout mode
VIN(min) < VIN <
VOUT (nom) + VDO(IN)
VBIAS < VOUT + VDO(BIAS)
VEN > VHI(EN)
IOUT < ICL
TJ < TSD for
shutdown
VIN < VUVLO(IN)
VBIAS < VBIAS(UVLO)
VEN < VLO(EN)
—
TJ ≥ TSD for
shutdown
Disabled mode
(any true condition
disables the device)
7.4.1 Normal Mode
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The bias voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature ( TJ < TSD(shutdown))
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.2 Dropout Mode
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. Similarly, if the bias voltage is
lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for
normal operation, the device operates in dropout mode as well. In this mode, the output voltage tracks the input
voltage. During this mode, the transient performance of the device becomes significantly degraded because the
pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result
in large output voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
or VBIAS < VOUT(NOM) + VDO directly after being in normal regulation state, but not during start up), the pass
transistor is driven into ohmic or triode region. When the input voltage returns to a value greater than or equal
to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a
short time when the device pulls the pass transistor back into the linear region.
7.4.3 Disable Mode
The output of the device can be shut down by forcing the voltage of the enable pin to less than the maximum EN
pin low-level voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned off,
internal circuits are shut down, and the output voltage is actively discharged to ground by an internal discharge
circuit from the output to ground.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and how to best implement them to achieve a reliable design.
8.1.1 Recommended Capacitor Types
The regulator is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors
at the input, output, and bias pins. Multilayer ceramic capacitors are the industry standard for use with
LDOs, but must be used with good judgment. Ceramic capacitors that use X7R-, X5R-, and COG-rated
dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated
capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor
type selected, ceramic capacitance varies with operating voltage and temperature. Generally, assume that
effective capacitance decreases by as much as 50%. The input, output, and bias capacitors recommended in
the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the
nominal value.
8.1.2 Input, Output, and Bias Capacitor Requirements
A minimum input ceramic capacitor is required for stability. A minimum output ceramic capacitor is also required
for stability; see the Recommended Operating Conditions table for the minimum capacitor values.
The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR.
A higher-value input capacitor may be necessary if large, fast rise-time load or line transients are anticipated,
or if the device is located several inches from the input power source. Dynamic performance of the device is
improved with the use of an output capacitor larger than the minimum value specified in the Recommended
Operating Conditions table.
Although a bias capacitor is not required, good design practice is to connect a 0.1-μF ceramic capacitor from
BIAS to GND. This capacitor counteracts reactive bias source effects if the source impedance is not sufficiently
low. If the BIAS source is susceptible to fast voltage drops (for example, a 2-V drop in less than 1 µs) when
the LDO load current is near the maximum value, the BIAS voltage drop may cause the output voltage to fall
briefly. In such cases, use a BIAS capacitor large enough to slow the voltage ramp rate to less than 0.5 V/µs. For
smaller or slower BIAS transients, any output voltage dips must be less than 5% of the nominal voltage.
Place the input, output, and bias capacitors as close as possible to the device to minimize the effects of trace
parasitic impedance.
8.1.3 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
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VDO
IRATED
(1)
Using a bias rail enables the TPS7A13 to achieve a lower dropout voltage between IN and OUT. However, a
minimum bias voltage above the nominal programmed output voltage must be maintained. Figure 6-13 specifies
the minimum VBIAS headroom required to maintain output regulation.
8.1.4 Behavior During Transition From Dropout Into Regulation
Some applications may have transients that place this device into dropout, especially when this device can
be powered from a battery with relatively high ESR. The load transient saturates the output stage of the error
amplifier when the pass element is driven fully on, making the pass element function like a resistor from VIN
to VOUT. The error amplifier response time to this load transient is limited because the error amplifier must
first recover from saturation and then places the pass element back into active mode. During this time, VOUT
overshoots because the pass element is functioning as a resistor from VIN to VOUT.
When VIN ramps up slowly for start up, the slow ramp-up voltage may place the device in dropout. As with many
other LDOs, the output can overshoot on recovery from this condition. However, this condition is easily avoided
through the use of the enable signal.
If operating under these conditions, apply a higher dc load or increase the output capacitance to reduce the
overshoot. These solutions provide a path to dissipate the excess charge.
8.1.5 Device Enable Sequencing Requirement
The IN, BIAS, and EN pin voltages can be sequenced in any order without causing damage to the device. Start
up is always monotonic regardless of the sequencing order or the ramp rates of the IN, BIAS, and EN pins. See
the Recommended Operating Conditions table for proper voltage ranges of the IN, BIAS, and EN pins.
8.1.6 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current while
output voltage regulation is maintained. See the Typical Characteristics section for the typical load transient
response. There are two key transitions during a load transient response: the transition from a light to a heavy
load, and the transition from a heavy to a light load. The regions in Figure 8-1 are broken down as described in
this section. Regions A, E, and H are where the output voltage is in steady-state operation.
tAt
tCt
tDt
B
tEt
tGt
tHt
F
Figure 8-1. Load Transient Waveform
During transitions from a light load to a heavy load, the following behavior can be observed:
•
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load, the:
•
•
Initial voltage rise results from the LDO sourcing a large current, and leads to an increase in the output
capacitor charge (region F)
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
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A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.7 Undervoltage Lockout Circuit Operation
The VIN UVLO circuit makes sure that the device remains disabled before the input supply reaches the minimum
operational voltage range. The VIN UVLO circuit also makes sure that the device shuts down when the input
supply collapses. Similarly, the VBIAS UVLO circuit makes sure that the device stays disabled before the bias
supply reaches the minimum operational voltage range. The VBIAS UVLO circuit also makes sure that the device
shuts down when the bias supply collapses.
Figure 8-2 depicts the UVLO circuit response to various input or bias voltage events. The diagram can be
separated into the following parts:
•
•
•
•
•
•
•
Region A: The output remains off while either the input or bias voltage is below the UVLO rising threshold
Region B: Normal operation, regulating device
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device is still enabled.
Region D: Normal operation, regulating device
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO
rising threshold is reached and a normal start up follows.
Region F: Normal operation followed by the input or bias falling to the UVLO falling threshold
Region G: The device is disabled when either the input or bias voltage falls below the UVLO falling threshold
to 0 V. The output falls as a result of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN / VBIAS
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 8-2. Typical VIN or VBIAS UVLO Circuit Operation
8.1.8 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
Equation 2 calculates the maximum allowable power dissipation for the device in a given package:
PD-MAX = [(TJ – TA) / RθJA]
(2)
Equation 3 represents the actual power being dissipated in the device:
PD = [(IGND(IN) + IIN) × VIN + IGND(BIAS) × VBIAS] – (IOUT × VOUT)
(3)
If the load current is much greater than IGND(IN) and IGND(BIAS), Equation 3 can be simplified as:
PD = (VIN – VOUT) × IOUT
18
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Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A13 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device depends on the ambient temperature and the thermal resistance
across the various interfaces between the die junction and ambient air.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 5, maximum power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA). The equation is rearranged in Equation 6 for output current.
TJ = TA + (RθJA × PD)
(5)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
(6)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of
the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB,
and copper-spreading area, and is only used as a relative measure of package thermal performance. For a
well-designed thermal layout, RθJA is actually the sum of the YCK package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.9 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 7 and are given in the Electrical Characteristics table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
(7)
where:
•
•
•
PD is the power dissipated as explained in Equation 3 and the Power Dissipation (PD) section
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.10 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is shown in Figure 8-3 and can
be separated into the following regions:
•
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level; see the Dropout Mode section for more details.
The rated output current limits the maximum recommended output current level. Exceeding this rating causes
the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– Figure 8-3 provides the shape of the slope. The slope is nonlinear because the maximum rated junction
temperature of the LDO is controlled by the power dissipation across the LDO; thus, when VIN – VOUT
increases the output current must decrease.
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
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Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited
by Thermals
Limited by
Maximum VIN
Limited by
Minimum VIN
VIN ± VOUT (V)
Figure 8-3. Continuous Operation Diagram With Description of Regions
8.2 Typical Application
CBIAS
IN
BIAS
OUT
IN
COUT
DC/DC Converter
Or PMU
TPS7A13
EN
GND
VOUT
OUT
CIN
SENSE
GND
Figure 8-4. High Efficiency Supply From a Rechargeable Battery
8.2.1 Design Requirements
Table 8-1 lists the parameters for this design example.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
1.0 V
VBIAS
2.4 V to 5.5 V
VOUT
0.9 V
IOUT
150 mA (typical), 300 mA (peak)
8.2.2 Detailed Design Procedure
This design example is powered by a rechargeable battery that can be a building block in many portable
applications. Noise-sensitive portable electronics require an efficient, small-size solution for their power supply.
Traditional LDOs are known for their low efficiency in contrast to low-input, low-output voltage (LILO) LDOs such
as the TPS7A13. Using a bias rail in the TPS7A13 allows the device to operate at a lower input voltage, thus
reducing the voltage drop across the pass transistor and maximizing device efficiency. The low voltage drop
allows the efficiency of the LDO to approximate that of a DC/DC converter. Equation 8 calculates the efficiency
for this design.
Efficiency = η = POUT / PIN × 100 % = (VOUT × IOUT) / (VIN × IIN + VBIAS × IBIAS) × 100 %
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Equation 8 reduces to Equation 9 because the design example load current is much greater than the quiescent
current of the bias rail.
Efficiency = η = (VOUT × IOUT) / (VIN × IIN) × 100%
(9)
8.2.3 Application Curve
VBIAS = VOUT(NOM) + 1.4 V, VEN = VIN, CIN = 1 µF, COUT = 1 µF, and CBIAS = 0.1 µF
Figure 8-5. VIN Dropout Voltage vs IOUT
9 Power Supply Recommendations
This LDO is designed to operate from an input supply voltage range of 0.6 V to 2.2 V and a bias supply voltage
range of 2.2V to 5.5 V. The input and bias supplies must be well regulated and free of spurious noise. To make
sure that the output voltage is well regulated and dynamic performance is at optimum, the input supply must be
at least VOUT(nom) + VDO and VBIAS = VOUT(nom) + VDO(BIAS).
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10 Layout
10.1 Layout Guidelines
For correct printed circuit board (PCB) layout, follow these guidelines:
•
•
•
Place input, output, and bias capacitors as close to the device as possible
Use copper planes for device connections to optimize thermal performance
Place thermal vias around the device to distribute heat
10.2 Layout Example
Figure 10-1. Recommended Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS7A13. The EVM can be requested at the Texas Instruments web site through the product folders or
purchased directly from the TI eStore
11.1.2 Device Nomenclature
Table 11-1. Device Nomenclature(1) (2)
(1)
(2)
PRODUCT
DESCRIPTION
TPS7A13xx(x)(P)yyyz
xx(x) is the nominal output voltage. Two or more digits are used in the ordering number (for example, 09
= 0.9V; 95 = 0.95V; 125 = 1.25 V).
P indicates active pull down; if there is no P, then the device does not have the active pull-down feature.
yyy is the package designator.
z is the package quantity. R is for reel (12000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 0.5 V to 2.05 V in 25-mV increments are available. Contact TI for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Using New Thermal Metrics application report
• Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package application report
• Texas Instruments, TPS7A13EVM-057 Evaluation Module user guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Mechanical Data
PACKAGE OUTLINE
YCK0006-C02
DSBGA - 0.33 mm max height
SCALE 12.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.33 MAX
C
SEATING PLANE
0.05 C
0.115
0.065
0.35 TYP
SYMM
C
D: Max = 1.02 mm, Min = 0.98 mm
0.7 TYP
SYMM
B
E: Max = 0.73 mm, Min = 0.69 mm
0.35 TYP
A
1
6X
0.015
0.22
0.18
2
0.175 TYP
C A B
4228736/A 05/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YCK0006-C02
DSBGA - 0.33 mm max height
DIE SIZE BALL GRID ARRAY
(0.175) TYP
6X ( 0.2)
2
1
A
(0.35) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.0375 MAX
0.0375 MIN
METAL UNDER
SOLDER MASK
EXPOSED
METAL
( 0.2)
SOLDER MASK
OPENING
( 0.2)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4228736/A 05/2022
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YCK0006-C02
DSBGA - 0.33 mm max height
DIE SIZE BALL GRID ARRAY
(0.175) TYP
(R0.05) TYP
6X ( 0.21)
1
2
A
(0.35) TYP
SYMM
B
C
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 50X
4228736/A 05/2022
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
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13-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS7A1308PYCKR
ACTIVE
DSBGA
YCK
6
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
NO
Samples
TPS7A1309PYCKR
ACTIVE
DSBGA
YCK
6
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
MA
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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