TPS7A2028PYCKR

TPS7A20 SBVS338G – MARCH 2020 – REVISED MAY 2022 TPS7A20 300-mA, Ultra-Low-Noise, Low-IQ, High PSRR LDO 1 Features 3 Description • The TPS7A20 is an ultra-small, low-dropout (LDO) linear regulator that can source 300 mA of output current. The TPS7A20 is designed to provide low noise, high PSRR, and excellent load and line transient performance that can meet the requirements of RF and other sensitive analog circuits. Using innovative design techniques, the TPS7A20 offers an ultra-low noise performance without the addition of a noise bypass capacitor. The TPS7A20 also provides the advantage of low quiescent current, which can be ideal for battery-powered applications. With an input voltage range of 1.6 V to 6.0 V and an output range of 0.8 V to 5.5 V, the TPS7A20 can be used for a wide variety of applications. The device uses a precision reference circuit to provide a maximum accuracy of 1.5% over load, line, and temperature variations. • • • • • • • • • • Low output voltage noise: 7 μVRMS – No noise-bypass capacitor required High PSRR: 95 dB at 1 kHz Very low IQ: 6.5 μA Input voltage range: 1.6 V to 6.0 V Output voltage range: 0.8 V to 5.5 V Output voltage tolerance: ±1.5% (max) Very low dropout: – 140 mV (max) at 300 mA (VOUT = 3.3 V) – 145 mV (max) at 300 mA (VOUT = 3.3 V, DBV) Low inrush current Smart enable pulldown Stable with 1-µF minimum ceramic output capacitor Packages: – 1-mm × 1-mm X2SON – 0.616-mm × 0.616-mm DSBGA – 2.90-mm × 1.60-mm SOT23-5 2 Applications • • • • • • Smartphones and tablets IP network cameras Portable medical equipment Smart meters and field transmitters Motor drives Wearables The TPS7A20 features an internal soft-start to lower the inrush current, thus minimizing the input voltage drop during start up. The device is stable with small ceramic capacitors, allowing for a small overall solution size. The TPS7A20 has a smart enable input circuit with an internally controlled pulldown resistor that keeps the LDO disabled even when the EN pin is left floating and helps eliminate the external components used to pulldown the EN pin. Device Information(1) PART NUMBER TPS7A20 (1) PACKAGE BODY SIZE (NOM) X2SON (4) 1.00 mm × 1.00 mm DSBGA (4) 0.616 mm × 0.616 mm SOT-23 (5) 2.90 mm × 1.60 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................6 6.6 Switching Characteristics............................................7 6.7 Typical Characteristics................................................ 8 7 Detailed Description......................................................23 7.1 Overview................................................................... 23 7.2 Functional Block Diagram......................................... 23 7.3 Feature Description...................................................24 7.4 Device Functional Modes..........................................26 8 Application and Implementation.................................. 27 8.1 Application Information............................................. 27 8.2 Typical Application.................................................... 30 9 Power Supply Recommendations................................31 10 Layout...........................................................................32 10.1 Layout Guidelines................................................... 32 10.2 Layout Examples.................................................... 32 11 Device and Documentation Support..........................33 11.1 Device Support........................................................33 11.2 Receiving Notification of Documentation Updates.. 33 11.3 Support Resources................................................. 33 11.4 Trademarks............................................................. 33 11.5 Electrostatic Discharge Caution.............................. 33 11.6 Glossary.................................................................. 33 12 Mechanical, Packaging, and Orderable Information.................................................................... 33 12.1 Mechanical Data..................................................... 34 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (April 2022) to Revision G (May 2022) Page • Changed UVLO condition from rising to falling for YCJ and YCK packages...................................................... 6 Changes from Revision E (December 2021) to Revision F (April 2022) Page • Changed DSBGA dimensions from 0.603 mm × 0.603 mm to 0.616 mm × 0.616 mm in Features and Description sections............................................................................................................................................1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 5 Pin Configuration and Functions 1 2 A IN OUT B EN GND 1 2 B EN GND A IN OUT Not to scale Not to scale Figure 5-1. YCJ and YCK Packages, 4-Pin DSBGA (Top View) Figure 5-2. YCJ and YCK Packages, 4-Pin DSBGA (Bottom View) Pin Functions: DSBGA PIN NO. A1 A2 NAME IN OUT I/O DESCRIPTION I Input voltage supply. For best transient response and to minimize input impedance, use the nominal value or larger capacitor from IN to ground as listed in the Recommended Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the device as possible. O Regulated output voltage. A low equivalent series resistance (ESR) capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger capacitor listed in the Recommended Operating Conditions table. Place the output capacitor as close to the OUT and GND pins of the device as possible. An internal 150-Ω (typical) pulldown resistor prevents a charge from remaining on VOUT when the regulator is in shutdown mode (VEN< VEN(LOW)). Enable input. A low voltage (< VEN(LOW)) on this input turns the regulator off and discharges the output pin to GND. A high voltage (> VEN(HI)) on this pin enables the regulator output. This pin has an internal 500-kΩ pulldown resistor to hold the regulator off by default. When VEN > VEN(HI), the 500-kΩ pulldown is disconnected to reduce input current. B1 EN I B2 GND — Common ground. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 3 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 OUT 1 4 IN IN 1 GND 2 EN 3 5 OUT 4 N/C 5 Thermal Pad GND 2 3 EN Not to scale Not to scale Figure 5-3. DQN Package, 4-Pin X2SON (Top View) Figure 5-4. DBV Package, 5-Pin SOT-23 (Top View) Pin Functions: X2SON, SOT-23 PIN NAME IN OUT 4 X2SON SOT-23 4 1 1 5 I/O DESCRIPTION I Input voltage supply. For best transient response and to minimize input impedance, use the nominal value or larger capacitor from IN to ground as listed in the Recommended Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the device as possible. O Regulated output voltage. A low equivalent series resistance (ESR) capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger capacitor listed in the Recommended Operating Conditions table. Place the output capacitor as close to the OUT and GND pins of the device as possible. An internal 150-Ω (typical) pulldown resistor prevents a charge from remaining on VOUT when the regulator is in shutdown mode (VEN< VEN(LOW)). Enable input. A low voltage (< VEN(LOW)) on this pin turns the regulator off and discharges the output pin to GND. A high voltage (> VEN(HI)) on this pin enables the regulator output. This pin has an internal 500-kΩ pulldown resistor to hold the regulator off by default. When VEN > VEN(HI), the 500-kΩ pulldown is disconnected to reduce input current. EN 3 3 I GND 2 2 — Common ground. N/C — 4 — No internal electrical connection. Thermal Pad 5 — — Thermal pad for the X2SON package. Connect this pad to GND or leave floating. Do not connect to any potential other than GND. Connect the thermal pad to a large-area ground plane for best thermal performance. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (3) Voltage Current Temperature (1) (2) (3) (4) MIN MAX VIN –0.3 6.5 UNIT VOUT –0.3 6.5 or VIN + 0.3 (2) VEN –0.3 6.5 Maximum output(4) Internally limited Operating junction, TJ –40 150 °C Storage, Tstg –65 150 °C V A Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The maximum value of VOUT is the lesser of 6.5 V or (VIN + 0.3 V). All voltages are with respect to the GND pin. Internal thermal shutdown circuitry protects the device from permanent damage. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT VIN Input supply voltage 1.6 6.0 V VEN Enable input voltage 0 6.0 V VOUT Nominal output voltage range IOUT Output current CIN Input capacitor(2) COUT Output capacitor(3) ESR Output capacitor effective series resistance TJ Operating junction temperature (1) (2) (3) 0.8 5.5 V 0 300 mA 1 1 –40 µF 200 µF 100 mΩ 125 °C All voltages are with respect to GND. An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.47 μF minimum is recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of systemlevel instability such as ringing or oscillation, especially in the presence of load transients. Effective output capacitance of 0.47 μF minimum and 200 μF maximum is required for stability. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 5 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.4 Thermal Information TPS7A20 THERMAL METRIC(1) DBV (SOT-23) DQN (X2SON) YCJ (DSBGA) YCK (DSBGA) 5 PINS 4 PINS 4 PINS 4 PINS UNIT RθJA Junction-to-ambient thermal resistance 187.1 166.1 199.6 201.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 85.5 103.6 2.8 2.8 °C/W RθJB Junction-to-board thermal resistance 54.4 110.6 67.5 69.3 °C/W ψJT Junction-to-top characterization parameter 27.1 3.0 1.4 1.4 °C/W ψJB Junction-to-board characterization parameter 54.1 103.3 67.4 69.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 98.8 N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics at operating temperature range (TJ = –40℃ to +125℃), VIN = VOUT(NOM) + 0.3 V or 1.6V, whichever is greater, VEN = 1.0 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃ PARAMETER ΔVOUT ΔVOUT Line regulation ΔVOUT Load regulation IGND Quiescent ground current TYP MAX 1.5 VIN = (VOUT(NOM) + 0.3 V) to 6.0 V, IOUT = 1 mA to 300 mA, VOUT ≥ 2.8 V (DBV package) -1.5 1.5 VIN = (VOUT(NOM) + 0.5 V) to 6.0 V, IOUT = 1 mA to 300 mA VOUT < 1.85 V (DQN, YCJ, YCK packages) –30 30 VIN = (VOUT(NOM) + 0.3 V) to 6.0 V, IOUT = 1 mA to 300 mA, VOUT < 2.8 V (DBV package) -40 VIN = (VOUT(NOM) + 0.3 V) to 6.0 V, IOUT = 1 mA mV 40 0.03 13 IOUT = 1 mA to 300 mA (DBV package) 19 TJ = 25°C 6.5 VEN = VIN = 6 V, IOUT = 0 mA UNIT % IOUT = 1 mA to 300 mA (DQN, YCJ, YCK packages) %/V mV 8.5 TJ = –40°C to 85°C 10 TJ = –40°C to 125°C 15 µA VEN = VIN = 6 V, IOUT = 300 mA 2000 0.07 0.2 µA 6.5 15 µA Shutdown ground current VEN = 0 V (disabled), VIN = 6.0 V, TJ = 25°C IGND(DO) IGND in dropout VIN ≤ VOUT(NOM) , IOUT = 0 mA, VEN = VIN Dropout voltage MIN –1.5 ISHDN VDO 6 Output voltage tolerance TEST CONDITIONS VIN = (VOUT(NOM) + 0.3 V) to 6.0 V, IOUT = 1 mA to 300 mA, VOUT ≥ 1.85 V (DQN, YCJ, YCK packages) 0.8 V ≤ VOUT < 1.0 V(1) 690 1.0 V ≤ VOUT < 1.2 V(1) 490 1.2 V ≤ VOUT < 1.5 V(1) 355 IOUT = 300 mA, 1.5 V ≤ VOUT < 2.5 V VOUT = 95% x VOUT(NOM), (DQN, YCJ, YCK packages 1.5 V ≤ VOUT < 2.5 V unless otherwise noted) (DBV) 200 mV 205 2.5 V ≤ VOUT < 5.5 V 140 2.5 V ≤ VOUT < 5.5 V (DBV) 145 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.5 Electrical Characteristics (continued) at operating temperature range (TJ = –40℃ to +125℃), VIN = VOUT(NOM) + 0.3 V or 1.6V, whichever is greater, VEN = 1.0 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃ PARAMETER ICL Output current limit ISC Short-circuit current limit TEST CONDITIONS TYP MAX VOUT = 0.9 x VOUT(NOM), VIN = VOUT(NOM) + 0.5 V VOUT < 1.5 V (YCJ, YCK packages) 360 520 770 VOUT = 0.9 x VOUT(NOM), VIN = VOUT(NOM) + 0.5 V VOUT < 1.5 V (DQN package) 360 520 730 VOUT = VOUT(NOM) - 150 mV, VOUT < 1.5 V (DBV VIN = VOUT(NOM) + 0.5 V package) 360 520 730 VOUT = 0.9 x VOUT(NOM), VIN = VOUT(NOM) + 0.3 V VOUT ≥ 1.5 V (YCJ, YCK packages) 360 520 770 VOUT = 0.9 x VOUT(NOM), VIN = VOUT(NOM) + 0.3 V VOUT ≥ 1.5 V (DQN package) 360 520 730 VOUT = 0 V 160 IOUT = 20 mA, VIN = VOUT + 1.0 V PSRR MIN Power-supply rejection ratio IOUT = 300 mA, VIN = VOUT + 1.0 V f = 100 Hz 95 f = 1 kHz 95 f = 10 kHz 75 f = 100 kHz 75 f = 1 MHz 45 f = 100 Hz 65 f = 1 kHz 92 f = 10 kHz 75 f = 100 kHz 60 f = 1 MHz 40 IOUT = 300 mA Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 2.8 V RPULLDOWN Output automatic discharge pulldown resistance VEN < VEN(LOW) (output disabled), VIN = 3.1 V 150 TSD Thermal shutdown TJ rising 165 TJ falling 140 VEN(LOW) Low input threshold VIN = 1.6 V to 6.0 V, VEN falling until the output is disabled VEN(HI) High input threshold VIN = 1.6 V to 6.0 V VEN rising until the output is enabled µVRMS 10 Ω °C 0.3 0.9 1.11 1.35 1.59 1.17 1.35 1.59 VIN falling (YCJ and YCK packages) 1.05 1.3 1.55 VIN falling (DBV and DQN packages) 1.11 1.3 1.55 VUVLO(HYST) UVLO hysteresis IEN EN input leakage current VEN = 6.0 V and VIN = 6.0 V REN(PULL- Smart enable pulldown resistor VEN = 0.25 V V V VIN rising (DBV and DQN packages) UVLO threshold (1) dB VIN rising (YCJ and YCK packages) VUVLO DOWN) IOUT = 1 mA mA mA 7 VN UNIT 50 90 V mV 250 500 nA KΩ Design simulation data only 6.6 Switching Characteristics at operating temperature range (TJ = –40℃ to +125℃), VIN = VOUT(NOM) + 0.3 V or 1.6V, whichever is greater, VEN = 1.0 V, IOUT = 1 mA, CIN= 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃ PARAMETER tSTR Start-up time TEST CONDITIONS From VEN > VEN(HI) to VOUT = 95% of VOUT(NOM), MIN TYP MAX UNIT 750 1150 µs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 7 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 9 TJ TJ 2 -55°C -40°C 1 0°C 25°C 85°C 125°C 150°C Change in Output Voltage (mV) Change in Output Voltage (mV) 3 0 -1 -2 -3 -4 -5 -6 3.1 3.4 3.7 4 4.3 4.6 4.9 Input Voltage (V) 5.2 5.5 5.8 -55°C -40°C 6 85°C 125°C 0 -3 -6 -9 -12 5.65 5.7 5.75 5.8 5.85 Input Voltage (V) 5.95 6 Figure 6-2. Line Regulation vs VIN Figure 6-1. Line Regulation vs VIN VOUT = 5.5 V, VEN = 1 V, DBV package VEN = 1 V, DBV package Figure 6-4. Line Regulation vs VIN Figure 6-3. Line Regulation vs VIN 16 15 TJ -55°C -40°C 10 0°C 25°C TJ 85°C 125°C 150°C 5 0 -5 -10 -15 -20 -25 0 25 50 75 100 125 150 175 200 225 250 275 300 Output Current (mA) VIN = 3.1 V, VEN = 1 V, DQN, YCJ, and YCK packages Change in Output Voltage (mV) Change in Output Voltage (mV) 5.9 VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages VEN = 1 V, DQN, YCJ, and YCK packages -55°C -40°C 12 0°C 25°C 85°C 125°C 150°C 8 4 0 -4 -8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Output Current (mA) 1.6 1.8 2 VIN = 3.1 V, VEN = 1 V, DQN, YCJ, and YCK packages Figure 6-5. Load Regulation vs IOUT 8 150°C 3 -15 5.6 6 0°C 25°C Figure 6-6. Load Regulation vs IOUT Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) VIN = 2.8 V, VEN = 1 V, DBV package VIN = 2.8 V, VEN = 1 V, DBV package Figure 6-8. Load Regulation vs IOUT Figure 6-7. Load Regulation vs IOUT 15 15 TJ -55°C -40°C 5 0°C 25°C TJ 85°C 125°C 150°C 0 -5 -10 -15 -20 -25 -30 -35 0 30 60 90 120 150 180 210 Output Current (mA) 240 270 300 VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages Figure 6-9. Load Regulation vs IOUT Change in Output Voltage (mV) Change in Output Voltage (mV) 10 -55°C -40°C 10 0°C 25°C 85°C 125°C 150°C 5 0 -5 -10 -15 -20 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Output Current (mA) 1.6 1.8 2 VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages Figure 6-10. Load Regulation vs IOUT VOUT = 5.5 V, VEN = 1 V, DBV package Figure 6-11. Load Regulation vs IOUT VOUT = 5.5 V, VEN = 1 V, DBV package Figure 6-12. Load Regulation vs IOUT Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 9 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 0.6 0.6 TJ Output Voltage Accuracy (%) 0°C 25°C 85°C 125°C TJ 0.5 150°C Output Voltage Accuracy (%) -55°C -40°C 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -55°C -40°C 0.4 0°C 25°C 150°C 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -1 0 25 50 0 75 100 125 150 175 200 225 250 275 300 Output Current (mA) D076 0.2 0.4 0.6 0.8 1 1.2 1.4 Output Current (mA) 1.6 1.8 VEN = 1 V, DQN, YCJ, and YCK packages VEN = 1 V, DQN, YCJ, and YCK packages Figure 6-13. Output Voltage Accuracy vs IOUT Figure 6-14. Output Voltage Accuracy vs IOUT VEN = 1 V, DBV package 2 VEN = 1 V, DBV package Figure 6-15. Output Voltage Accuracy vs IOUT Figure 6-16. Output Voltage Accuracy vs IOUT 0.2 0.3 TJ TJ 0°C 25°C 85°C 125°C 150°C Output Voltage Accuracy (%) -55°C -40°C 0.1 Output Voltage Accuracy (%) 85°C 125°C 0 -0.1 -0.2 -0.3 -0.4 -55°C -40°C 0.2 0°C 25°C 85°C 125°C 150°C 0.1 0 -0.1 -0.2 -0.5 -0.3 -0.6 0 30 60 90 120 150 180 210 Output Current (mA) 240 270 300 VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages Figure 6-17. Output Voltage Accuracy vs IOUT 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Output Current (mA) 1.6 1.8 2 VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages Figure 6-18. Output Voltage Accuracy vs IOUT Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) VOUT = 5.5 V, VEN = 1 V, DBV package VOUT = 5.5 V, VEN = 1 V, DBV package Figure 6-19. Output Voltage Accuracy vs IOUT Figure 6-20. Output Voltage Accuracy vs IOUT 0.15 0.15 TJ Output Voltage Accuracy (%) 0°C 25°C 85°C 125°C TJ 0.1 150°C Output Voltage Accuracy (%) -55°C -40°C 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -55°C -40°C 0.05 0°C 25°C 85°C 125°C 150°C 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.25 3.1 3.6 4.1 4.6 5.1 Input Voltage (V) 5.6 VEN = 1 V, IOUT = 1 mA, DQN, YCJ, and YCK packages Figure 6-21. Output Voltage Accuracy vs VIN 6 -0.3 5.6 5.7 5.75 5.8 5.85 Input Voltage (V) 5.9 5.95 6 VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages Figure 6-22. Output Voltage Accuracy vs VIN VEN = 1 V, IOUT = 1 mA, DBV package Figure 6-23. Output Voltage Accuracy vs VIN 5.65 VOUT = 5.5 V, VEN = 1 V, DBV package Figure 6-24. Output Voltage Accuracy vs VIN Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 11 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 130 90 TJ TJ -55°C -40°C 0°C 25°C 85°C 125°C 150°C -55°C -40°C 85 110 Dropout Voltage (mV) Dropout Voltage (mV) 120 100 90 80 0°C 25°C 85°C 125°C 150°C 80 75 70 65 70 60 60 55 50 0 30 60 90 120 150 180 210 Output Current (mA) 240 270 0 300 1 2 4 5 6 7 Output Current (mA) 8 9 10 VEN = 1 V, DQN, YCJ, and YCK packages VEN = 1 V, DQN, YCJ, and YCK packages Figure 6-26. Dropout Voltage vs IOUT Figure 6-25. Dropout Voltage vs IOUT VEN = 1 V, DBV package VEN = 1 V, DBV package Figure 6-27. Dropout Voltage vs IOUT Figure 6-28. Dropout Voltage vs IOUT 160 95 -55°C -40°C 0°C 140 TJ 25°C 85°C 125°C TJ 150°C -55°C -40°C 90 Dropout Voltage (mV) 150 Dropout Voltage (mV) 3 130 120 110 100 90 0°C 25°C 85°C 125°C 150°C 85 80 75 70 65 80 60 70 60 55 0 30 60 90 120 150 180 210 Output Current (mA) 240 270 300 0 D099 VOUT = 1.8 V, VEN = 1 V, DQN, YCJ, and YCK packages 2 3 4 5 6 7 Output Current (mA) 8 9 10 D100 VOUT = 1.8 V, VEN = 1 V, DQN, YCJ, and YCK packages Figure 6-29. Dropout Voltage vs IOUT 12 1 Figure 6-30. Dropout Voltage vs IOUT Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) VOUT = 1.8 V, VEN = 1 V, DBV package VOUT = 1.8 V, VEN = 1 V, DBV package Figure 6-31. Dropout Voltage vs IOUT Figure 6-32. Dropout Voltage vs IOUT 180 14 TJ 0°C 25°C -40°C -20°C 160 50°C 85°C 140 130 120 8 7 5 4.5 5 4 1.6 5.5 2.1 2.6 13 0°C 25°C 6 TJ 85°C 125°C 150°C -55°C -40°C 11 Quiescent Current (PA) Quiescent Current (PA) 5.6 12 TJ -55°C -40°C 10 9 8 7 6 0°C 25°C 85°C 125°C 150°C 10 9 8 7 6 5 5 4 1.6 5.1 Figure 6-34. I GND vs VIN Figure 6-33. Dropout Voltage vs VOUT 11 3.1 3.6 4.1 4.6 Input Voltage (V) VEN = 1 V, IOUT = 0 mA IOUT = 300 mA 12 150°C 9 100 3 3.5 4 Output Voltage ( V) 85°C 125°C 10 6 2.5 0°C 25°C 11 110 2 -55°C -40°C 12 150 90 1.5 TJ 13 125°C Quiescent Current (PA) Dropout Voltage (mV) 170 2.1 2.6 3.1 3.6 4.1 4.6 Input Voltage (V) 5.1 5.6 6 4 1.6 2.6 3.1 3.6 4.1 Input Voltage (V) 4.6 5.1 5.5 VOUT(NOM) = 5.5 V, VEN = 1 V, IOUT = 0 mA VEN = VIN, IOUT = 0 mA Figure 6-35. IGND vs VIN 2.1 Figure 6-36. IGND vs VIN in the Dropout Region Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 13 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 12 TJ -55°C -40°C 11 0°C 25°C 85°C 125°C 150°C Ground Current (uA) Quiescent Current (PA) 10 9 8 7 6 5 4 1.6 2.1 2.6 3.1 3.6 4.1 Input Voltage (V) 4.6 5.1 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 250 0 TJ -55°C -40°C 0 5.5 30 60 90 85°C 125°C 150°C 120 150 180 210 Output Current (mA) 240 270 300 VEN = 1 V VOUT(NOM) = 5.5 V, VEN = VIN, IOUT = 0 mA Figure 6-38. IGND vs IOUT Figure 6-37. IGND vs VIN in the Dropout Region 4000 500 TJ 450 85°C 125°C 150°C -55°C -40°C 400 Ground Current (PA) TJ -55°C -40°C 0°C 25°C 1000 Ground Current (PA) 0°C 25°C 100 10 0°C 25°C 85°C 125°C 150°C 350 300 250 200 150 100 50 0 2 0.001 0.01 0.1 1 Output Current (mA) 10 0 100 300 0.5 1 1.5 D072 VEN = 1 V 4.5 5 D073 Figure 6-40. IGND vs IOUT 45 4000 -55°C TJ -40°C 0°C 25°C Shutdown Current (nA) 30 25 20 15 10 TJ 125°C 85°C 3500 35 Shutdown Current (nA) 4 VEN = 1 V Figure 6-39. IGND vs IOUT 40 2 2.5 3 3.5 Output Current (mA) 150°C 3000 2500 2000 1500 1000 5 500 0 -5 1.6 2.1 2.6 3.1 3.6 4.1 4.6 Input Voltage (V) 5.1 5.6 6 0 1.6 2.1 3.1 3.6 4.1 4.6 Input Voltage (V) 5.1 5.6 6 VEN = 0 V VEN = 0 V Figure 6-41. Shutdown Current vs VIN 14 2.6 Figure 6-42. Shutdown Current vs VIN Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) 4500 4.5 4000 4 3500 3.5 Output Voltage (V) Enable Pin Leakage Current (nA) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 3000 2500 2000 1500 1000 TJ 25°C 85°C 125°C -55°C -40°C 0°C 500 TJ 0°C 25°C -55°C -40°C 3 2.5 2 1.5 1 150°C 0.5 0 0 0 0.5 1 1.5 2 2.5 3 3.5 VEN - VIN (V) 4 4.5 5 5.5 6 0 50 100 150 200 250 300 350 400 450 500 550 600 Output Current (mA) VEN = 6 V, IOUT = 0 mA VEN = 1 V Figure 6-43. Enable Pin Leakage Current vs VEN – VIN Figure 6-44. Current Limit 1.4 1.2 TJ -55°C -40°C 0°C 25°C 85°C 125°C VUVLO+ (VIN rising) VUVLO- (VIN falling) 1.39 150°C 1.38 Input Voltage (V) 1 Output Voltage (V) 85°C 125°C 0.8 0.6 0.4 1.37 1.36 1.35 1.34 1.33 1.32 0.2 1.31 1.3 -60 0 0 50 100 150 200 250 300 350 400 450 500 550 600 Output Current (mA) -40 -20 0 0.9 0.85 0.8 ( ( ( ( ( VIN Vout = Vout = Vout = Vout = Vout = 0.8 1.8 2.8 5.5 0.8 V V V V V ) ) ) ) - 5.5 V ) 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 160 Figure 6-47. Enable Logic High Threshold vs Temperature Enable Pin Logic Low Threshold VEN(LO) (V) Enable Pin Logic High Threshold VEN(HI) (V) 1 V V V V V D088 Figure 6-46. UVLO Threshold vs Temperature Figure 6-45. Current Limit 1.6 2.1 3.1 5.8 6.0 100 120 140 160 VEN = 1 V VOUT = 0.8 V, VEN = 1 V 0.95 20 40 60 80 Temperature (°C) 0.9 0.85 1.6 2.1 3.1 5.8 6.0 0.8 0.75 0.7 V V V V V ( ( ( ( ( VIN Vout = Vout = Vout = Vout = Vout = 0.8 1.8 2.8 5.5 0.8 V V V V V ) ) ) ) - 5.5 V ) 0.65 0.6 0.55 0.5 0.45 0.4 0.35 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 160 Figure 6-48. Enable Logic Low Threshold Low vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 15 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 400 300 Smart Enable Pulldown Resistor ( K:) Pulldown Resistor (:) 350 540 VIN 1.6 V ( VOUT = 0.8 V ) 2.1 V ( VOUT = 1.8 V ) 3.1 V ( VOUT = 2.8 V ) 6 V ( VOUT = 5.5 V ) 250 200 150 100 -60 -35 -10 15 40 65 90 Temperature (°C) 115 140 160 VIN 1.6 2.4 3.4 4.4 5.4 6.0 520 500 480 460 440 420 -60 -30 0 VEN = 0.25 V 150 0.9 10 0.8 40 IOUT VOUT 30 0.8 0 0.7 20 0.7 -10 0.6 10 0.6 -20 0.5 0 0.5 -30 0.4 -10 0.4 -40 0.3 -20 0.3 -50 0.2 -30 0.2 -60 0.1 -40 0.1 IOUT -70 VOUT -80 18 20 2 4 6 8 10 12 Time (Ps) 14 16 Output Current (A) 20 0 -50 -0.1 -60 40 0 4 8 12 16 D030 20 24 Time (µs) 28 32 36 D033 IOUT = 300 mA to 1 mA, tFALLING = 1 µs Figure 6-51. Load Transient Figure 6-52. Load Transient 0.9 0 0.8 40 IOUT VOUT 30 0.8 -20 0.7 20 0.7 -40 0.6 10 0.6 -60 0.5 0 0.5 -80 0.4 -10 0.4 -100 0.3 -20 0.3 -120 0.2 -30 0.2 -140 0.1 -40 0.1 IOUT -160 VOUT -180 18 20 0 2 4 6 8 10 12 Time (Ps) 14 16 0 -50 -0.1 -60 100 0 D031 IOUT = 1 mA to 300 mA, tRISING = 200 ns Figure 6-53. Load Transient 10 20 30 40 50 60 Time (µs) 70 80 90 AC-Coupled Output Voltage (mV) 0.9 AC-Coupled Output Voltage (mV) 20 Output Current (A) 1 0 AC-Coupled Output Voltage (mV) 1 AC-Coupled Output Voltage (mV) Output Current (A) 120 Figure 6-50. Smart Enable Pulldown Resistor vs Temperature and VIN IOUT = 1 mA to 300 mA, tRISING = 1 µs Output Current (A) 90 0.9 0 16 30 60 Temperature (°C) VEN = 0.25 V Figure 6-49. Output Pulldown Resistor vs Temperature 0 V V V V V V D032 IOUT = 300 mA to 1 mA, tFALLING = 200 ns Figure 6-54. Load Transient Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) 0.9 0 0.8 30 IOUT VOUT 20 0.7 -40 0.7 10 0.6 -80 0.6 0 0.5 -120 0.5 -10 0.4 -160 0.4 -20 0.3 -200 0.3 -30 0.2 -240 0.2 -40 0.1 -280 0.1 -50 0 IOUT -320 VOUT -360 18 20 -0.1 0 2 4 6 8 10 12 Time (µs) 14 16 Output Current (A) 40 0.8 0 -60 -0.1 -70 500 0 50 IOUT = 0 mA to 300 mA, tRISING = 1 µs 200 250 300 Time (µs) 350 400 450 D037 Figure 6-56. Load Transient 0.9 0.8 0 0.8 30 IOUT VOUT 20 0.7 -40 0.7 10 0.6 -80 0.6 0 0.5 -120 0.5 -10 0.4 -160 0.4 -20 0.3 -200 0.3 -30 0.2 -240 0.2 -40 0.1 -280 0.1 -50 0 IOUT -320 VOUT -360 18 20 -0.1 0 2 4 6 8 10 12 Time (µs) 14 16 Output Current (A) 40 0 -60 -0.1 -70 500 0 50 IOUT = 0 mA to 300 mA, tRISING = 200 ns 4 5 3 4 2 3 1 2 0 1 -1 0 -2 -1 -3 -2 -4 -3 100 30 40 50 60 Time (µs) 70 80 350 400 450 D036 90 6 5 6 VOUT 5 VIN 4 4 3 3 2 2 1 1 0 0 -1 -1 -2 -2 -3 -3 -4 -4 100 0 10 D060 VIN = 3.1 V → 4.1 V → 3.1 V, VIN tRISING = 5 µs, IOUT = 1 mA 20 30 40 50 60 Time (Ps) 70 80 90 Input Voltage (V) 7 VOUT 6 VIN Input Voltage (V) 5 20 200 250 300 Time (µs) Figure 6-58. Load Transient AC-Coupled Output Voltage (mV) 6 10 150 IOUT = 300 mA to 0 mA, tFALLING = 200 ns Figure 6-57. Load Transient 0 100 D034 AC-Coupled Output Voltage (mV) 0.9 AC-Coupled Output Voltage (mV) Output Current (A) 150 IOUT = 300 mA to 0 mA, tFALLING = 1 µs Figure 6-55. Load Transient AC-Coupled Output Voltage (mV) 100 D035 AC-Coupled Output Voltage (mV) 0.9 AC-Coupled Output Voltage (mV) Output Current (A) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) D061 VIN = 3.1 V → 4.1 V → 3.1 V, VIN tRISING = 5 µs, IOUT = 300 mA Figure 6-59. Line Transient Figure 6-60. Line Transient Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 17 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 120 VIN 3.10 V 3.30 V 3.80 V 110 100 90 Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) 120 80 70 60 50 40 30 20 10 0 10 100 1k 10k 100k Frequency (Hz) 1M VIN 3.1 V 3.3 V 3.8 V 110 100 90 80 70 60 50 40 30 20 10 0 10 10M 100 IOUT = 20 mA 110 110 Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) 120 100 90 80 70 60 50 40 30 10 0 10 0.01 mA 20 mA 100 1k 300 mA 10k 100k Frequency (Hz) 1M 10M D001 D015 Figure 6-62. PSRR vs Frequency and VIN 120 IOUT 100 mA 200 mA 10k 100k Frequency (Hz) IOUT = 300 mA Figure 6-61. PSRR vs VIN vs Frequency and VIN 20 1k D011 1M COUT 1 PF 10 PF 200 PF 100 90 80 70 60 50 40 30 20 10 0 10 10M 100 1k 10k 100k Frequency (Hz) D012 1M 10M D001 D013 IOUT = 20 mA Figure 6-63. PSRR vs Frequency and IOUT Figure 6-64. PSRR vs Frequency and COUT 2 2 IOUT 1 mA, RMS noise = 8.63 PVRMS 20 mA, RMS noise = 6.66 PVRMS 100 mA, RMS noise = 6.69 PVRMS 200 mA, RMS noise = 6.73 PVRMS 300 mA, RMS noise = 7.76 PVRMS 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 100 1k 10k 100k Frequency (Hz) 1M 10M 0.001 10 100 D002 VRMS BW = 10 Hz to 100 kHz 1k 10k 100k Frequency (Hz) 1M 10M D003 IOUT = 20 mA, VRMS BW = 10 Hz to 100 kHz Figure 6-65. Noise vs Frequency and IOUT 18 VIN 3.1 V, RMS Noise = 6.66 PVRMS 3.3 V, RMS Noise = 6.71 PVRMS 3.8 V, RMS Noise = 6.70 PVRMS 1 Output Voltage Noise (PV —Hz) Output Voltage Noise (PV —Hz) 1 Figure 6-66. Noise vs Frequency and VIN Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 2 2 VIN 3.1 V, RMS Noise = 6.76 PVRMS 3.3 V, RMS Noise = 6.77 PVRMS 3.8 V, RMS Noise = 7.10 PVRMS 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.001 10 100 1k 10k 100k Frequency (Hz) 1M 0.2 0.1 0.05 0.02 0.01 0.005 0.001 10 10M 1k 10k 100k Frequency (Hz) 1M Figure 6-67. Noise vs Frequency and VIN D006 Figure 6-68. Noise vs Frequency and COUT 2 COUT 1 PF, RMS noise = 7.14 PVRMS 10 PF, RMS noise = 7.14 PVRMS 200 PF, RMS noise = 6.87 PVRMS 0.5 IOUT 20 mA, RMS noise = 7.11 PVRMS 300 mA, RMS noise = 7.04 PVRMS 1 Output Voltage Noise (PV —Hz) 1 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 100 1k 10k 100k Frequency (Hz) 1M 0.001 10 10M 100 1k D007 VIN = 3.8 V, IOUT = 300 mA, VRMS BW = 10 Hz to 100 kHz 10k 100k Frequency (Hz) 1M D010 Figure 6-70. Noise vs Frequency and IOUT 2 2 IOUT 20 mA, RMS noise = 7.09 PVRMS 300 mA, RMS noise = 7.19 PVRMS 0.5 IOUT 20 mA, RMS noise = 7.21 PVRMS 300 mA, RMS noise = 7.69 PVRMS 1 Output Voltage Noise (PV —Hz) 1 0.2 0.1 0.05 0.02 0.01 0.005 0.002 10M VOUT = 0.8 V, VRMS BW = 10 Hz to 100 kHz Figure 6-69. Noise vs Frequency and COUT 0.001 10 10M VIN = 3.8 V, IOUT = 20 mA, VRMS BW = 10 Hz to 100 kHz 2 0.001 10 100 D004 IOUT = 300 mA, VRMS BW = 10 Hz to 100 kHz Output voltage Noise (PV —Hz) 0.5 0.002 0.002 Output voltage Noise (PV —Hz) COUT 1 PF, RMS noise = 6.65 PVRMS 10 PF, RMS noise = 6.94 PVRMS 200 PF, RMS noise = 6.56 PVRMS 1 Output voltage Noise (PV —Hz) Output Voltage Noise (PV —Hz) 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 100 1k 10k 100k Frequency (Hz) 1M 10M 0.001 10 D009 VOUT = 0.8 V, VIN = 1.8 V, VRMS BW = 10 Hz to 100 kHz Figure 6-71. Noise vs Frequency and IOUT 100 1k 10k 100k Frequency (Hz) 1M 10M D008 VOUT = 5.5 V, VIN = 6 V, VRMS BW = 10 Hz to 100 kHz Figure 6-72. Noise vs Frequency and IOUT Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 19 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 2 900 1.8 1.6 1.4 800 1.2 Voltage (V) Turnon Time (Ps) 850 750 700 1 0.8 0.6 0.4 650 VIN VEN VOUT ( IOUT = 0 mA) VOUT ( IOUT = 1 mA) VOUT ( IOUT = 300 mA) 0.2 0 600 -0.2 -0.4 550 -60 -40 -20 0 20 40 60 80 Temperature (°C) 0 100 120 140 160 From VEN = VEN(HI) to VOUT = 95% of VOUT(NOM), IOUT = 0 mA 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Time (Ps) D048 VOUT = 0.8 V, VIN = 0 V to 1.8 V, VEN = 0 V to 1.8 V, VEN rises 500 µs behind VIN, VIN and VEN slew rate = 1 V/µs Figure 6-74. Start-Up 2 2 1.8 1.8 1.6 1.6 1.4 1.4 1.2 1.2 Voltage (V) Voltage (V) Figure 6-73. Start-Up Turn-On Time 1 0.8 0.6 0.4 0 -0.2 0.6 0.4 VIN VEN VOUT ( IOUT = 0 mA) VOUT ( IOUT = 1 mA) VOUT ( IOUT = 300 mA) 0.2 1 0.8 0.2 VIN / VEN VOUT ( IOUT = 0 mA) VOUT ( IOUT = 1 mA) VOUT ( IOUT = 300 mA) 0 -0.2 -0.4 -0.4 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Time (Ps) D049 0 VOUT = 0.8 V, VIN = 0 V to 1.8 V, VEN = 0 V to 1.8 V, VEN rises 500 µs ahead of VIN, VIN and VEN slew rate = 1 V/µs Figure 6-75. Start-Up 600 800 1000 1200 1400 1600 1800 2000 Time (Ps) D050 Figure 6-76. Start-Up 4.5 4 4 3.5 3.5 3 Voltage (V) 3 Voltage (V) 400 VOUT = 0.8 V, VIN = 0 V to 1.8 V, VEN = VIN, VIN slew rate = 1 V/µs 4.5 2.5 2 1.5 1 VIN VEN VOUT ( IOUT = 0 mA) VOUT ( IOUT = 1 mA) VOUT ( IOUT = 300 mA) 0.5 0 -0.5 2.5 2 1.5 1 VIN VEN VOUT ( IOUT = 0 mA) VOUT ( IOUT = 1 mA) VOUT ( IOUT = 300 mA) 0.5 0 -0.5 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Time (Ps) D051 VIN = 0 V to 3.8 V, VEN = 0 V to 3.8 V, VEN rises 500 µs behind VIN, VIN and VEN slew rate = 1 V/µs 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Time (Ps) D052 VIN = 0 V to 3.8 V, VEN = 0 V to 3.8 V, VEN rises 500 µs ahead of VIN, VIN and VEN slew rate = 1 V/µs Figure 6-77. Start-Up 20 200 Figure 6-78. Start-Up Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 4.5 4 3.5 Voltage (V) Voltage (V) 3 2.5 2 1.5 1 VIN / VEN VOUT ( IOUT = 0 mA) VOUT ( IOUT = 1 mA) VOUT ( IOUT = 300 mA) 0.5 0 -0.5 0 200 400 600 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 0 800 1000 1200 1400 1600 1800 2000 Time (Ps) D053 VIN = 0 V to 3.8 V, VEN = 0 V to 3.8 V, VEN = VIN, VIN and slew rate = 1 V/µs VIN VEN VOUT ( IOUT = 0 mA) VOUT ( IOUT = 1 mA) VOUT ( IOUT = 300 mA) 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Time (us) D054 VOUT = 5.5 V, VIN = 0 V to 6.0 V, VEN = 0 V to 6.0 V, VEN rises 500 µs behind VIN, VIN and VEN slew rate = 1 V/µs Figure 6-80. Start-Up Voltage (V) Voltage (V) Figure 6-79. Start-Up 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 VIN VEN VOUT ( IOUT = 0 mA) VOUT ( IOUT = 1 mA) VOUT ( IOUT = 300 mA) 0 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Time (Ps) D055 VIN / VEN VOUT ( IOUT = 0 mA) VOUT ( IOUT = 1 mA) VOUT ( IOUT = 300 mA) 0 VOUT = 5.5 V, VIN = 0 V to 6.0 V, VEN = 0 V to 6.0 V, VEN rises 500 µs ahead of VIN, VIN and VEN slew rate = 1 V/µs 200 400 800 1000 1200 1400 1600 1800 2000 Time (Ps) D056 VOUT = 5.5 V, VIN = 0 V to 6 V, VEN = VIN, VIN slew rate = 1 V/µs Figure 6-81. Start-Up Figure 6-82. Start-Up 300 2.25 270 16 2 240 4 14 1.75 210 3.5 12 1.5 180 3 10 1.25 150 2.5 VIN VEN VOUT 1 6 0.75 4 2 0 0 120 240 360 480 600 720 Time (µs) 840 5 IIN VIN VEN 120 VOUT 4.5 2 90 1.5 0.5 60 1 0.25 30 0.5 0 960 1080 1200 0 0 150 D047 VOUT = 0.8 V, VIN = 1.8 V, VEN = 0 V to 1.8 V, VEN slew rate = 1 V/µs, COUT = 10 µF 300 450 Voltage (V) 8 Voltage (V) 2.5 IIN 18 Input CUrrent (mA) 20 Input Current (mA) 600 0 600 750 900 1050 1200 1350 1500 Time (µs) D043 VIN = 3.8 V, VEN = 0 V to 3.8 V, VEN slew rate = 1 V/µs, COUT = 10 µF Figure 6-83. Inrush Current Figure 6-84. Inrush Current Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 21 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 6.7 Typical Characteristics (continued) VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C (unless otherwise noted) 800 8 IIN VIN VEN VOUT 7.2 640 6.4 560 5.6 480 4.8 400 4 320 3.2 240 2.4 160 1.6 80 0.8 0 0 150 300 450 Voltage (V) Input Current (mA) 720 0 600 750 900 1050 1200 1350 1500 Time (µs) D044 VOUT = 5.5 V, VIN = 6.0 V, VEN = 0 V to 6.0 V, VEN slew rate = 1 V/µs, COUT = 10 µF Figure 6-85. Inrush Current 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 7 Detailed Description 7.1 Overview Designed to meet the needs of sensitive RF and analog circuits, the TPS7A20 provides low noise, high PSRR, low quiescent current, as well as low line and load transient response figures. Using innovative design techniques, the TPS7A20 offers class-leading noise performance without the need for a separate noise filter capacitor. The TPS7A20 is designed to operate with a single 1-µF input capacitor and a single 1-µF ceramic output capacitor. 7.2 Functional Block Diagram Current Limit IN Bandgap OUT + Active Discharge P-Version Only ± ± + Error Amp + UVLO Thermal Shutdown Internal Controller EN 500NŸ GND Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 23 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 7.3 Feature Description 7.3.1 Low Output Noise Any internal noise at the TPS7A20 reference voltage is reduced by a first-order, low-pass RC filter before being passed to the output buffer stage. The low-pass RC filter has a –3-dB cut-off frequency of approximately 0.1 Hz. During start-up, the filter resistor is bypassed to reduce output rise time; the filter begins normal operation after the output voltage reaches the correct value. 7.3.2 Smart Enable The enable (EN) input polarity is active high. The output voltage is enabled when the voltage of the enable input is greater than VEN(HI) and disabled when the enable input voltage is less than VEN(LOW). If independent control of the output voltage is not needed, connect EN to IN. This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable internal pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical Characteristics table. 7.3.3 Dropout Voltage Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the value required to maintain output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. RDS(ON) = VDO IRATED (1) 7.3.4 Foldback Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brickwall current limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application report. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 Figure 7-1 shows a diagram of the foldback current limit. VOUT Brickwall VOUT(NOM) VFOLDBACK Foldback IOUT 0V 0 mA ISC IRATED ICL Figure 7-1. Foldback Current Limit 7.3.5 Undervoltage Lockout (UVLO) The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table. 7.3.6 Thermal Shutdown A thermal shutdown protection circuit disables the LDO when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device resets (turns on) when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before startup completes. For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating Conditions table. Operation above this maximum temperature causes the device to exceed its operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 25 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 7.3.7 Active Discharge An internal pulldown MOSFET connects a resistor from OUT to ground when the device is disabled to actively discharge the output capacitance. The active discharge circuit is activated by driving EN low or by the voltage on IN falling below the undervoltage lockout (UVLO) threshold. Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a short period of time. 7.4 Device Functional Modes 7.4.1 Device Functional Mode Comparison Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table for parameter values. Table 7-1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VEN IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown) VIN < VUVLO VEN < VEN(LOW) Not applicable TJ > TSD(shutdown) Disabled (any true condition disables the device) 7.4.2 Normal Operation The device regulates to the nominal output voltage when the following conditions are met: • • • The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) • The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to less than the enable falling threshold 7.4.3 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. 7.4.4 Disabled The output of the LDO can be shut down by driving EN to less than VEN(LOW) (see the Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shut down, and the output voltage is actively discharged to ground by an internal discharge circuit between OUT and ground. 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Recommended Capacitor Types The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors recommended in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. 8.1.2 Input and Output Capacitor Requirements Although the LDO itself is stable without an input capacitor, good analog design practice is to connect a capacitor from IN to GND, with a value at least equal to the nominal value specified in the Recommended Operating Conditions table. The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR, and is recommended if the source impedance is greater than 0.5 Ω. When the source resistance and inductance are sufficiently high, especially in the presence of load transients, the overall system may be susceptible to instability (including ringing and sustained oscillation) and other performance degradation if there is insufficient capacitance between IN and GND. A capacitor with a value greater than the minimum may be necessary if large, fast-rise-time load or line transients are anticipated or if the device is located more than a few centimeters from the input power source. An output capacitor of an appropriate value helps ensure stability and improve dynamic performance. Use an output capacitor within the range specified in the Recommended Operating Conditions table. 8.1.3 Load Transient Response The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure 8-1 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state. tAt tCt tDt B tEt tGt tHt F Figure 8-1. Load Transient Waveform During transitions from a light load to a heavy load, the: • Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the output capacitor (region B) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 27 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 • Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation (region C) During transitions from a heavy load to a light load, the: • • Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase (region F) Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor (region G) A larger output capacitance reduces the peaks during a load transient but slows down the response time of the device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher current discharge path is provided for the output capacitor. 8.1.4 Undervoltage Lockout (UVLO) Operation The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure 8-2 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the following parts: • • • • • • • Region A: The device does not start until the input reaches the UVLO rising threshold. Region B: Normal operation, regulating device. Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The output may fall out of regulation but the device remains enabled. Region D: Normal operation, regulating device. Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls because of the load and active discharge circuit. The device is re-enabled when the UVLO rising threshold is reached by the input voltage and a normal start-up follows. Region F: Normal operation followed by the input falling to the UVLO falling threshold. Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The output falls because of the load and active discharge circuit. UVLO Rising Threshold UVLO Hysteresis VIN C VOUT tAt tBt tDt tEt tFt tGt Figure 8-2. Typical UVLO Operation 8.1.5 Power Dissipation (PD) Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses. As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. Use Equation 2 to approximate PD: PD = (VIN – VOUT) × IOUT (2) Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the TPS7A20 allows for maximum efficiency across a wide range of output voltages. 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane. The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. According to Equation 3, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). Equation 4 rearranges Equation 3 for output current. TJ = TA + (RθJA × PD) (3) IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)] (4) Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the X2SON package junction-to-case (bottom) thermal resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper. 8.1.5.1 Estimating Junction Temperature The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table. ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD (5) where: • • • PD is the power dissipated as explained in Equation 2 TT is the temperature at the center-top of the device package TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge 8.1.5.2 Recommended Area for Continuous Operation The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-3 and can be separated into the following parts: • • • • Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a given output current level. See the Dropout Operation section for more details. The rated output currents limits the maximum recommended output current level. Exceeding this rating causes the device to fall out of specification. The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating causes the device to fall out of specification and reduces long-term reliability. – The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum-rated junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN – VOUT increases the output current must decrease. The rated input voltage range governs both the minimum and maximum of VIN – VOUT. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 29 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 Output Current (A) Figure 8-3 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a RθJA as given in the Thermal Information table. Output current limited by dropout Rated output current Output current limited by thermals Limited by maximum VIN Limited by minimum VIN VIN ± VOUT (V) Figure 8-3. Region Description of Continuous Operation Regime 8.2 Typical Application Figure 8-4 shows the typical application circuit for the TPS7A20. Input and output capacitances may need to be increased above the 1 µF minimum for some applications. VOUT VIN INPUT OUTPUT 1.0 µF 1.0 µF TPS7A20 VEN ENABLE GND GND SVA-30180501 Figure 8-4. TPS7A20 Typical Application 8.2.1 Design Requirements Table 8-1 summarizes the design requirements for Figure 8-4. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 3.1 V to 3.6 V Output voltage 2.8 V Output current 200 mA Maximum ambient temperature 85°C 8.2.2 Detailed Design Procedure For this design example, the 2.8-V output version (TPS7A2028) is selected. A nominal 3.3-V input supply is assumed. A minimum 1.0-μF input capacitor is recommended to minimize the effect of resistance and inductance between the 3.3-V source and the LDO input. A minimum 1.0-μF output capacitor is also 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 recommended for stability and good load transient response. The dropout voltage (VDO) is less than 140 mV maximum at a 2.8-V output voltage and 300-mA output current, so there are no dropout issues with a minimum input voltage of 3.0 V and a maximum output current of 200 mA. 4.5 100 4 90 3.5 80 3 70 PSRR (dB) Voltage (V) 8.2.3 Application Curves 2.5 2 1.5 1 IOUT 200 mA 60 50 40 30 0.5 20 VIN / VEN VOUT 0 -0.5 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Time (us) D064 10 0 10 20 Figure 8-5. Start-Up 100 1000 10000 100000 1000000 Frequency (Hz) 1E+7 D065 Figure 8-6. PSRR 9 Power Supply Recommendations This device is designed to operate from an input supply voltage range of 1.6 V to 6.0 V. The input supply must be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic performance is optimum, the input supply must be at least VOUT(nom) + 0.3 V or 1.6 V, whichever is greater. TI highly recommends using a 1-µF or greater input capacitor to reduce the impedance of the input supply, especially during transients. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 31 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 10 Layout 10.1 Layout Guidelines • • • • Place input and output capacitors as close to the device as possible. Use copper planes for device connections to optimize thermal performance. Place thermal vias around the device to distribute the heat. Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad. 10.2 Layout Examples VIN VOUT CIN 1 IN 2 GND 3 EN COUT 5 OUT GND GND Enable 4 N/C Figure 10-1. DBV Package (SOT-23) Typical Layout TPS7A20 VOUT 1 VIN 4 COUT CIN 2 3 Power Ground VEN Figure 10-2. DQN Package (X2SON) Typical Layout VIN VOUT TPS7A20 A1 A2 B1 B2 COUT CIN VEN Power Ground Figure 10-3. YCJ and YCK Package (DSBGA) Typical Layout 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature Table 11-1. Device Nomenclature (1) (2) PRODUCT (1) (2) VOUT TPS7A20xx(x)Pyyyz xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). P indicates an active output discharge feature. All members of the TPS7A20 family actively discharge the output when the device is disabled. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces for DQN and DBV; 12000 pieces for YCJ and YCK). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. Output voltages from 0.8 V to 5.5 V in 25-mV increments are available. Contact the factory for details and availability. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 33 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 12.1 Mechanical Data PACKAGE OUTLINE YCJ0004-C02 DSBGA - 0.35 mm max height SCALE 15.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER D C 0.35 MAX SEATING PLANE 0.13 0.07 BALL TYP 0.05 C 0.35 TYP B D: Max = 0.636 mm, Min = 0.596 mm SYMM 0.35 TYP E: Max = 0.636 mm, Min = 0.596 mm A 4X 0.015 0.20 0.16 1 SYMM 2 C A B 4226216/A 09/2020 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 EXAMPLE BOARD LAYOUT YCJ0004-C02 DSBGA - 0.35 mm max height DIE SIZE BALL GRID ARRAY (0.35) TYP 4X ( 0.18) 2 1 A SYMM (0.35) TYP B SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 50X 0.0375 MAX 0.0375 MIN METAL UNDER SOLDER MASK EXPOSED METAL ( 0.18) SOLDER MASK OPENING ( 0.18) METAL SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED (PREFERRED) NON-SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4226216/A 09/2020 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 35 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 EXAMPLE STENCIL DESIGN YCJ0004-C02 DSBGA - 0.35 mm max height DIE SIZE BALL GRID ARRAY (0.39) TYP (R0.05) TYP 4X ( 0.21) 1 2 A SYMM (0.39) TYP B METAL TYP SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL SCALE: 50X 4226216/A 09/2020 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com 36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 PACKAGE OUTLINE YCK0004-C01 DSBGA - 0.33mm MAX HEIGHT SCALE 15.000 DIE SIZE BALL GRID ARRAY A B E BUMP A1 CORNER D 0.33 MAX C SEATING PLANE 0.13 0.07 0.05 C BUMP 0.175 D: Max = 0.636 mm, Min = 0.596 mm B E: Max = 0.636 mm, Min = 0.596 mm 0.175 0.35 A 4X 0.015 0.20 0.16 C A B 1 2 0.35 4228575/A 03/2022 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 37 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 EXAMPLE BOARD LAYOUT YCK0004-C01 DSBGA - 0.33mm MAX HEIGHT DIE SIZE BALL GRID ARRAY SYMM 4X ( 0.18) 1 (0.175) 2 A SYMM (0.35) B (0.175) (0.35) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:60X 0.0375 MAX 0.0375 MIN ( 0.18) METAL EXPOSED METAL SOLDERMASK OPENING ( 0.18) SOLDERMASK OPENING EXPOSED METAL NON SOLDERMASK DEFINED METAL UNDER SOLDER MASK SOLDERMASK DEFINED (PREFERRED) SOLDERMASK DETAILS NOT TO SCALE 4228575/A 03/2022 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). www.ti.com 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 TPS7A20 www.ti.com SBVS338G – MARCH 2020 – REVISED MAY 2022 EXAMPLE STENCIL DESIGN YCK0004-C01 DSBGA - 0.33mm MAX HEIGHT DIE SIZE BALL GRID ARRAY METAL TYP (R0.05) TYP SYMM 2 1 A 4X ( 0.21) (0.195) SYMM (0.39) B (0.195) (0.39) SOLDERPASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL SCALE:80X 4228575/A 03/2022 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS7A20 39 PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) PTPS7A2025PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 Samples PTPS7A2045PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 Samples TPS7A2009PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GBF Samples TPS7A2009PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KT Samples TPS7A20105PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KS Samples TPS7A2011PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 Q Samples TPS7A2012PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2ATF Samples TPS7A2012PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JC Samples TPS7A2012PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 M Samples TPS7A2015PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2DTF Samples TPS7A2015PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JD Samples TPS7A201825PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 IQ Samples TPS7A20185PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green Level-1-260C-UNLIM -40 to 125 2CBF Samples TPS7A20185PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JE Samples TPS7A20185PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 T Samples TPS7A2018PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AUF Samples TPS7A2018PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JF Samples TPS7A2018PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JF Samples TPS7A2018PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 D Samples TPS7A2020PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 S Samples NIPDAU | SN Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 4-Aug-2023 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS7A2022PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 K Samples TPS7A2024PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2CCF Samples TPS7A2025PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AVF Samples TPS7A2025PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JG Samples TPS7A2025PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 L Samples TPS7A2027PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KO Samples TPS7A2027PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 N Samples TPS7A20285PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GCF Samples TPS7A20285PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KN Samples TPS7A20285PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 P Samples TPS7A2028PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AWF Samples TPS7A2028PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JH Samples TPS7A2028PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JH Samples TPS7A2028PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 E Samples TPS7A2028PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 E Samples TPS7A2029PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JI Samples TPS7A2030PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AXF Samples TPS7A2030PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JJ Samples TPS7A2031PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GDF Samples TPS7A2032PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GEF Samples TPS7A2033PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AZF Samples Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 4-Aug-2023 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS7A2033PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JA Samples TPS7A2033PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JA Samples TPS7A2033PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 O Samples TPS7A2036PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GIF Samples TPS7A2036PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KP Samples TPS7A2040PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KQ Samples TPS7A2042PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GFF Samples TPS7A2042PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KV Samples TPS7A2045PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GGF Samples TPS7A2045PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JB Samples TPS7A2050PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2B1F Samples TPS7A2050PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KR Samples TPS7A2050PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KR Samples TPS7A2050PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 H Samples TPS7A2055PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GHF Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2023 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of