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TPS7A7100
SBVS189F – MARCH 2012 – REVISED SEPTEMBER 2015
TPS7A7100 1-A, Fast-Transient, Low-Dropout Voltage Regulator
1 Features
3 Description
•
•
•
•
•
•
•
The TPS7A7100 low-dropout (LDO) voltage regulator
is designed for applications seeking very-low dropout
capability (140 mV at 1 A) with an input voltage from
1.5 V to 6.5 V. The TPS7A7100 offers an innovative,
user-configurable, output-voltage setting from 0.9 V to
3.5 V, eliminating external resistors and any
associated error.
1
•
•
•
Low-Dropout Voltage: 140 mV at 1 A
VIN Range: 1.5 V to 6.5 V
Configurable Fixed VOUT Range: 0.9 V to 3.5 V
Adjustable VOUT Range: 0.9 V to 5 V
Very Good Load- and Line-Transient Response
Stable With Ceramic Output Capacitor
1.5% Accuracy Overline, Overload, and
Overtemperature
Programmable Soft Start
Power Good (PG) Output
3-mm × 3-mm QFN-16 and 5-mm × 5-mm QFN20 Packages
2 Applications
•
•
•
•
•
•
Wireless Infrastructure: SerDes, FPGA, DSP™
RF Components: VCO, ADC, DAC, LVDS
Set-Top Boxes: Amplifier, ADC, DAC, FPGA, DSP
Wireless LAN, Bluetooth®
PCs and Printers
Audio and Visual
The TPS7A7100 has very fast load-transient
response, is stable with ceramic output capacitors,
and supports a better than 2% accuracy over line,
load, and temperature. A soft-start pin allows for an
application to reduce inrush into the load.
Additionally, an open-drain, power-good signal allows
for sequencing power rails.
The TPS7A7100 is available in 3-mm × 3-mm,
16-pin VQFN and 5-mm × 5-mm, 20-pin VQFN
packages.
Device Information(1)
PART NUMBER
TPS7A7100
PG
CIN
TPS7A7100
EN
CSS
OUT
SNS
CFF
VQFN (20)
5.00 mm × 5.00 mm
Load Transient Response With
Seven Different Outputs:
1.5 VIN to 1 VOUT, 1.5 VIN to 1.2 VOUT,
1.8 VIN to 1.5 VOUT, 2.5 VIN to 1.8 VOUT,
3 VIN to 2.5 VOUT, 3.3 VIN to 3 VOUT,
and 5.5 VIN to 5 VOUT
1.5 V
SS
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
IN
PACKAGE
VQFN (16)
1.2 V = 0.5 Vref
+ 100 mV
COUT + 200 mV
+ 400 mV
6
3
5.5V to 5.0V
Output Current Slew Rate: 1A/µs
50mV
100mV
1.6V
200mV 400mV 800mV
4
3.3V to 3.0V
Output Current
3.0V to 2.5V
2.5V to 1.8V
2
1.8V to 1.5V
3
2
1
Output Current (A)
GND
Output Voltage (V)
5
FB
Optional
1
1.5V to 1.2V
0
1.5V to 1.0V
0
Time (100µs/div)
G310
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A7100
SBVS189F – MARCH 2012 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configurations.................................................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
21
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 26
10.1
10.2
10.3
10.4
10.5
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
Estimating Junction Temperature ........................
26
26
27
27
28
11 Device And Documentation Support................. 30
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
12 Mechanical, Packaging, And Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2013) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed from Enable and Shutdown the Device to Enable ................................................................................................ 20
Changes from Revision C (May 2012) to Revision D
Page
•
Added CFF capacitor to front page block diagram .................................................................................................................. 1
•
Added text to FB pin description ............................................................................................................................................ 3
•
Added CFF test condition and table note to Electrical Characteristics.................................................................................... 6
•
Deleted maximum value for Output Current Limit parameter in Electrical Characteristics .................................................... 6
•
Added CFF capacitor to Figure 22......................................................................................................................................... 12
•
Added CFF capacitor to Figure 23......................................................................................................................................... 13
•
Added CFF capacitor to Figure 24......................................................................................................................................... 14
•
Added CFF capacitor to Figure 25......................................................................................................................................... 15
•
Added CFF capacitor to Figure 26......................................................................................................................................... 16
•
Added CFF capacitor to Figure 27......................................................................................................................................... 17
•
Added CFF capacitor to Figure 28......................................................................................................................................... 19
•
Added CFF capacitor to front page block diagram ................................................................................................................ 22
•
Changed capacitor values in first sentence of Output Capacitor Requirements section ..................................................... 23
Changes from Revision B (April 2012) to Revision C
Page
•
Added RGT package to Figure 42 ....................................................................................................................................... 27
•
Added RGT package to Figure 44 ....................................................................................................................................... 29
2
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SBVS189F – MARCH 2012 – REVISED SEPTEMBER 2015
5 Pin Configurations
OUT
GND
IN
IN
18
17
16
IN
13
19
IN
14
OUT
OUT
15
RGW Package
20-Pin VQFN
Top View
20
OUT
16
RGT Package
16-Pin VQFN
Top View
SNS
1
12
EN
OUT
1
15
IN
FB
2
11
SS
SNS
2
14
EN
PG
3
10
1.6V
FB
3
13
SS
50mV
4
9
800mV
PG
4
12
NC
50mV
5
11
1.6V
7
8
9
10
GND
400mV
800mV
8
400mV
200mV
7
GND
6
6
200mV
Thermal Pad
100mV
5
100mV
Thermal Pad
Pin Functions
PIN
NAME
50mV,
100mV,
200mV,
400mV,
800mV,
1.6V
RGW
RGT
I/O
DESCRIPTION
5, 6, 7,
9, 10, 11
4, 5, 6,
8, 9, 10
I
Output voltage setting pins. These pins must be connected to ground or left floating.
Connecting these pins to ground increases the output voltage by the value of the pin name;
multiple pins can be simultaneously connected to GND to select the desired output voltage.
Leave these pins floating (open) when not in use. See the User-Configurable Output Voltage
section for more details.
EN
14
12
I
Enable pin. Driving this pin to logic high enables the device; driving the pin to logic low disables
the device. See the Enable section for more details.
FB
3
2
I
Output voltage feedback pin. Connected to the error amplifier. See the User-Configurable
Output Voltage and Traditional Adjustable Configuration sections for more details. TI highly
recommends connecting a 220-pF ceramic capacitor from FB pin to OUT.
8, 18
7
—
IN
15, 16,
17
13, 14
I
NC
12
—
—
Not internally connected. The NC pin is not connected to any electrical node. TI strongly
recommends connecting this pin and the thermal pad to a large-area ground plane. See the
Power Dissipation section for more details.
1, 19, 20
15, 16
O
Regulated output pin. A 4.7-μF or larger capacitance is required for stability. See Output
Capacitor Requirements for more details.
PG
4
3
O
Active-high power good pin. An open-drain output that indicates when the output voltage
reaches 90% of the target. See Power Good for more details.
SNS
2
1
I
Output voltage sense input pin. See the User-Configurable Output Voltage and Traditional
Adjustable Configuration sections for more details.
SS
13
11
—
Soft-start pin. Leaving this pin open provides soft start of the default setting.
Connecting an external capacitor between this pin and the ground enables the soft-start
function by forming an RC-delay circuit in combination with the integrated resistance on the
silicon. See the Soft-Start section for more details.
—
TI strongly recommends connecting the thermal pad to a large-area ground plane. If available,
connect an electrically-floating, dedicated thermal plane to the thermal pad as well.
GND
OUT
Thermal Pad
Ground pin.
Unregulated supply voltage pin. TI recommends connecting an input capacitor to this pin. See
Input Capacitor Requirements for more details.
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SBVS189F – MARCH 2012 – REVISED SEPTEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted). (1)
IN, PG, EN
Voltage
(2)
7
–0.3
50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V
–0.3
UNIT
V
VIN + 0.3
(2)
VOUT + 0.3 (2)
Internally limited
PG (sink current into IC)
Temperature
(1)
MAX
SS, FB, SNS, OUT
OUT
Current
MIN
–0.3
V
V
A
5
mA
Operating virtual junction, TJ
–55
160
°C
Storage, Tstg
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is VIN + 0.3 V or +7 V, whichever is smaller.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Supply voltage
1.425
VOUT
Output voltage
VEN
Enable voltage
VPG
NOM
MAX
UNIT
6.5
V
0.9
5
V
0
6.5
V
Pullup voltage
0
6.5
V
50 mV, 100 mV, 200 mV,
400 mV, 800 mV, 1.6 V
Any-out voltage
0
VOUT
IOUT
Output current
COUT
Output capacitance
CFB
Feedforward capacitance
TJ
Junction temperature
(1)
4
0
1
A
4.7
200 (1)
µF
0
100
nF
–40
125
°C
For output capacitors larger than 47 µF a feedforward capacitor of at least 220 pF must be used.
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6.4 Thermal Information
TPS7A7100 (3)
THERMAL METRIC
RθJA
(1) (2)
Junction-to-ambient thermal resistance (4)
(5)
RGW (VQFN)
RGT (VQFN)
20 PINS
16 PINS
UNIT
35.7
44.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
33.6
54.3
°C/W
RθJB
Junction-to-board thermal resistance (6)
15.2
17.2
°C/W
ψJT
Junction-to-top characterization parameter (7)
0.4
1.1
°C/W
15.4
17.2
°C/W
3.8
3.8
°C/W
(8)
ψJB
Junction-to-board characterization parameter
RθJC(bot)
Junction-to-case (bottom) thermal resistance (9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
For thermal estimates of this device based on printed-circuit-board (PCB) copper area, see the TI PCB Thermal Calculator.
Thermal data for the RGW package is derived by thermal simulations based on JEDEC-standard methodology as specified in the
JESD51 series. The following assumptions are used in the simulations:
(a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4 × 4 thermal via array.
ii. RGT: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.
(b) i. RGW: Both the top and bottom copper layers have a dedicated pattern for 4% copper coverage.
ii .RGT: Both the top and bottom copper layers have a dedicated pattern for 5% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area.
To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction
Temperature sections.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to +125°C), 1.425 V ≤ VIN ≤ 6.5 V, VIN ≥ VOUT(TARGET) + 0.3 V or VIN ≥
VOUT(TARGET) + 0.5 V (1) (2), OUT connected to 50 Ω to GND (3),VEN = 1.1 V, COUT = 10 μF, CSS = 10 nF, CFF = 0 pF (RGW
package), CFF = 220 pF (RGT package) (4), and PG pin pulled up to VIN with 100 kΩ, 27 kΩ ≤ R2 ≤ 33 kΩ for adjustable
configuration (5), unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage
V(SS)
SS pin voltage
TEST CONDITIONS
VOUT
Output voltage accuracy (6) (7)
Fixed with voltage setting pins
0.9
3.5
–1.5%
1.5%
RGT package only, fixed, –40°C ≤ TA ≤ 85°C,
25 mA ≤ IOUT ≤ 1 A
–2%
2%
Adjustable, 25 mA ≤ IOUT ≤ 1 A
–2%
2%
Fixed, 25 mA ≤ IOUT ≤ 1 A
–3%
IOUT = 25 mA
ΔVO(ΔIO)
Load regulation
25 mA ≤ IOUT ≤ 1 A
(8)
Output current limit
140
mV
3.3 V < VOUT, IOUT = 1 A, V(FB) = GND
350
mV
VOUT forced at 0.9 × VOUT(TARGET), VIN = 3.3 V,
VOUT(TARGET) = 0.9 V
1.1
VIL(EN)
EN pin low-level input voltage
(disable device)
VIH(EN)
EN pin high-level input voltage
(enable device)
VIT(PG)
PG pin threshold
For the direction PG↓ with decreasing VOUT
Vhys(PG)
PG pin hysteresis
For PG↑
VOL(PG)
PG pin low-level output voltage
VOUT < VIT(PG), IPG = –1 mA (current into device)
Ilkg(PG)
PG pin leakage current
VOUT > VIT(PG), V(PG) = 6.5 V
I(SS)
SS pin charging current
V(SS) = GND, VIN = 3.3 V
Vn
Output noise voltage
BW = 100 Hz to 100 kHz,
VIN = 1.5 V, VOUT = 1.2 V, IOUT = 1 A
Tsd
Thermal shutdown temperature
TJ
Operating junction temperature
6
1.6
A
1.8
mA
Minimum load,
VIN = 6.5 V, VOUT(TARGET) = 0.9 V, IOUT = 25 mA
EN pin current
(8)
%/A
VOUT ≤ 3.3 V, IOUT = 1 A, V(FB) = GND
I(EN)
(3)
(4)
(5)
(6)
(7)
V
%/V
0.1
4
mA
5
μA
±0.1
μA
0
0.5
V
1.1
6.5
V
0.96VOUT
V
Shutdown, PG = (open),
VIN = 6.5 V, VOUT(TARGET) = 0.9 V, V(EN) < 0.5 V
(1)
(2)
V
3%
0.01
Full load, IOUT = 1 A
GND pin current
UNIT
V
5
Line regulation
I(GND)
6.5
0.9
ΔVO(ΔVI)
I(LIM)
MAX
Adjustable with external feedback resistors
RGT package only, adjustable, –40°C ≤ TA ≤ 85°C,
25 mA ≤ IOUT ≤ 1 A
Dropout voltage
TYP
0.5
Output voltage
V(DO)
MIN
1.425
0.1
VIN = 6.5 V, V(EN) = 0 V and 6.5 V
0.85VOUT
0.9VOUT
0.02VOUT
3.5
5.1
V
0.4
V
1
μA
7.2
μA
μVRMS
39.57
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
–40
°C
°C
125
°C
When VOUT ≤ 3.5 V, VIN ≥ (VOUT + 0.3 V) or 1.425 V, whichever is greater; when VOUT > 3.5 V, VIN ≥ (VOUT + 0.5 V).
VOUT(TARGET) is the calculated target VOUT value from the output voltage setting pins: 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, and
1.6 V in fixed configuration, or the expected VOUT value set by external feedback resistors in adjustable configuration.
This 50-Ω load is disconnected when the test conditions specify an IOUT value.
CFF is the capacitor between FB pin and OUT.
R2 is the bottom-side of the feedback resistor between the FB pin and GND. See for details.
When the TPS7A7100 is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
The TPS7A7100 is not tested at VOUT = 0.9 V, 2.7 V ≤ VIN ≤ 6.5 V, and 500 mA ≤ IOUT ≤ 1 A because the power dissipation is higher
than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the
power dissipation limit of the package.
V(DO) is not defined for output voltage settings less than 1.2 V.
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6.6 Typical Characteristics
At TJ = 25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩ pullup resistor, unless otherwise noted.
− 40°C
0°C
25°C
85°C
105°C
125°C
Output Voltage (V)
0.918
0.909
5.15
Y−axis scale is 1%Vout/div
Y−axis scale is 1%Vout/div
5.1
Output Voltage (V)
0.927
0.9
0.891
0.882
0.873
0.2
0.4
0.6
Output Current (A)
0.8
5
− 40°C
0°C
25°C
85°C
105°C
125°C
4.95
4.9
VIN = 1.425 V
R1 = 24.1 kΩ, R2 = 30.1 kΩ
0
5.05
4.85
1
0
0.2
G000
Figure 1. Load Regulation (0.9 V, Adjustable)
3.605
− 40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
3.57
Output Voltage (V)
Output Voltage (V)
0.918
0.909
0.9
0.891
0.882
0.873
0
0.2
VIN = 1.425 V
VOUT(TARGET) = 0.9 V
400mV pin to GND; 50mV, 100mV
200mV, 800mV, 1.6V pins open
0.4
0.6
Output Current (A)
0.8
0.2
0
0.2
0.8
1
− 40°C
0°C
25°C
85°C
105°C
125°C
150
0.8
1
G203
IOUT = 1 A
FB = GND and plot VIN − VOUT
100
50
0
1
2
G010
Figure 5. Dropout Voltage vs Output Current
0.4
0.6
Output Current (A)
Figure 4. Load Regulation (3.5 V, Fixed By Setting Pins)
VIN = 1.5 V
FB = GND
0.4
0.6
Output Current (A)
VIN = 3.8 V
VOUT(TARGET) = 3.5 V
200mV, 400mV, 800mV, 1.6V pins
to GND; 50mV, 100mV pins open
3.465
G200
50
0
G003
Y−axis scale is 1%Vout/div
100
0
1
3.5
3.395
1
Dropout Voltage (mV)
Dropout Voltage (mV)
150
3.535
200
− 40°C
0°C
25°C
85°C
105°C
125°C
0.8
3.43
Figure 3. Load Regulation (0.9 V, Fixed By Setting Pins)
200
0.4
0.6
Output Current (A)
Figure 2. Load Regulation (5 V, Adjustable)
0.927
− 40°C
0°C
25°C
85°C
105°C
125°C
VIN = 5.3 V
R1 = 271 kΩ, R2 = 30.1 kΩ
3
4
Input Voltage (V)
5
5.5
G013
Figure 6. Dropout Voltage vs Temperature
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Typical Characteristics (continued)
At TJ = 25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩ pullup resistor, unless otherwise noted.
0.927
0.909
Y−axis scale is 1%Vout/div
Y−axis scale is 1%Vout/div
5.1
Output Voltage (V)
0.918
Output Voltage (V)
5.15
− 40°C
0°C
25°C
85°C
105°C
125°C
0.9
0.891
0.882
0.873
1.5
2
2.5
3 3.5 4 4.5
Input Voltage (V)
5
5.5
6
5
− 40°C
0°C
25°C
85°C
105°C
125°C
4.95
4.9
IOUT = 25 mA
R1 = 24.1 kΩ, R2 = 30.1 kΩ
1
5.05
4.85
6.5
5
5.5
6
Input Voltage (V)
G006
Figure 7. Line Regulation (0.9 V, Adjustable)
3.605
− 40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
3.57
Output Voltage (V)
Output Voltage (V)
0.918
0.909
0.9
0.891
0.882
0.873
1
1.5
2
IOUT = 25 mA
VOUT(TARGET) = 0.9 V
400mV pin to GND; 50mV, 100mV
200mV, 800mV, 1.6V pins open
2.5
3 3.5 4 4.5
Input Voltage (V)
5
5.5
6
IOUT = 25 mA
VOUT(TARGET) = 3.5 V
200mV, 400mV, 800mV, 1.6V pins
to GND; 50mV, 100mV pins open
3.5
3.465
Y−axis scale is 1%Vout/div
6.5
5
5.5
6
Input Voltage (V)
G206
6.5
G207
Figure 10. Line Regulation (3.5 V, Fixed By Setting Pins)
Error in Actual Output Voltage (%)
1
3.2
Actual Output Voltage (V)
3.535
3.395
3.6
2.8
2.4
2
1.6
1.2
VIN = 4 V
IOUT = 50 mA
1.2
1.6
2
2.4
VOUT(TARGET) (V)
2.8
3.2
3.6
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
VIN = 4 V
IOUT = 50 mA
−0.8
−1
0.8
G020
Figure 11. Measured Output Voltage vs Pin-Setting
8
G007
3.43
Figure 9. Line Regulation (0.9 V, Fixed By Setting Pins)
0.8
0.8
6.5
Figure 8. Line Regulation (5 V, Adjustable)
0.927
− 40°C
0°C
25°C
85°C
105°C
125°C
IOUT = 25 mA
R1 = 271 kΩ, R2 = 30.1 kΩ
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1.2
1.6
2
2.4
VOUT(TARGET) (V)
2.8
3.2
3.6
G021
Figure 12. Accuracy vs Pin-Setting
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Typical Characteristics (continued)
At TJ = 25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩ pullup resistor, unless otherwise noted.
4
Ground Current (mA)
5
− 40°C
0°C
25°C
85°C
105°C
125°C
3
VIN = 1.8 V
VOUT(TARGET) = 1.5 V
200mV, 800mV pins to GND
50mV, 100mV, 200mV, 400mV
pins open
2
1
0
− 40°C
0°C
25°C
85°C
105°C
125°C
4
Ground Current (mA)
5
3
2
1
0
0.2
0.4
0.6
Output Current (A)
0.8
0
1
1
2.5
3 3.5 4 4.5
Input Voltage (V)
5
5.5
6
6.5
G033
Figure 14. GND Pin Current vs Input Voltage
VIN = 4 V
VOUT(TARGET) = 3.5 V
200mV, 400mV, 800mV, 1.6V pins to GND
50mV, 100mV pins open
EN = GND
50−Ω resistor between OUT and GND
Current Limit (A)
Shutdown Ground Current (µA)
3
2
3
− 40°C
0°C
25°C
85°C
105°C
125°C
4
1.5
G029
Figure 13. GND Pin Current vs Output Current
5
2
2
1
1
0
1
1.5
2
2.5
3 3.5 4 4.5
Input Voltage (V)
5
5.5
6
0
6.5
0.5
1
VIN=1.5V
VIN=6.5V
VOUT(TARGET) = 1.2 V
100mV, 200mV, 400mV pins to GND
50mV, 800mV, 1.6V pins open
50−Ω resistor between OUT and GND
1
1.5
2
2.5
Forced Output Voltage (V)
3
3.5
G040
Figure 16. Current Limit vs Output Voltage (Foldback)
VIN = 1.5 V, − 40 °C
VIN = 1.5 V, 25 °C
VIN = 1.5 V, 125 °C
VIN = 6.5 V, − 40 °C
VIN = 1.5 V, 25 °C
VIN = 1.5 V, 125 °C
0.8
PG Pin Voltage (V)
96
95
94
93
92
91
90
89
88
87
86
85
84
−50
0
G032
Figure 15. GND Pin Current In Shutdown vs Temperature
Threshould Voltage (%VOUT)
IOUT = 25 mA
VOUT(TARGET) = 0.9 V
400mV pin to GND; 50mV, 100mV
200mV, 800mV, 1.6V pins open
0.6
VOUT(TARGET) = 1.2 V
100mV, 200mV, 400mV
pins to GND
50mV, 800mV, 1.6V
pins open
50−Ω resistor
from OUT to GND
Spec limit defined at 1−mA.
0.4
0.2
−25
0
25
50
Temperature (°C)
75
100
125
0
0
0.5
1
1.5
Forced PG Pin Current (mA)
G050
Figure 17. Power-Good Threshold Voltage vs Temperature
2
G051
Figure 18. Power-Good Pin Drive Capability
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Typical Characteristics (continued)
10
Output Spectral Noise Density (µV/ Hz)
Output Spectral Noise Density (µV/ Hz)
At TJ = 25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩ pullup resistor, unless otherwise noted.
VOUT(TARGET) = 0.9 V
VOUT(TARGET) = 1.2 V
VOUT(TARGET) = 3.3 V
1
VIN = VOUT(TARGET) + 0.3 V
IOUT = 1 A
100 Hz to 100 kHz RMS Noise
0.9 V: 36.26 µVRMS
1.2 V: 39.57 µVRMS
3.3 V: 84.67 µVRMS
0.1
0.01
10
100
1k
Frequency (Hz)
10k
100k
10
VIN = 1.8 V, IOUT = 1 A
VOUT(TARGET) = 1.5 V
200mV, 800mV pins to GND
50mV, 100mV, 400mV, 1.6V pins open
1
CSS = 100nF, COUT = 100µF
CSS = 100nF, COUT = 10µF
CSS = 10nF, COUT = 100µF
CSS = 10nF, COUT = 10µF
CSS = 1nF, COUT = 100µF
CSS = 1nF, COUT = 10µF
0.1
0.01
10
100
1k
Frequency (Hz)
G060
Figure 19. Noise Spectral Density By Output Voltage
10k
100k
G063
Figure 20. Noise Spectral Density By External Capacitors
100
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
90
80
PSRR (dB)
70
60
50
40
30
VIN=3.6V, IOUT=100mA
VIN=3.6V, IOUT=1A
VIN=3.8V, IOUT=100mA
VIN=3.8V, IOUT=1A
20
10
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
G070
Figure 21. Power-Supply Ripple Rejection vs Frequency
10
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7 Detailed Description
7.1 Overview
The TPS7A7100 belongs to a family of new-generation LDO regulators that uses innovative circuitry to offer
very-low dropout voltage along with the flexibility of a programmable output voltage.
The dropout voltage for this LDO regulator family is 0.14 V at 1 A. This voltage is ideal for making the
TPS7A7100 into a point-of-load (POL) regulator because 0.14 V at 1 A is lower than any voltage gap among the
most common voltage rails: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V, and 3.3 V. This device offers a fully user-configurable
output voltage setting method. The TPS7A7100 output voltage can be programmed to any target value from
0.9 V to 3.5 V in 50-mV steps.
Another big advantage of using the TPS7A7100 is the wide range of available operating input voltages: from
1.5 V to 6.5 V. The TPS7A7100 also has very good line and load transient response. All these features allow the
TPS7A7100 to meet most voltage-regulator needs for under 6-V applications, using only one device so less time
is spent on inventory control.
Texas Instruments also offers different output current ratings with other family devices: the TPS7A7200 (2 A) and
TPS7A7300 (3 A).
7.2 Functional Block Diagram
Current
Limit
IN
Charge
Pump
SS
CSS
UVLO
0.5-V Reference
OUT
Thermal
Protection
PG
700-µs
Delay
1.2-V Reference
70 kΩ
Optional
0.45 V
50 kΩ
50 kΩ
SNS
3.2R
FB
Hysteresis
EN
32R
GND
50mV
16R
8R
4R
2R
100mV 200mV 400mV 800mV
1R
1.6V
NOTE: 32R = 1.024 MΩ (that is, 1R = 32 kΩ).
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7.3 Feature Description
7.3.1 User-Configurable Output Voltage
IN
IN
GND
OUT
OUT
Unlike traditional LDO devices, the TPS7A7100 comes with only one orderable part number; there is no
adjustable or fixed output voltage option. The output voltage of the TPS7A7100 is selectable in accordance with
the names given to the output voltage setting pins: 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, and 1.6 V. For
each pin connected to the ground, the output voltage setting increases by the value associated with that pin
name, starting from the value of the reference voltage of 0.5 V; floating the pins has no effect on the output
voltage. Figure 22 through Figure 27 show examples of how to program the output voltages.
OUT
IN
SNS
EN
FB
SS
CFF
NC
PG
Thermal Pad
1.6V
Optional
800mV
400mV
GND
200mV
100mV
50mV
VIN
FB
OUT
SNS
0.5 V
3.2R
CFF
FB
32R
16R
8R
4R
2R
1R
50mV
100mV
200mV
400mV
800mV
1.6V
VOUT = 0.9 V = 0.5 V + 400 mV
0.5 V is Vref
VOUT = 0.5 V ´ (1 + 3.2R/4R)
Figure 22. 0.9-V Configuration
12
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IN
IN
GND
OUT
OUT
Feature Description (continued)
OUT
IN
SNS
EN
FB
SS
CFF
NC
PG
Thermal Pad
1.6V
Optional
800mV
400mV
GND
200mV
100mV
50mV
VIN
FB
OUT
SNS
0.5 V
3.2R
CFF
FB
32R
16R
8R
4R
2R
1R
50mV
100mV
200mV
400mV
800mV
1.6V
VOUT = 1.2 V = 0.5 V + 100 mV + 200 mV + 400 mV
0.5 V is Vref
VOUT = 0.5 V ´ (1 + 3.2R/2.29R)
2.29R is parallel resistance of 16R, 8R, and 4R.
Figure 23. 1.2-V Configuration
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IN
IN
GND
OUT
OUT
Feature Description (continued)
OUT
IN
SNS
EN
FB
SS
CFF
NC
PG
Thermal Pad
1.6V
Optional
800mV
400mV
GND
200mV
100mV
50mV
VIN
FB
OUT
SNS
0.5 V
3.2R
CFF
FB
32R
16R
8R
4R
2R
1R
50mV
100mV
200mV
400mV
800mV
1.6V
VOUT = 1.8 V = 0.5 V + 100 mV + 400 mV + 800 mV
0.5 V is Vref
VOUT = 0.5 V ´ (1 + 3.2R/1.23R)
1.23R is parallel resistance of 16R, 4R, and 2R.
Figure 24. 1.8-V Configuration
14
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IN
IN
GND
OUT
OUT
Feature Description (continued)
OUT
IN
SNS
EN
FB
SS
CFF
NC
PG
Thermal Pad
1.6V
Optional
800mV
400mV
GND
200mV
100mV
50mV
VIN
FB
OUT
SNS
0.5 V
3.2R
CFF
FB
32R
16R
8R
4R
2R
1R
50mV
100mV
200mV
400mV
800mV
1.6V
VOUT = 2.5 V = 0.5 V + 400 mV + 1.6 V
0.5 V is Vref
VOUT = 0.5 V ´ (1 + 3.2R/0.8R)
0.8R is parallel resistance of 4R and 1R.
Figure 25. 2.5-V Configuration
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IN
IN
GND
OUT
OUT
Feature Description (continued)
OUT
IN
SNS
EN
FB
SS
CFF
NC
PG
Thermal Pad
1.6V
Optional
800mV
400mV
GND
200mV
100mV
50mV
VIN
FB
OUT
SNS
0.5 V
3.2R
CFF
FB
32R
16R
8R
4R
2R
1R
50mV
100mV
200mV
400mV
800mV
1.6V
VOUT = 3.3 V = 0.5 V + 400 mV + 800 mV + 1.6 V
0.5 V is Vref
VOUT = 0.5 V ´ (1 + 3.2R/0.571R)
0.571R is parallel resistance of 4R, 2R, and 1R.
Figure 26. 3.3-V Configuration
16
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IN
IN
GND
OUT
OUT
Feature Description (continued)
OUT
IN
SNS
EN
FB
SS
CFF
NC
PG
Thermal Pad
1.6V
Optional
800mV
400mV
GND
200mV
100mV
50mV
VIN
FB
OUT
SNS
0.5 V
3.2R
CFF
FB
32R
16R
8R
4R
2R
1R
50mV
100mV
200mV
400mV
800mV
1.6V
VOUT = 3.5 V = 0.5 V + 200 mV + 400 mV + 800 mV + 1.6 V
0.5 V is Vref
VOUT = 0.5 V ´ (1 + 3.2R/0.533R)
0.533R is parallel resistance of 8R, 4R, 2R, and 1R.
Figure 27. 3.5-V Configuration
See Table 1 for a full list of target output voltages and corresponding pin settings. The voltage setting pins have
a binary weight; therefore, the output voltage can be programmed to any value from 0.9 V to 3.5 V in 50-mV
steps.
Figure 11 and Figure 12 show this output voltage programming performance.
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Feature Description (continued)
SPACE
NOTE
Any output voltage setting that is not listed in Table 1 is not covered in Electrical
Characteristics. For output voltages greater than 3.5 V, use a traditional adjustable
configuration (see the Traditional Adjustable Configuration section).
Table 1. User Configurable Output Voltage Setting
18
VOUT(TARGET)
(V)
50 mV
100 mV
200 mV
400 mV
800 mV
1.6 V
VOUT(TARGET)
(V)
50 mV
100 mV
200 mV
400 mV
800 mV
1.6 V
0.9
open
open
open
GND
open
open
2.25
GND
GND
open
open
open
GND
0.95
GND
open
open
GND
open
open
2.3
open
open
GND
open
open
GND
1
open
GND
open
GND
open
open
2.35
GND
open
GND
open
open
GND
1.05
GND
GND
open
GND
open
open
2.4
open
GND
GND
open
open
GND
1.1
open
open
GND
GND
open
open
2.45
GND
GND
GND
open
open
GND
1.15
GND
open
GND
GND
open
open
2.5
open
open
open
GND
open
GND
1.2
open
GND
GND
GND
open
open
2.55
GND
open
open
GND
open
GND
1.25
GND
GND
GND
GND
open
open
2.6
open
GND
open
GND
open
GND
1.3
open
open
open
open
GND
open
2.65
GND
GND
open
GND
open
GND
1.35
GND
open
open
open
GND
open
2.7
open
open
GND
GND
open
GND
1.4
open
GND
open
open
GND
open
2.75
GND
open
GND
GND
open
GND
1.45
GND
GND
open
open
GND
open
2.8
open
GND
GND
GND
open
GND
1.5
open
open
GND
open
GND
open
2.85
GND
GND
GND
GND
open
GND
1.55
GND
open
GND
open
GND
open
2.9
open
open
open
open
GND
GND
1.6
open
GND
GND
open
GND
open
2.95
GND
open
open
open
GND
GND
1.65
GND
GND
GND
open
GND
open
3
open
GND
open
open
GND
GND
1.7
open
open
open
GND
GND
open
3.05
GND
GND
open
open
GND
GND
1.75
GND
open
open
GND
GND
open
3.1
open
open
GND
open
GND
GND
1.8
open
GND
open
GND
GND
open
3.15
GND
open
GND
open
GND
GND
1.85
GND
GND
open
GND
GND
open
3.2
open
GND
GND
open
GND
GND
1.9
open
open
GND
GND
GND
open
3.25
GND
GND
GND
open
GND
GND
1.95
GND
open
GND
GND
GND
open
3.3
open
open
open
GND
GND
GND
2
open
GND
GND
GND
GND
open
3.35
GND
open
open
GND
GND
GND
2.05
GND
GND
GND
GND
GND
open
3.4
open
GND
open
GND
GND
GND
2.1
open
open
open
open
open
GND
3.45
GND
GND
open
GND
GND
GND
2.15
GND
open
open
open
open
GND
3.5
open
open
GND
GND
GND
GND
2.2
open
GND
open
open
open
GND
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7.3.2 Traditional Adjustable Configuration
For any output voltage target that is not supported in the User-Configurable Output Voltage section, a traditional
adjustable configuration with external-feedback resistors can be used with the TPS7A7100. shows how to
configure the TPS7A7100 as an adjustable regulator with an equation and Table 2 lists recommended pairs of
feedback resistor values.
IN
IN
OUT
GND
OUT
NOTE
The bottom side of feedback resistor R2 in Figure 28 must be in the range of 27 kΩ to
33 kΩ to maintain the specified regulation accuracy.
CFF
OUT
IN
R1
SNS
EN
R2
FB
SS
NC
PG
Thermal Pad
1.6V
Optional
800mV
400mV
200mV
GND
100mV
50mV
VIN
FB
OUT
SNS
0.5 V
3.2R
CFF
FB
32R
16R
8R
4R
2R
1R
50mV
100mV
200mV
400mV
800mV
1.6V
R1
R2
VOUT =
(R1 + R2 )
R2
´ 0.500
Figure 28. Traditional Adjustable Configuration With External Resistors
Table 2. Recommended Feedback-Resistor Values
E96 SERIES
R40 SERIES
VOUT(TARGET)
(V)
R1 (kΩ)
R2 (kΩ)
R1 (kΩ)
R2 (kΩ)
1
30.1
30.1
30
30
1.2
39.2
28
43.7
31.5
1.5
61.9
30.9
60
30
1.8
80.6
30.9
80
30.7
1.9
86.6
30.9
87.5
31.5
2.5
115
28.7
112
28
3
147
29.4
150
30
3.3
165
29.4
175
31.5
5
280
30.9
243
27.2
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7.3.3 Undervoltage Lockout (UVLO)
The TPS7A7100 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is
operating properly. The UVLO circuit has a deglitch feature that typically ignores undershoot of the input voltage
upon the event of device start-up. Still, a poor input line impedance may cause a severe input voltage drop when
the device powers on. As explained in the Input Capacitor Requirements section, the input line impedance
should be well-designed.
7.3.4 Soft-Start
The TPS7A7100 has an SS pin that provides a soft-start (slow start) function.
By leaving the SS pin open, the TPS7A7100 performs a soft-start by its default setting.
As shown in Functional Block Diagram, by connecting a capacitor between the SS pin and the ground, the CSS
capacitor forms an RC pair together with the integrated 50-kΩ resistor. The RC pair operates as an RC-delay
circuit for the soft-start together with the internal 700-µs delay circuit.
The relationship between CSS and the soft-start time is shown in Figure 38 through Figure 40.
7.3.5 Current Limit
The TPS7A7100 internal current limit circuitry protects the regulator during fault conditions. During a current limit
event, the output sources a fixed amount of current that is mostly independent of the output voltage. The current
limit function is provided as a fail-safe mechanism and is not intended to be used regularly. Do not design any
applications to use this current limit function as a part of expected normal operation. Extended periods of current
limit operation degrade device reliability.
Powering on the device with the enable pin, or increasing the input voltage above the minimum operating voltage
while a low-impedance short exists on the output of the device, may result in a sequence of high-current pulses
from the input to the output of the device. The energy consumed by the device is minimal during these events;
therefore, there is no failure risk. Additional input capacitance helps to mitigate the load transient requirement of
the upstream supply during these events.
7.3.6 Enable
The EN pin switches the enable and disable (shutdown) states of the TPS7A7100. A logic high input at the EN
pin enables the device; a logic low input disables the device. When disabled, the device current consumption is
reduced.
7.3.7 Power Good
The TPS7A7100 has a power good function that works with the PG output pin. When the output voltage
undershoots the threshold voltage VIT(PG) during normal operation, the PG open-drain output turns from a highimpedance state to a low-impedance state. When the output voltage exceeds the VIT(PG) threshold by an amount
greater than the PG hysteresis, Vhys(PG), the PG open-drain output turns from a low-impedance state to highimpedance state. By connecting a pullup resistor (usually between OUT and PG pins), any downstream device
can receive an active-high enable logic signal.
When setting the output voltage to less than 1.8 V and using a pullup resistor between OUT and PG pins,
depending on the downstream device specifications, the downstream device may not accept the PG output as a
valid high-level logic voltage. In such cases, place a pullup resistor between IN and PG pins, not between OUT
and PG pins.
Figure 18 shows the open-drain output drive capability. The on-resistance of the open-drain transistor is
calculated using Figure 18, and is approximately 200 Ω. Any pullup resistor greater than 10 kΩ works fine for this
purpose.
20
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(MIN).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device (such as a bipolar junction transistor, or BJT) is in
saturation and no longer controls the current through the LDO. Line or load transients in dropout can result in
large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 3 lists the conditions that lead to the different modes of operation.
Table 3. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(NOM) + VDO
and VIN > VIN(MIN)
VEN > VIH(EN)
IOUT < I(LIM)
TJ < 125°C
Dropout mode
VIN < VOUT(NOM) + VDO
VEN > VIH(EN)
—
TJ < 125°C
—
VEN < VIL(EN)
—
TJ > 160°C
Disabled mode (any true
condition disables the
device)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A7100 is a very-low dropout LDO with very fast load transient response. The TPS7A7100 provides a
number of features such as a power good signal for output monitoring, a soft-start pin to reduce inrush currents
during start-up, and it is suitable for applications that require up to 1 A of output current.
8.2 Typical Application
1.5 V
IN
PG
CIN
TPS7A7100
EN
SS
CSS
1.2 V = 0.5 Vref
+ 100 mV
COUT + 200 mV
+ 400 mV
OUT
SNS
CFF
FB
Optional
GND
50mV
100mV
1.6V
200mV 400mV 800mV
Figure 29. 1.2-V Output Using ANY-OUT Pins
8.2.1 Design Requirements
Table 4 lists the design parameters for this example.
Table 4. Design Parameters
22
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
1.425 V to 6.5 V
Output voltage
1.2 V
Output current rating
1A
Output capacitor range
4.7 µF to 200 µF
feedforward capacitor range
220 pF to 100 nF
Soft-Start capacitor range
0 to 1 µF
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8.2.2 Detailed Design Procedures
8.2.2.1 ANY-OUT Programmable Output Voltage
For ANY-OUT operation, the TPS7A7001 does not use any external resistors to set the output voltage, but uses
device pins labeled 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, and 1.6 V to set the regulated output voltage.
Each pin is either connected to ground (active) or is left open (floating). The ANY-OUT programming is set as the
sum of the internal reference voltage (V(SS) = 0.5 V) plus the sum of the respective voltages assigned to each
active pin. By leaving all ANY-OUT pins open, or floating, the output will be set to the minimum possible output
voltage equal to V(SS). By grounding all of the ANY-OUT pins the output will be set to 3.65 V.
When using the ANY-OUT pins, the SNS pin must always be connected between the OUT and FB pins.
However, the feedforward capacitor must be connected to the FB pin, not the SNS pin.
8.2.2.2 Traditional Adjustable Output Voltage
For applications that need the regulated output voltage to be greater than 3.65 V (or those that require more
resolution than the 50 mV that the ANY-OUT pins provide), the TPS7A7100 can also be use the traditional
adjustable method of setting the regulated output.
When using the traditional method of setting the output, the FB pin should be connected to the node connecting
the top and bottom resistors of the resistor divider. The SNS pin should be left floating.
8.2.2.3 Input Capacitor Requirements
As a result of its very fast transient response and low-dropout operation support, it is necessary to reduce the
line impedance at the input pin of the TPS7A7100. The line impedance depends heavily on various factors, such
as wire (PCB trace) resistance, wire inductance, and output impedance of the upstream voltage supply (power
supply to the TPS7A7100). Therefore, a specific value for the input capacitance cannot be recommended until
the previously listed factors are finalized.
In addition, simple usage of large input capacitance can form an unwanted LC resonance in combination with
input wire inductance. For example, a 5-nH inductor and a 10-µF input capacitor form an LC filter that has a
resonance at 712 kHz. This value of 712 kHz is well inside the bandwidth of the TPS7A7100 control loop.
The best guideline is to use a capacitor of up to 1 µF with well-designed wire connections (PCB layout) to the
upstream supply. If it is difficult to optimize the input line, use a large tantalum capacitor in combination with a
good-quality, low-ESR, 1-µF ceramic capacitor.
8.2.2.4 Output Capacitor Requirements
The TPS7A7100 is designed to be stable with standard ceramic capacitors with capacitance values from 4.7 μF
to 47 μF without a feedforward capacitor. For output capacitors from 47 uF to 200 uF a feedforward capacitor of
at least 220 pF must be used. The TPS7A7100 is evaluated using an X5R-type, 10-μF ceramic capacitor. TI
highly recommends the X5R- and X7R-type capacitors because they have minimal variation in value and ESR
over temperature. Maximum ESR must be less than 1 Ω.
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude,
but increases duration of the transient response.
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8.2.3 Application Curves
1.2
3
2
Output Voltage
1.1
1
4
Output Current Slew Rate: 1A/µs
VOUT(TARGET)=3.3V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
3.4
3.3
2
Output Voltage
3.2
1
Output
Current
Output
Current
1
0
3.1
Time (100µs/div)
Time (100µs/div)
Voltage (V)
VIN
4
Voltage (V)
IOUT=1A,
VOUT(TARGET)=3.3V
400mV, 800mV, 1.6V
pins to GND
50mV, 100mV, 200mV
pins open
3.8
3.6
VOUT
3.4
3.2
Time (20 µs/div)
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
4.5
VIN
4
4
VIN
Voltage (V)
3.5
3
2.5
VOUT
2
IN = EN
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
IN = EN
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
3
2.5
2
VOUT
1.5
1
0.5
0
0
Time (1 ms/div)
G302
Figure 34. Turnon Response (IN = EN)
24
G301
5
3.5
Voltage (V)
VOUT
Figure 33. Power Up and Power Down (IN = EN)
4.5
0.5
VIN
Time (2 ms/div)
5
1
VOUT(TARGET)=3.3V
400mV, 800mV,
1.6V pins to GND
50mV, 100mV,
200mV pins open
50−Ω resistor between
OUT and GND
G300
Figure 32. Line Transient Response
1.5
G316
Figure 31. Load Transient Response (VOUT = 3.3 V)
4.6
4.2
0
G313
Figure 30. Load Transient Response (VOUT = 1.2 V)
4.4
3
Output Current (A)
1.3
3.5
Output Voltage (V)
4
Output Current Slew Rate: 1A/µs
VOUT(TARGET)=1.2V
100mV, 200mV, 400mV pins to GND
50mV, 800mV, 1.6V pins open
Output Current (A)
Output Voltage (V)
1.4
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Time (1 ms/div)
G303
Figure 35. Turnoff Response (IN = EN)
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5
5
4.5
4.5
VOUT
VIN
4
3.5
3
Voltage (V)
Voltage (V)
3.5
VEN
2.5
2
1.5
0.5
3
2
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
1
0
Time (1 ms/div)
Time (1 ms/div)
G304
Figure 36. EN Pulse On Response (Over Stable VIN)
G305
Figure 37. EN Pulse Off Response (Over Stable VIN)
5
5
VOUT (CSS=0F)
4.5
VIN
VOUT(TARGET) = 3.3 V
50−Ω resistor from OUT to GND
4.5
4
VIN
VOUT (CSS=0F)
3.5
Voltage (V)
3.5
Voltage (V)
VEN
0.5
0
3
2.5
VOUT
2.5
1.5
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
1
4
VIN
4
VEN
VOUT (CSS=10nF)
2
VOUT (CSS=100nF)
1.5
3
2.5
VOUT (CSS=10nF)
VEN
VOUT (CSS=100nF)
2
1.5
1
VOUT (CSS=1µF)
1
VOUT (CSS=1µF)
0.5
VOUT(TARGET) = 3.3 V
50−Ω resistor from OUT to GND
0.5
0
0
Time (5 ms/div)
Time (50 ms/div)
G306
Figure 38. Soft-Start Delay vs CSS (Enlarged View)
G307
Figure 39. Soft-Start Delay vs CSS (Reduced View)
Softstart Delay (ms)
1000
0%VOUT to 90%VOUT
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
100
10
1
0.1
1
10
100
CSS (nF)
1000
G308
Figure 40. Soft-Start Delay vs CSS
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9 Power Supply Recommendations
This device is designed for operation from an input voltage supply ranging from 1.425 V to 6.5 V. This input
supply must be well regulated. The TPS7A7100 family of fast-transient, low-dropout linear regulators achieve
stability with a minimum output capacitance of 4.7 μF; however, TI recommends using 10-μF ceramic capacitors
for both the input and output to maximize AC performance.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing
the board with separate ground planes for IN and OUT, with each ground plane connected only at the GND
pin of the device.
In addition, the ground connection for the output capacitor must connect directly to the GND pin of the device.
Equivalent series inductance (ESL) and ESR must be minimized to maximize performance and ensure
stability.
Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the
regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed.
The use of vias and long traces is strongly discouraged because they may impact system performance
negatively and even cause instability.
If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout
pattern used for TPS7A7100 evaluation board, available at www.ti.com.
10.2 Layout Example
100mV
200mV
GND
1.6V
50mV
NC
PG
Thermal
Pad
EN
CIN
R1
OUT
OUT
OUT
IN
IN
SNS
IN
R2
FB
SS
GND
CSS
400mV
800mV
Ground
Input
Output
COUT
Notes: Cin and Cout are 0805 packages
CSS, R1, and R2 are 0402 packages
R1 and R2 only needed for adjustable operation
Denotes a via to a connection made on another layer
Figure 41. TPS7A7100 Recommended Layout
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10.3 Thermal Considerations
The thermal protection feature disables the output when the junction temperature rises to approximately 160°C,
allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal-protection
circuit may cycle on and off. This thermal limit protects the device from damage as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your particular application. This
configuration produces a worst-case junction temperature of 125°C at the highest-expected ambient temperature
and worst-case load.
The internal-protection circuitry of the TPS7A7100 has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS7A7100 into thermal shutdown
degrades device reliability.
10.4 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using
Equation 1:
PD
VIN VOUT u IOUT
(1)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the VQFN (RGW or RGT) package, the primary conduction path for heat is through the exposed pad to the
PCB. The pad can be connected to ground or be left floating; however, it should be attached to an appropriate
amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal
resistance depends on the maximum ambient temperature, maximum device junction temperature, and power
dissipation of the device and can be calculated using Equation 2:
RqJA =
+125°C - TA
PD
(2)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 42.
120
θJA(RGW)
θJA(RGT)
100
θJA (°C/W)
80
60
40
20
0
0
1
2
3
4
5
6
7
Board Copper Area (inch2)
8
9
10
G800
Figure 42. θJA vs Board Size
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Power Dissipation (continued)
Figure 42 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effects of heat spreading in the ground plane and must not be used to estimate
actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, TI strongly recommends using ΨJT
and ΨJB, as explained in the Estimating Junction Temperature section.
10.5 Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with corresponding formulas (given in Equation 3). For backwards compatibility, an older θJC,Top
parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
Where:
PD is the power dissipation shown by Equation 2.
TT is the temperature at the center-top of the IC package.
TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (see
Figure 43).
(3)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see Application Report SBVA025, Using New Thermal Metrics,
available for download at www.ti.com.
TB on PCB
TT on top of IC
1mm
(a) Example RGW (QFN) Package Measurement
Figure 43. Measuring Points For TT And TB
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Estimating Junction Temperature (continued)
By looking at Figure 44, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 3 is a good way to estimate TJ by simply measuring TT or TB, regardless of the
application board size.
25
ψJB(RGT)
ψJT and ψJB (°C/W)
20
15
ψJB(RGW)
10
5
0
ψJT(RGT)
0
1
2
ψJT(RGW)
3
4
5
6
7
Board Copper Area (inch2)
8
9
10
G801
Figure 44. ΨJT And ΨJB vs Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
see Application Report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further
information, see Application Report SPRA953, IC Package Thermal Metrics, also available on the TI website.
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11 Device And Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator, SBVA042.
• Using New Thermal Metrics, SBVA025.
• Semiconductor and IC Package Thermal Metrics, SPRA953.
11.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
DSP, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, And Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
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11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS7A7100RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PYLQ
Samples
TPS7A7100RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PYLQ
Samples
TPS7A7100RGWR
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SBS
Samples
TPS7A7100RGWT
ACTIVE
VQFN
RGW
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SBS
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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