TPS7B86-Q1
SBVS362C – JUNE 2020 – REVISED AUGUST 2022
TPS7B86-Q1 Automotive, 500-mA, 40-V, Adjustable, Low-Dropout Regulator
With Power-Good
1 Features
3 Description
•
The TPS7B86-Q1 is a low-dropout linear regulator
designed to connect to the battery in automotive
applications. The device has an input voltage range
extending to 40 V, which allows the device to
withstand transients (such as load dumps) that are
anticipated in automotive systems. With only a 17µA quiescent current at light loads, the device is an
optimal solution for powering always-on components
such as microcontrollers (MCUs) and controller area
network (CAN) transceivers in standby systems.
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
– Junction temperature: –40°C to +150°C, TJ
Input voltage range: 3 V to 40 V (42 V max)
Output voltage range:
– Adjustable output: 1.2 V to 18 V
– Fixed 3.3-V and 5-V output
Maximum output current: 500 mA
Output voltage accuracy: ±0.85% (max)
Low dropout voltage:
– 475 mV (max) at 450 mA (VOUT ≥ 3.3 V)
Low quiescent current:
– 17 μA (typ) at light loads
– 5 μA (max) when disabled
Excellent line transient response:
– ±2% VOUT deviation during cold-crank
– ±2% VOUT deviation (1-V/µs VIN slew rate)
Power-good with programmable delay period
Stable with a 2.2-µF or larger capacitor
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Package options:
– 5-pin TO-252 package: 29.7°C/W RθJA
– 8-pin HSOIC-8 package with thermal pad:
41.8°C/W RθJA
The device has state-of-the-art transient response
that allows the output to quickly react to changes
in load or line (for example, during cold-crank
conditions). Additionally, the device has a novel
architecture that minimizes output overshoot when
recovering from dropout. During normal operation, the
device has a tight DC accuracy of ±0.85% over line,
load, and temperature.
The power-good delay can be adjusted by external
components, allowing the delay time to be configured
to fit application-specific systems.
The device is available in thermally conductive
packaging to allow the device components to
efficiently transfer heat to the circuit board.
Package Information (1)
PART NUMBER
2 Applications
Reconfigurable instrument clusters
Body control modules (BCM)
Always-on battery-connected applications:
– Automotive gateways
– Remote keyless entries (RKE)
40
0.25
VIN
VOUT 0.2
35
0.15
30
0.1
25
0.05
20
0
15
-0.05
10
-0.1
5
TPS7B86-Q1
(1)
BODY SIZE (NOM)
DDA (HSOIC, 8)
4.89 mm × 3.90 mm
KVU (TO-252, 5)
6.60 mm × 6.10 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
OUT
IN
R1
Output Voltage (V)
45
Input Voltage (V)
•
•
•
PACKAGE
EN
TPS7B86-Q1
(Adjustable)
FB
R2
GND
-0.15
0
0
500
1000
1500
Time (Ps)
2000
2500
-0.2
3000
Line Transient Response (3-V/µs VIN Slew Rate)
Adjustable Output Voltage
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7B86-Q1
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SBVS362C – JUNE 2020 – REVISED AUGUST 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Switching Characteristics............................................8
6.7 Typical Characteristics................................................ 9
7 Detailed Description......................................................16
7.1 Overview................................................................... 16
7.2 Functional Block Diagrams ...................................... 16
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................20
8 Application and Implementation.................................. 21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 26
8.3 Power Supply Recommendations.............................27
8.4 Layout....................................................................... 27
9 Device and Documentation Support............................30
9.1 Device Support......................................................... 30
9.2 Receiving Notification of Documentation Updates....30
9.3 Support Resources................................................... 30
9.4 Trademarks............................................................... 30
9.5 Electrostatic Discharge Caution................................30
9.6 Glossary....................................................................30
10 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2022) to Revision C (August 2022)
Page
• Changed Pin Configuration and Functions section: added D version of DDA pinout and added B version to
existing DDA Package (With PG) pinout............................................................................................................ 3
• Changed Power-Good (PG) section................................................................................................................. 18
• Added D version information to Device Nomenclature table............................................................................ 30
Changes from Revision A (December 2020) to Revision B (May 2022)
Page
• Added Functional Safety-Capable bullets to Features section........................................................................... 1
• Changed PG pin description in Pin Functions table........................................................................................... 3
• Adding load regulation specification for the B version........................................................................................ 7
• Changed Start-Up Plot Inrush Current figure......................................................................................................9
• Changed TPS7B86-Q1 With PG figure............................................................................................................ 16
• Changed Power-Up Waveform With EN figure.................................................................................................27
2
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5 Pin Configuration and Functions
Thermal
3
4
FB/NC
5
2
EN
GND
1
Pad
VO
VI
Not to scale
Figure 5-1. KVU Package, 5-Pin TO-252 (Top View)
OUT
1
FB/NC
2
8
IN
7
EN
OUT
1
FB/NC
2
Thermal
Pad
8
IN
7
EN
Thermal
Pad
NC
3
6
NC
NC
4
5
GND
Figure 5-2. DDA Package (Without PG),
8-Pin HSOIC (Top View)
OUT
1
FB/NC
2
DELAY
3
6
PG
NC
4
5
GND
Figure 5-3. DDA Package (With PG),
8-Pin HSOIC, B Version (Top View)
8
IN
7
NC
Thermal
Pad
DELAY
3
6
EN
GND
4
5
PG
Figure 5-4. DDA Package (With PG),
8-Pin HSOIC, D Version (Top View)
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Table 5-1. Pin Functions
PIN
NAME
DELAY
EN
—
2
DDA
DDA (B
(Without
Version)
PG)
—
7
3
7
DDA (D
Version)
3
6
TYPE
DESCRIPTION
O
Power-good delay adjustment pin. Connect a capacitor from this pin
to GND to set the PG reset delay. Leave this pin floating for a
default (t(DLY_FIX)) delay. See the Power-Good (PG) section for more
information. If this functionality is not desired, leave this pin floating
because connecting this pin to GND causes a permanent increase in
the GND current.
I
Enable pin. The device is disabled when the enable pin becomes lower
than the enable logic input low level (VIL). Do not leave this pin floating
because this pin is high impedance. If left floating, this pin may cause
the device to enable or disable.
FB/NC
4
2
2
2
I
This pin is a feedback pin when using an external resistor divider or an
NC pin when using the device with a fixed output voltage. When using
the adjustable device, this pin must be connected through a resistor
divider to the output for the device to function. If using a fixed output this
pin can either be left floating or connected to GND.
GND
3
5
5
4
G
Ground pin. Connect this pin to the thermal pad with a low-impedance
connection.
IN
1
8
8
8
P
Input power-supply voltage pin. For best transient response and to
minimize input impedance, use the recommended value or larger
ceramic capacitor from IN to GND as listed in the Recommended
Operating Conditions table and the Input Capacitor section. Place the
input capacitor as close to the input of the device as possible.
NC
—
3, 4, 6
4
7
—
No internal connection. This pin can be left floating or tied to GND for
best thermal performance.
OUT
5
1
1
1
O
Regulated output voltage pin. A capacitor is required from OUT
to GND for stability. For best transient response, use the nominal
recommended value or larger ceramic capacitor from OUT to GND;
see the Recommended Operating Conditions table and the Output
Capacitor section. Place the output capacitor as close to output of the
device as possible. If using a high equivalent series resistance (ESR)
capacitor, decouple the output with a 100-nF ceramic capacitor.
PG
—
—
6
5
O
Active-high, power-good pin. An open-drain output indicates when
the output voltage reaches VPG(TH,RISING) of the target. Using a feedforward capacitor can disrupt PG (power good) functionality. See the
Power-Good (PG) section for more information.
Pad
Pad
Pad
Pad
—
Thermal pad. Connect the pad to GND for best possible thermal
performance. See the Layout section for more information.
Thermal
pad
4
KVU
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VIN
Unregulated input
–0.3
42
V
EN
Enable input
–0.3
42
V
VOUT
Regulated output
–0.3
VIN + 0.3 V(2)
V
FB
Feedback
–0.3
20
V
Delay
Reset delay input, power-good adjustable threshold
–0.3
6
V
PG
Power-good output
–0.3
20
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
UNIT
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.
The absolute maximum rating is VIN + 0.3 V or 20 V, whichever is smaller
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VOUT
TYP
MAX
UNIT
3
40
Output voltage
1.2
18
V
IOUT
Output current
0
500
mA
FEN
Enable pin frequency(1)
5
kHz
VEN
Enable Pin voltage
0
40
V
VDelay
Delay pin voltage, power-good adjustable threshold
0
5.5
V
VPG
Power-good output pin
0
18
V
CFF
Feed-forward capacitor
0
1
µF
COUT
Output capacitor(3)
2.2
220
µF
ESR
Output capacitor ESR requirements
CIN
Input capacitor(2)
CDelay
Power-good delay capacitor
TJ
Operating junction temperature
(1)
(2)
(3)
0.001
0.1
V
2
Ω
1
µF
–40
1
µF
150
°C
Minimum pulse time on the EN pin is 100 µs.
For robust EMI performance the minimum input capacitance is 500 nF.
Effective output capacitance of 1 µF minimum required for stability.
6.4 Thermal Information
TPS7B86-Q1
THERMAL METRIC(1) (2)
DDA
5 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
29.7
41.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40.2
55
°C/W
RθJB
Junction-to-board thermal resistance
8.6
17.3
°C/W
ψJT
Junction-to-top characterization parameter
2.9
4.5
°C/W
ψJB
Junction-to-board characterization parameter
8.5
17.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
5.7
°C/W
(1)
(2)
6
KVU
The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper.
The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated.
For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application
report.
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6.5 Electrical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
Test Conditions
MIN
VOUT
ΔVOUT(ΔIOUT)
Regulated output (DDA package)
Regulated output (KVU Package)
Load regulation (B Version)
MAX
–0.75
0.75
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA, TJ = 25ºC(1)
–0.75
0.75
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA(1)
–0.85
0.85
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA(1)
–0.85
0.85
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA, TJ = 25ºC(1)
–0.85
0.85
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA, TJ = 25ºC(1)
–0.85
0.85
mA(1)
–1.15
1.15
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 500 mA(1)
–1.15
1.15
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450 mA, TJ =
VOUT
TYP
25ºC(1)
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA to 450
UNIT
%
%
VIN = VOUT + 1 V, IOUT = 100 µA to 450 mA , VOUT ≥ 3.3 V
0.45
%
VIN = VOUT + 1 V, IOUT = 100 µA to 500 mA , VOUT ≥ 3.3 V
0.475
%
VIN = VOUT + 1 V, IOUT = 100 µA to 450 mA , VOUT ≥ 3.3 V
0.425
VIN = VOUT + 1 V, IOUT = 100 µA to 500 mA , VOUT ≥ 3.3 V
0.45
ΔVOUT(ΔIOUT)
Load regulation
ΔVOUT(ΔIOUT)
Load regulation (adjustable output
only)
VIN = VOUT + 1 V, IOUT = 100 µA to 450 mA , VOUT < 3.3 V
0.625
VIN = VOUT + 1 V, IOUT = 100 µA to 500 mA , VOUT < 3.3 V
0.65
ΔVOUT(ΔVIN)
Line regulation
VIN = VOUT + 1 V to 40 V, IOUT = 100 µA
0.2
%
ΔVOUT
Load transient response settling
time(2)
tR = tF = 1 µs; COUT = 10 µF, VOUT ≥ 3.3V
100
µs
ΔVOUT
Load transient response overshoot, tR = tF = 1 µs; COUT = 10 µF,
undershoot(2)
VOUT ≥ 3.3V
10%
%VOUT
10%
%VOUT
ΔVOUT
Load transient response overshoot, tR = tF = 1 µs; COUT = 10 µF,
undershoot(2)
VOUT < 3.3V
IOUT = 150 mA to 350 mA
IOUT = 0 mA to 500 mA
–10%
IOUT = 150 mA to 350 mA
–2.5%
IOUT = 350 mA to 150 mA
–10%
VIN = VOUT + 1 V to 40V, IOUT = 0 mA, TJ = 25ºC(3)
IQ
Quiescent current
ISHUTDOWN
Shutdown supply current (IGND)
VDO
Dropout voltage fixed output
voltages (DDA Package)
17
26
IOUT = 500 µA
35
VEN = 0 V, TJ = 25ºC
2.5
VEN = 0 V
4
260
360
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
335
475
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
360
535
Dropout voltage fixed output
voltages (KVU Package)
µA
mV
43
IOUT = 315 mA, VFB = 0.61 V, VIN = 3 V
400
IOUT = 450 mA, VFB = 0.61 V, VIN = 3 V
525
IOUT = 500 mA, VFB = 0.61 V, VIN = 3 V
570
IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
VDO
µA
43
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
IOUT ≤ 1 mA, VFB = 0.61 V, VIN = 3 V
Dropout voltage adjustable output
21
VIN = VOUT + 1 V to 40 V, IOUT = 0 mA(3)
IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
VDO
%
–2%
IOUT = 350 mA to 150 mA
IOUT = 0 mA to 500 mA
%
mV
46
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
275
400
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
360
525
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
390
575
46
mV
IOUT = 315 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
327
440
mV
IOUT = 450 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
428
575
mV
464
630
mV
0.65
0.656
V
10
nA
50
nA
2.82
V
IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95
VDO
Dropout voltage adjustable output
voltages (KVU Package)
VFB
Feedback voltage
Reference voltage for FB
IFB
Feedback current
Current into FB pin
IEN
EN pin current
VEN = VIN = 13.5 V
VUVLO(RISING)
Rising input supply UVLO
VIN rising
IOUT = 500 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM)
0.644
-10
2.6
2.7
mV
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6.5 Electrical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
Test Conditions
MIN
2.5
2.6
UNIT
Falling input supply UVLO
VUVLO(HYST)
V UVLO(IN) hysteresis
VIL
Enable logic input low level
VIH
Enable logic input high level
ICL
Output current limit
VIN = VOUT + 1 V, VOUT short to 90% x VOUT(NOM)
PSRR
Power supply rejection ratio
VIN - VOUT = 1 V, frequency = 1 kHz, IOUT = 450 mA
VPG(OL)
PG pin low level output voltage
VOUT ≤ 0.83 x VOUT
VPG(TH,RISING)
Default power-good threshold
VOUT rising
85
VPG(TH,FALLING)
Default power-good threshold
VOUT falling
83
VPG(HYST)
Power-good hysteresis
VDLY(TH)
Threshold to release power-good
high
Voltage at DELAY pin rising
IDLY(CHARGE)
Delay capacitor charging current
Voltage at DELAY pin = 1 V
TJ
Junction temperature
TSD(SHUTDOWN)
Junction shutdown temperature
175
°C
TSD(HYST)
Hysteresis of thermal shutdown
20
°C
(2)
(3)
2.38
MAX
VUVLO(FALLING)
(1)
VIN falling
TYP
230
V
mV
0.7
V
780
mA
2
V
540
70
dB
0.4
V
95
93
%VOUT
2
1.17
1.21
1
1.5
–40
1.25
V
2
µA
150
°C
Power dissipation is limited to 2 W for device production testing purposes. The power dissipation can be higher during normal
operation. See the thermal dissipation section for more information on how much power the device can dissipate while maintaining a
junction temperature below 150℃.
Specified by design.
For the adjustable output this is tested in unity gain and resistor current is not included.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
Power-good propagation delay
No capacitor connect at DELAY pin
100
µs
t(Deglitch)
Power-good deglitch time
No capacitor connect at DELAY pin
90
µs
Power-good propagation delay
Delay capacitor value:
C(DELAY) = 100 nF
80
ms
t(DLY)
8
TEST CONDITIONS
t(DLY_FIX)
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6.7 Typical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 μA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted)
5.015
0.3
500 mA
100 PA
0.25
0.2
0.15
0qC
25qC
85qC
125qC
150qC
5.005
Output Voltage (V)
Accuracy (%)
-55qC
-40qC
5.01
0.1
0.05
0
-0.05
-0.1
-0.15
5
4.995
4.99
4.985
-0.2
4.98
-0.25
-0.3
-60
-40
-20
0
20
40
60
80
Temperature qC
4.975
100 120 140 160
5
10
15
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 150 mA
Figure 6-1. Accuracy vs Temperature
Figure 6-2. Line Regulation vs VIN
5.015
5.015
-55qC
-40qC
5.01
0qC
25qC
85qC
125qC
150qC
5
4.995
4.99
85qC
125qC
150qC
5
4.995
4.99
4.985
4.985
4.98
4.98
4.975
4.975
5
10
15
20
25
Input Voltage (V)
30
35
40
5
10
15
VOUT = 5 V, IOUT = 5 mA
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V, IOUT = 1 mA
Figure 6-3. Line Regulation vs VIN
Figure 6-4. Line Regulation vs VIN
5.015
5.01
-55qC
-40qC
5.01
0qC
25qC
85qC
125qC
150qC
-40 qC
25 qC
85 qC
5.0075
5.005
5.005
Output Voltage (V)
Output Voltage (V)
0qC
25qC
5.005
Output Voltage (V)
5.005
Output Voltage (V)
-55qC
-40qC
5.01
5
4.995
4.99
5.0025
5
4.9975
4.985
4.995
4.98
4.9925
4.975
0
25
50
75
100
Output Current (mA)
125
150
4.99
0
5
VOUT = 5 V
10
15
20
25
Input Voltage (V)
30
35
40
COUT = 10 µF, VOUT = 5 V
Figure 6-5. Load Regulation vs IOUT
Figure 6-6. Line Regulation at 50 mA
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 μA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted)
5.01
550
-40 qC
25 qC
85 qC
5.0075
450
Dropout Voltage (mV)
5.005
Output Voltage (V)
-55 qC
-40 qC
0 qC
500
5.0025
5
4.9975
4.995
25 qC
85 qC
125 qC
150 qC
400
350
300
250
200
150
100
4.9925
50
0
4.99
0
5
10
15
20
25
Input Voltage (V)
30
35
0
40
50
100
150
200 250 300 350
Output Current (mA)
500
550
-55 qC
-40 qC
0 qC
500
25 qC
85 qC
125 qC
150 qC
450
Dropout Voltage (mV)
450
Dropout Voltage (mV)
500
Figure 6-8. Dropout Voltage (VDO) vs IOUT
Figure 6-7. Line Regulation at 100 mA
400
350
300
250
200
150
100
400
350
300
250
200
-55qC
-40qC
50
0qC
25qC
85qC
125qC
150qC
150
0
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
2
500
4
90
10
12
14
Input Voltage (V)
16
18
20
10
5
80
70
Noise (PV/—Hz)
60
50
40
30
20
0
10
8
Figure 6-10. Dropout Voltage (VDO) vs VIN
Figure 6-9. Dropout Voltage (VDO) vs IOUT
10
6
IOUT = 450 mA
VIN = 20 V
Power Supply Rejection Ratio (dB)
450
VIN = 3 V
COUT = 10 µF, VOUT = 5 V
1 mA
10 mA
100
50 mA
150 mA
1k
350 mA
500 mA
10k
100k
Frequency (Hz)
1M
10M
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10
COUT = 10 µF (X7R 50 V), VOUT = 5 V
Figure 6-11. PSRR vs Frequency and IOUT
10
400
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IOUT
10 mA, 364.8 PVRMS
150 mA, 391.4 PVRMS
500 mA, 437.2 PVRMS
100
1k
10k
100k
Frequency (Hz)
1M
10M
COUT = 10 µF (X7R 50 V), VOUT = 5 V
Figure 6-12. Noise vs Frequency
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 μA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted)
80
Power Supply Rejection Ratio (dB)
2
1
0.5
0.2
0.1
0.05
IOUT
10 mA, 252.5 PVRMS
150 mA, 267.6 PVRMS
500 mA, 293.8 PVRMS
0.002
0.001
10
100
1k
60
50
40
30
20
10
6 V VIN
10k
100k
Frequency (Hz)
1M
0
10
10M
0.15
30
0.1
25
0.05
20
0
15
-0.05
10
5
0
1500
Time (Ps)
2000
300
VIN
VOUT 240
6
180
4
120
2
60
0
0
-60
-4
-120
-0.1
-6
-180
-0.15
-8
-240
-10
-300
500
0
50
100
300
-40qC
25qC
150qC
IOUT
0
0
-50
-100
-100
-200
-150
-300
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
Figure 6-17. Load Transient, No Load to 100 mA
AC Coupled Output Voltage (mV)
200
100
350
400
450
150
300
-40qC
50
0.5
200 250 300
Time (Ps)
Figure 6-16. Line Transients
Output Current (mA)
AC Coupled Output Voltage (mV)
150
150
VOUT = 5 V, IOUT = 100 mA, VIN = 5.5 V to 6.5 V,
rise time = 1 µs, VEN = 3.3 V
Figure 6-15. Line Transients
0
10M
8
VOUT = 5 V, IOUT = 1 mA, VIN = 13.5 V to 45 V,
slew rate = 2.7 V/µs, VEN = 3.3 V
100
1M
-2
-0.2
3000
2500
Input Voltage (V)
35
1000
10k
100k
Frequency (Hz)
10
Output Voltage (V)
Input Voltage (V)
40
0.25
VIN
VOUT 0.2
500
1k
13.5 V VIN
Figure 6-14. PSRR vs Frequency and VIN
Figure 6-13. Noise vs Frequency
0
100
10 VIN
COUT = 10 µF (X7R 50 V), IOUT = 500 mA, VOUT = 5 V
COUT = 10 µF (X7R 50 V), VOUT = 3.3 V
45
7 V VIN
AC Coupled Output Voltage (mV)
0.02
0.01
0.005
70
25qC
150qC
IOUT
100
200
50
100
0
0
-50
-100
-100
-200
-150
0
20
40
60
80
100 120
Time (Ps)
140
160
180
Output Current (mA)
Noise (PV/—Hz)
10
5
-300
200
VOUT = 5 V, IOUT = 0 mA to 100 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
Figure 6-18. Load Transient, No Load to 100-mA Rising Edge
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 μA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted)
50
30
180
20
120
10
60
0
0
-10
-60
-20
-120
-30
-180
-40
-240
-50
-300
0
40
80
120
160
Time (Ps)
200
240
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
VEN = 3.3 V, COUT = 10 µF
Figure 6-19. Load Transient, 45 mA to 105 mA
-50
-100
-100
-200
-150
AC Coupled Output Voltage (mV)
0
-300
0.25
0.5
0.75
1
1.25
Time (ms)
1.5
1.75
300
-50
200
-100
100
75
100 125 150
Time (Ps)
175
200
225
0
250
VOUT = 5 V, IOUT = 150 mA to 350 mA, slew rate = 0.1 A/µs,
VEN = 3.3 V, COUT = 10 µF
Figure 6-23. Load Transient, 150-mA to 350-mA
12
-200
20
40
60
80
100 120
Time (Ps)
140
160
180
-250
200
300
25qC
150qC
IOUT
100
200
50
100
0
0
-50
-100
-100
-200
20
40
60
80
100 120
Time (Ps)
140
160
180
-300
200
300
AC Coupled Output Voltage (mV)
0
50
-150
-30
Figure 6-22. Load Transient, No Load to 150-mA Rising Edge
400
25
-20
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
Output Current (mA)
AC Coupled Output Voltage (mV)
50
0
-100
0
600
-40qC
25qC
150qC 500
IOUT
-150
-50
-10
-150
Figure 6-21. Load Transient, No Load to 150-mA
100
0
0
2
VOUT = 5 V, IOUT = 0 mA to 150 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
150
50
10
150
Output Current (mA)
AC Coupled Output Voltage (mV)
100
0
100
20
Figure 6-20. Load Transient, 45-mA to 105-mA Rising Edge
200
0
150
30
-40qC
50
IOUT
VOUT = 5 V, IOUT = 45 mA to 105 mA, slew rate = 0.1 A/µs,
VEN = 3.3 V, COUT = 10 µF
300
-40qC
25qC
150qC
IOUT
150qC
40
0
150
25qC
-40
280
100
200
-40qC
240
Output Current (mA)
IOUT
600
-40qC
25qC
150qC
IOUT
250
200
150
500
400
300
100
200
50
100
0
0
-50
-100
-100
-200
-150
-300
-200
-400
-250
-500
-300
Output Current (mA)
150qC
AC Coupled Output Voltage (mV)
25qC
Output Current (mA)
300
-40qC
40
Output Current (mA)
AC Coupled Output Voltage (mV)
50
-600
0
0.5
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
VOUT = 5 V, IOUT = 0 mA to 500 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
Figure 6-24. Load Transient, No Load to 500 mA
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 μA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted)
900
660
100
750
659
50
600
658
0
450
-50
300
-100
150
-150
0
-200
-150
150
150qC
IOUT
657
IOUT (mA)
25qC
Output Current (mA)
AC Coupled Output Voltage (mV)
-40qC
656
655
654
653
652
-250
0
20
40
60
80
100 120
Time (Ps)
140
160
180
-300
200
651
VOUT = 5 V, IOUT = 0 mA to 500 mA, slew rate = 1 A/µs,
VEN = 3.3 V, COUT = 10 µF
-45
-15
15
45
75
Temperature (qC)
105
135
VIN = VOUT + 1 V, VOUT = 90% × VOUT(NOM)
Figure 6-26. Output Current Limit vs Temperature
Figure 6-25. Load Transient, No Load to 500-mA Rising Edge
175
40
-55qC
-40qC
35
0qC
25qC
85qC
125qC
150qC
-55qC
-40qC
0qC
25qC
85qC
150
125
Iq (PA)
30
Iq (PA)
Current Limit
650
-75
25
20
125qC
150qC
100
75
50
15
25
10
0
5
10
15
20
25
Input Voltage (V)
30
35
40
0
5
10
15
20
25
Input Voltage (V)
30
35
40
VOUT = 5 V
Figure 6-28. Quiescent Current (IQ) vs VIN
281
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-55 qC
-40 qC
0 qC
25 qC
85 qC
125 qC
150 qC
280
279
Ground Current (PA)
Ground Current (PA)
Figure 6-27. Quiescent Current (IQ) vs VIN
278
277
276
275
274
273
272
0
50
100
150
200 250 300 350
Output Current (mA)
400
Figure 6-29. Ground Current (IGND) vs IOUT
450
500
271
-75
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
Figure 6-30. Ground Current at 100 mA
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 μA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted)
1.38
26
Falling Threshold
Rising Threshold
1.36
1.34
EN Threshold (V)
24
23
22
1.32
1.3
1.28
1.26
1.24
1.22
21
-75
-50
-25
0
25
50
75
Ambient Temperature (qC)
100
125
150
1.2
-60
Figure 6-31. Ground Current at 500 µA
-20
0
20 40 60 80
Temperature (qC)
20
Falling Threshold
Rising Threshold
Voltage (V)
89
15
900
Output Voltage
Enable Voltage 800
Inrush Current 700
12.5
600
10
500
7.5
400
5
300
2.5
200
0
100
17.5
91
90
100 120 140 160
Figure 6-32. EN Threshold vs Temperature
92
PG Threshold (%)
-40
-2.5
88
0
-5
0
87
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
300
400 500 600
Time (s)
700
800
-100
900 1000
1.58
Falling Threshold
Rising Threshold
1.57
2.7
Delay Pin Current (PA)
UVLO Threshold (V)
200
Figure 6-34. Start-Up Plot Inrush Current
2.8
2.65
2.6
2.55
2.5
1.56
1.55
1.54
1.53
2.45
2.4
-60
100
VIN = 13.5 V, VOUT = 5 V, IOUT = 150 mA, VEN = 3.3 V, COUT =
10 µF
Figure 6-33. PG Threshold vs Temperature
2.75
Output Current (mA)
Ground Current (PA)
25
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
1.52
-60
-40
-20
0
20 40 60 80
Temperature qC
100 120 140 160
VDELAY = 1 V
Figure 6-35. Undervoltage Lockout (UVLO) Threshold vs
Temperature
14
Figure 6-36. Delay Pin Current vs Temperature
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6.7 Typical Characteristics (continued)
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 μA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω, CIN = 1 µF, and VEN
= 2 V (unless otherwise noted)
20
18
OFF
Output voltage (V)
16
14
12
10
ON
8
6
4
0.2
0.4
0.6
0.8
1
1.2
Injected current (mA)
1.4
1.6
-50
1.8
-25
25
50
75 100 125
Temperature (qC)
150
175
200
xx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx
Figure 6-38. Thermal Shutdown
Figure 6-37. Output Voltage vs Injected Current
10
5
2
1
0.5
x
0.2
0.1
0.05
ESR (:)
0
x
Stable region
0.02
0.01
0.005
0.002
0.001
0.0005
x
0.0002
0.0001
1
2
3 4 5 6 78 10
20 30 50 70 100
COUT (PF)
200 300 500
Figure 6-39. Stability, ESR vs COUT
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7 Detailed Description
7.1 Overview
The TPS7B86-Q1 is a low-dropout linear regulator (LDO) with improved transient performance that allows
for quick response to changes in line or load conditions. The device aslo features a novel output overshoot
reduction feature that minimizes output overshoot during cold-crank conditions.
The integrated power-good and delay features allow for the system to notify down-stream components when the
power is good and assist in sequencing requirements.
During normal operation, the device has a tight DC accuracy of ±0.85% over line, load, and temperature. The
increased accuracy allows for the powering of sensitive analog loads or sensors.
7.2 Functional Block Diagrams
IN
OUT
Current
Limit
R1
±
+
Thermal
Shutdown
UVLO
R2
EN
Bandgap
GND
Figure 7-1. TPS7B86-Q1 Fixed Output Without PG
IN
OUT
Current
Limit
±
+
Thermal
Shutdown
UVLO
EN
FB
Bandgap
GND
Figure 7-2. TPS7B86-Q1 Adjustable Output Without PG
16
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IN
OUT
Current
Limit
R1
–
+
Thermal
Shutdown
UVLO
R2
EN
Bandgap
–
VREF
+
VSUBREG
PG
DELAY
–
VREF
+
PG
CTRL
Cap
Control
GND
Figure 7-3. TPS7B86-Q1 With PG
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7.3 Feature Description
7.3.1 Enable (EN)
The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable
pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than
the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the
enable pin to the input of the device.
7.3.2 Power-Good (PG)
The power-good (PG) pin is an open-drain output and can be connected to a regulated supply through an
external pullup resistor. The maximum pullup voltage is listed as VPG in the Recommended Operating Conditions
table. For the PG pin to have a valid output, the voltage on the IN pin must be greater than VUVLO(RISING),
as listed in the Electrical Characteristics table. When VOUT exceeds VPG(TH, RISING), the PG output is high
impedance and the PG pin voltage pulls up to the connected regulated supply. When the regulated output falls
below VPG(TH, FALLING), the open-drain output turns on and pulls the PG output low. If output voltage monitoring is
not needed, the PG pin can be left floating or connected to ground.
By connecting a pullup resistor to an external supply, any downstream device can receive power-good (PG) as a
logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid
logic signal for the receiving device.
7.3.3 Adjustable Power-Good Delay Timer (DELAY)
The power-good delay period is a function of the external capacitor on the DELAY pin. The adjustable delay
configures the amount of time required before the PG pin becomes high. This delay is configured by connecting
an external capacitor from this pin to GND. Figure 7-4 shows the typical timing diagram for the power-good delay
pin. If the DELAY pin is left floating, the power-good delay is t(DLY_FIX). For more information on how to program
the PG delay, see the Setting the Adjustable Power-Good Delay section.
VIN
V(UVLO)
t < t(DEGLITCH)
VOUT
DELAY
V(PG_HYST)
V(PG_TH) rising
V(PG_ADJ) rising
V(PG_TH) falling
V(PG_ADJ) falling
V(DLY _TH)
t(DEGLITCH)
t(DLY )
t(DEGLITCH)
t(DLY )
PG
Power Up
Input Voltage Drop
Undervoltage
Power Down
V(PG_TH) falling = V(PG_TH) rising – V(PG_HYST)..
Figure 7-4. Typical Power-Good Timing Diagram
7.3.4 Undervoltage Lockout
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
18
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7.3.5 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start-up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
7.3.6 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the
output current fault condition continues, the device cycles between current limit and thermal shutdown. For more
information on current limits, see the Know Your Limits application note.
Figure 7-5 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
IOUT
0V
0 mA
IRATED
ICL
Figure 7-5. Current Limit
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
•
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off and internal circuits are shutdown.
20
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TPS7B86-Q1 requires an output capacitor of 2.2 µF or larger (1 µF or larger capacitance) for stability
and an equivalent series resistance (ESR) between 0.001 Ω and 2 Ω. For best transient performance, use
X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over
temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for
the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the
maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several
inches from the input power source.
8.1.2 Adjustable Device Feedback Resistor Selection
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)
(1)
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series
resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)
(2)
8.1.3 Feed-Forward Capacitor
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin
to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance
CFF can be used; however, the start-up time increases. For a detailed description of CFF tradeoffs, see the Pros
and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.
CFF and R1 form a zero in the loop gain at frequency fZ, while CFF, R1, and R2 form a pole in the loop gain at
frequency fP. CFF zero and pole frequencies can be calculated from the following equations:
fZ = 1 / (2 × π × CFF × R1)
(3)
fP = 1 / (2 × π × CFF × (R1 || R2))
(4)
8.1.4 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
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switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
RDS(ON) =
VDO
IRATED
(5)
8.1.5 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
8.1.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(6)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(7)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
22
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8.1.6.1 Thermal Performance Versus Copper Area
The most used thermal resistance parameter RθJA is highly dependent on the heat-spreading capability built
into the particular PCB design, and therefore varies according to the total copper area, copper weight, and
location of the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard
(see Figure 8-1), PCB, and copper-spreading area, and is only used as a relative measure of package thermal
performance. For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case
(bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.
Wire
Die
Mold
Compound
Die
Attach
2oz
Signal
Trace
Internal Signal
or power plane
1oz copper
Lead
Frame
Internal
GND plane
1oz copper
Thermal
Vias
Bottom
Relief
2oz copper
Thermal
Pad or Tab
of the LDO
Figure 8-1. JEDEC Standard 2s2p PCB
Figure 8-2 through Figure 8-5 illustrate the functions of RθJA and ψJB versus copper area and thickness. These
plots are generated with a 101.6-mm × 101.6-mm × 1.6-mm PCB of two and four layers. For the 4-layer board,
inner planes use 1-oz copper thickness. Outer layers are simulated with both 1-oz and 2-oz copper thickness.
A 2x3 (DDA package) or a 3×4 (KVU package) array of thermal vias with a 300-µm drill diameter and 25-µm
copper plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the
bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper
plane of equal area.
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4
4
2
2
0
10
20
Layer
Layer
Layer
Layer
PCB,
PCB,
PCB,
PCB,
30
40
50
60
70
Cu Area Per Layer (cm 2)
1
2
1
2
oz
oz
oz
oz
80
copper
copper
copper
copper
90
Thermal Resistance - RTJA (qC/W)
4
4
2
2
85
Layer
Layer
Layer
Layer
PCB,
PCB,
PCB,
PCB,
1
2
1
2
oz
oz
oz
oz
copper
copper
copper
copper
75
65
55
45
35
25
15
0
10
20
30
40
50
60
70
Cu Area Per Layer (cm 2)
80
90
100
Figure 8-4. RθJA vs Copper Area (KVU Package)
4
4
2
2
21
20
19
Layer
Layer
Layer
Layer
PCB,
PCB,
PCB,
PCB,
1
2
1
2
oz
oz
oz
oz
copper
copper
copper
copper
18
17
16
15
14
13
12
11
100
Figure 8-2. RθJA vs Copper Area (DDA Package)
95
Thermal Resistance -
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