TRF1221IRGZR

TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 Dual VCO/PLL Synthesizer With IF Upconverter • • • • • • • • • DESCRIPTION The TRF1121 and TRF1221 are VHF-UHF upconverters with integrated UHF and S-band frequency synthesizers for radio applications in the 2-GHz to 4-GHz range. The IC performs the first upconversion and generates the local oscillator (LO) for the second upconversion. The device uniquely integrates an image reject mixer, IF gain blocks, 5-bit gain control, and two complete phase-locked-loop (PLL) circuits including: VCOs, resonator circuit, varactors, dividers, and phase detectors. LPCC−48 PACKAGE (TOP VIEW) LO2ABPB LO2ATUN LO2ABPA LO2BBPB LO2BTUN LO2BBPA GND LO2OP LO2ON GND VCCLO2 GND • • The TRF1121 and TRF1221 are designed to function as part of complete 2.5-GHz and 3.5-GHz radio chipsets, respectively. In the chipset, the transmit chain operates as a double upconverter from an IF frequency input (typically from a baseband modem's DAC) to an RF output frequency. The TRF1121/ TRF1221 performs the first upconversion from IF signals in the range of 10 MHz to 60 MHz to a second IF frequency in the range of 300 MHz to 360 MHz. The radio chipset features sufficient linearity, phase noise, and dynamic range to work in either single carrier or multicarrier, line-of-sight or non-line-of-sight, standard (IEEE 802.16), or proprietary systems. Due to the modular nature of the chipset, it is ideal for use in systems that employ transmit or receive diversity. 48 47 46 45 44 43 42 41 40 39 38 37 • Low Phase Noise Image Reject Upconverter Dual VCO/PLL For Double Upconversion Architecture On-Chip VCO, Resonator, and PLL Only; Requires Off-Chip Loop Filter External S-Band VCO Option 5-Bit Transmit Level Control, 32 dB in 1-dB Steps S-Band LO Frequency Range: – TRF1121: 1500 to 2500 MHz – TRF1221: 1700 to 3600 MHz UHF LO Frequency Range: 250 MHz to 350 MHz Input Frequency Range: 10 MHz to 70 MHz S-Band LO Phase Noise Typical 0.5° rms (100 Hz to 1 MHz) Output Power Range From –32 dBm to 0 dBm in 1-dB Steps (500-mVpp Differential Input) Minimum UHF LO Step Size of 50 kHz for TRF1121 and 62.5 kHz for TRF1221 Image Rejection: –50 dBc, Typical (20–40 MHz Tx IF Input) LO Leakage: –36 dBm, Typical Third-Order IMD: < –60 dBc at Maximum Gain CP2O LD2 LF2 DATA CLK VCCD2 FR VCCD1 FRBP EN LF1 LD1 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 EXTLO2IP EXTLO2IN TXON IFOP VCCIF IFON GND GND GAIN[4] GAIN[3] GAIN[2] GAIN[1] 13 14 15 16 17 18 19 20 21 22 23 24 • • • CP1O LO1BPA LO1TUN LO1BPB VCCLO1 GND GND GND BBIN BBIP VCCUPC GAIN[0] FEATURES 1 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2008, Texas Instruments Incorporated TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. BLOCK DIAGRAM VCCD1 VCCD2 GND Power Supply VCCIF Upconverter VCCUPC VarAtten IFOP IF2 BBIP 90o IFON BBIN IF1 TXON 90o GAIN[4] GAIN[3] GAIN[2] GAIN[1] Amplitude Select VCCLO1 N GAIN[0] LO1BPA LO1BPB CLK DATA EN Serial Interface Synth #1 Divider PFD/CP VCO#1 Synth #2 Divider − + + Synthesizer #1 N LO2OP VCO2A LO2ON PFD/CP VCO2B − + + Synthesizer #2 FR FRBP LD1 LF1 CP1O LO1TUN LF2 LD2 CP2O LO2ATUN LO2BTUN EXTLO2IP Submit Documentation Feedback EXTLO2IN VCCLO2 LO2ABPB LO2ABPA LO2BBPA LO2BBPB 2 Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): TRF1121 TRF1221 TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O TYPE DESCRIPTION BBIN 21 I Analog Baseband IF input (2-kΩ differential) negative, dc-coupled; internal voltage is 4 V DC BBIP 22 I Analog Baseband IF input (2-kΩ differential) positive, dc-coupled; internal voltage is 4 V DC CLK 5 I Digital CP1O 13 O Analog Analog synthesizer 1 charge pump output CP2O 1 O Analog Analog synthesizer 2 charge pump output DATA 4 I Digital Serial interface data input EN 10 I Digital Serial interface load enable (active-high) EXTLO2IN 35 I Analog External input for LO2 (differential) negative and logic level for VCO select. EXTLO2IP 36 I Analog External input for LO2 (differential) positive and logic level for VCO select. FR 7 I Analog 18-MHz reference clock input, HCMOS input. (DC level = 2.5 V) FRBP 9 O Analog Reference frequency bypass. Internally biased to 2.5 V. GAIN[0] 24 I Digital Gain control bit 0 (LSB). Logic low induces 1-dB attenuation. GAIN[1] 25 I Digital Gain control bit 1. Logic low induces 2-dB attenuation. GAIN[2] 26 I Digital Gain control bit 2. Logic low induces 4-dB attenuation. GAIN[3] 27 I Digital Gain control bit 3. Logic low induces 8-dB attenuation. GAIN[4] 28 I Digital Gain control bit 4 (MSB). Logic low induces 16-dB attenuation. Power Ground Serial interface clock input GND 18–20, 29, 30, 37, 39, 42 IFON 31 O Analog IF analog output (100-Ω differential) negative, dc-coupled, internal voltage is 2.1 V dc. IFOP 33 O Analog IF analog output (100-Ω differential) positive, dc-coupled, internal voltage is 2.1 V dc. LD1 12 O Digital Synthesizer 1 lock detect output, high is locked. LD2 2 O Digital Synthesizer 2 lock detect output, high is locked. LF1 11 O Analog Lock detect filter capacitor for LO1, 0.01 µF typical 100 kΩ (1) LF2 3 O Analog Lock detect filter capacitor for LO2, 0.01-µF typical, 100-kΩ pullup (1) LO1BPA 14 O Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to any other pin. LO1BPB 16 O Analog Bypass capacitor for LO1, 0.1 µF (min), DCV = 1 V LO1TUN 15 I Analog VCO synthesizer 1 tuning port LO2ABPA 46 O Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to any other pin. LO2ABPB 48 O Analog Bypass capacitor for LO2A, 0.1 µF (min), DCV = 1 V LO2ATUN 47 I Analog LO2A tune port LO2BBPA 43 O Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to any other pin. LO2BBPB 45 O Analog Bypass capacitor for LO2B, 0.1 µF (min), DCV = 1 V LO2BTUN 44 I Analog LO2B tune port LO2ON 40 O Analog LO2 negative output (differential) and positive VCC bias (5 V) for LO buffer amplifier LO2OP 41 O Analog LO2 positive output (differential) and positive VCC bias (5 V) for LO buffer amplifier TXON 34 I Digital IF amplifier enable active high VCCD1 8 I Power 5-V power for digital VCCD2 6 I Power 5-V power for digital VCCIF 32 I Power 5-V power for analog VCCLO1 17 I Power VCC for LO1 VCCLO2 38 I Power VCC for LO2 A and B VCCUPC 23 I Power 5-V power for analog Back (1) Back side of package has metal base that must be grounded for thermal and RF performance Current leakage on the order of 10 µA through the capacitor or by any other means from either LF pin can cause false loss-of-lock signals. The two pullup resistors (R16 and R17) in Figure 23 reduce this sensitivity. Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): TRF1121 TRF1221 Submit Documentation Feedback 3 TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE UNIT VCC DC supply voltage 0 to 5.5 V ICC DC supply current 270 mA Pin RF input power 20 dBm TJ Junction temperature 150 °C Pdiss Power dissipation 1.5 W Digital input voltage –0.3 to VCC + 0.3 V Analog input voltage VCC V 25 °C/W RθJC Thermal resistance, junction-to-ambient (1) Tstg Storage temperature –40 to 105 °C Top Operating temperature –40 to 85 °C 260 °C Lead temperature, 40 seconds maximum (1) Thermal resistance is junction-to-ambient assuming thermal pad with nine thermal vias under package metal base. See the recommended PCB layout. ELECTRICAL CHARACTERISTICS The characteristics listed in the following tables are at VCC = 5 V, TA = 25°C (unless otherwise noted) DC CHARACTERISTICS PARAMETER VCC ICC_TxON ICC_TxOFF DC supply voltage Supply current TEST CONDITIONS MIN TA = 25°C TYP 4.8 MAX 5.2 TA = 25°C, TXON enabled 180 TA = 25°C, TXON disabled 130 UNIT V mA UPCONVERTER CHARACTERISTICS Input signal 500 mVpp, VCC = 5 V, 25°C, IF1 = 26 MHz, IF2 = 325 MHz unless otherwise stated PARAMETER fIF1 Input center frequency fIF2 Output frequency range VBB Input signal level ZIF1 Input IF1 differential impedance TEST CONDITIONS MIN See Figure 3 TYP MAX 26 270 Peak-to-peak differential MHz 500 1000 mV 2 kΩ 0 dBm –32 dBm Output power (maximum gain) Output power (minimum gain) Measured at IF2 (IF2OP, IF2ON) with 500-mVpp differential input to IF1(BBIP, BBIN), GAIN[4:0] = 00000 ΔGmax Gain flatness 300 MHz < IF2 < 330 MHz ΔPSTEP Gain step size OP1dB Output power a 1-dB gain compression GAIN[4:0] = 11111 12 OIP3 Output third order intercept For any gain setting 24 IR Image rejection IF1 = 15 to 45 MHz PLO1 LO1 leakage At GAIN[4:0] = 11111 decreases dB for dB as gain state is changed NF Input noise figure At max gain (GAIN[4:0] = 11111), no worse than 1-dB degradation per 1 dB of attenuation ZIF2 Output RF impedance Differential 4 Submit Documentation Feedback MHz 400 Measured at IF2 (IF2OP, IF2ON) with 500-mVpp differential input to IF1(BBIP, BBIN) and GAIN[4:0] = 11111 Pout ±0.3 0.7 UNIT 1 dB 1.3 dB dBm dBm –30 dBc –36 dBm 27 dB 100 Ω Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): TRF1121 TRF1221 TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 SYNTHESIZER #1 (UHF-BAND PLL) CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX fRef Reference frequency fVCO1 Frequency φnFRVCO1 Free-running VO1 SSB phase noise at 100 kHz –115 dBc/Hz φnLD LO1 Locked synthesizer-1 SSB phase noise at 10 kHz –115 dBc/Hz φnLD LO1 Locked synthesizer-1 SSB phase noise at 100 kHz –115 fLD LO1 MSLO1 18 UNIT TRF1121 and TRF1221 250 Locked synthesizer-1 integrated RMS phase noise 100 Hz to 1 MHz Tuning sensitivity For VLO1TUN > 2 V 30 TRF1121, 18-MHz reference input 50 TRF1221, 18-MHz reference input 62.5 ΔfLO1 Step size RRS LO1 Reference spur rejection RFS LO1 Fractional spurs rejection MHz 350 MHz dBc/Hz 0.2 ° 60 MHz/V kHz –70 dBc –60 dBc SYNTHESIZER #2 (S-BAND PLL) CHARACTERISTICS PARAMETER fRef TEST CONDITIONS MIN Reference frequency TYP 18 1500 2100 TRF1221 1700 2450 TRF1121 1700 2500 TRF1221 2400 3600 TRF1121 For VLO1TUN >2 V 150 350 TRF1221 For VLO1TUN >2 V 200 400 TRF1121 For VLO1TUN >2 V 200 400 TRF1221 For VLO1TUN >2 V 350 550 Output frequency, VCO2A fLO2B Output frequency, VCO2B MSLO2A Tuning sensitivity, VCO2A MSLO2B Tuning sensitivity, VCO2B ΔfLO2 Step size For 18-MHz reference input PLO2 Output power level Measured into a 100-Ω differential load at the LO1OP/N port –3 Free-running SSB phase noise at 100 kHz Measured into a 100-Ω differential load at the LO1OP/N port –100 φnLD VCO2 Locked synthesizer SSB phase noise at 10 kHz LO2 φLD LO2 RRS RFS Locked synthesizer SSB phase noise at 100 kHz 1 Measured into a 100-Ω differential load at the LO2OP/N port with loop filter set to 400 kHz nominal MHz/V dBc/Hz –102 –97 –100 –95 0.5 1 LO2 Reference sideband suppression Measured into a 100-Ω differential load at the LO1OP/N port. PLL loop bandwidth ~400 kHz –65 –60 At 1 MHz offset (Loop BW ~400 kHz) –50 –45 LO2 Fractional spur suppression At 2 MHz offset (Loop BW ~400 kHz) –65 –60 All others –70 –70 Harmonics suppression RLLO2 Output return loss Measured into a 100-Ω differential load at the LO1OP/N port –11 PextVCO Ext VCO input power RLextVCO Ext VCO port input return loss Differential mode –10 Zin extVCO Ext VCO port input impedance Differential mode Product Folder Link(s): TRF1121 TRF1221 MHz/V dBm Locked, 100 Hz to 1 MHz Copyright © 2005–2008, Texas Instruments Incorporated MHz MHz Integrated RMS phase noise LO2 MHz dBc/Hz Measured into a 100-Ω differential load at the LO1OP/N port RH UNIT MHz TRF1121 fLO2A φnFR MAX –20 ° dBc dBc dBc –16 dB –13 dBm –15 dB 100 Ω Submit Documentation Feedback 5 TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 INPUT REFERENCE REQUIREMENTS Conditions: Signal BW = 6 MHz nom, 15 dB maximum loss IF2 SAW filter. See Figure 19 PARAMETER fRef TEST CONDITIONS MIN Reference frequency MAX 18 Temperature stability Customer requirements VFR Ref. source input voltage (1) HCMOS output DCfref Reference input symmetry Waveform duty cycle tFR Reference source pulse rise time 10% to 90% of maximum voltage transition fFR Reference phase noise at 10-kΩ offset (1) TYP UNIT MHz PPM 4 4.5 40% 5 Vpp 60% 1 4 –153 –150 ns dBc/Hz Note that for source peak-to-peak voltages of less than 4 V and dc component other than 2.5 V, degradation of the close-in phase noise may occur. For oscillators with no dc component, a dc voltage may be applied using a voltage divider (see the schematic, Figure 23). AC TIMING, SERIAL BUS INTERFACE CDI Data A[7]=MSB DVC A[6] A[5] CEL A[4] D[1] D[0] LSB Clock EN ELC CPWH PARAMETER CPWL EPWH MIN TYP MAX UNIT CDI Clock to data invalid 10 ns DVC Data valid to clock 10 ns CPWH Clock pulse duration high 50 ns CPWL Clock pulse duration low 50 ns CEL Clock to enable low 10 ns ELC Enable low to clock 10 ns EPWH Enable pulse duration 10 ns Figure 1. Serial Interface Timing Diagram 6 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): TRF1121 TRF1221 TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 DIGITAL INTERFACE CHARACTERISTICS Conditions: Signal BW = 6 MHz nom, 15 dB maximum loss IF2 SAW filter. See Figure 19 PARAMETER VIH Input high voltage VIL TEST CONDITIONS MIN TYP MAX UNIT 2.1 5 V Input low voltage 0 0.8 V IIH Input high current 0 50 µA IIL Input low current 0 –50 µA CI Input capacitance VOH Output logic 1 voltage ROH Output logic 1 impedance VOL Output low voltage 3 0 to 100-µA load 2.4 pF 3.6 18 0 to –100-µA load 0 V kΩ 0.4 V AUXILIARY AND CONTROL PARAMETER TXON EXTLO2IP EXTLO2IN EXTLO2IP EXTLO2IN EXTLO2IP EXTLO2IN IF amplifier enable On-chip VCO2A selection On-chip VCO2B selection On-chip VCO2 selection TEST CONDITIONS MIN TYP MAX IF output on High IF output off Low UNIT High Logic level applied to EXTLOIP and EXTLOIN pins to select either on chip VCO 2A or 2B. Pullup resistor = 200 Ω and pulldown resistor = 1 kΩ. Low Low High Logic level applied to EXTLOIP and EXTLOIN pins to select the external VCO2 input Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): TRF1121 TRF1221 Low Low Submit Documentation Feedback 7 TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 FREQUENCY PLAN The TRF1121 and TRF1221 allow a variety of frequency plans. Figure 2 illustrates the allowable combinations of first and second IFs. However, due to the fact that the chip features image reject mixers, significant changes in the frequency plan can result in degradation of the image rejection as shown in Figure 3. LO leakage vs LO1 frequency is shown in Figure 4. In order to maintain maximum image rejection and LO suppression, a recommended frequency plan is TxIF1 = 26 MHz, TxIF2 = 325 MHz. 385 375 365 355 IF2 (MHz) 345 335 325 26 / 325 315 26 / 315 305 295 285 275 0 10 20 30 40 50 60 70 80 IF1 (MHz) Figure 2. Potential IF Combinations (TRF1121/1221) 8 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): TRF1121 TRF1221 TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 0 Vin=500mVpp diff Max. Gain, T=25oC −10 Image Rejectin (dBc) −20 −30 −40 −50 LO2=270 MHz −60 LO2=299MHz LO2=320 MHz −70 5 15 25 35 45 55 65 75 Input Tx IF1 (MHz) RC1x21 IR Figure 3. Image Rejection vs IF1, Transmit Chain 0 Vin=500mVpp diff T=25oC LO1 Leakage (dBm) −10 −20 −30 −40 −50 250 260 270 280 290 300 310 320 330 340 350 LO1 Frequency (MHz) Figure 4. LO1 Leakage at IF2 Port, Maximum Gain Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): TRF1121 TRF1221 Submit Documentation Feedback 9 TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 TRANSMIT LEVEL CONTROL The TRF1121 and TRF1221 offer 32 dB of gain control through a five-wire parallel bus. When driven with a 500-mVpp differential baseband IF signal, the transmit level can be programmed between –32 dBm and 0 dBm in 1-dB steps. Figure 5 shows the output power, two-tone imtermodulation level, LO leakage, and gain deviation from ideal vs gain state, while Figure 6 shows the upconverter gain variation vs temperature. 1 0 Vin=500mVpp diff T=25oC Pout −20 0 Gain Deviation from ideal −30 −1 −40 −50 LO1 Leakage at IF2 port −60 −2 IMD Level with two input tones at 250 mVpp diff. each Gain Deviation from Ideal (dB) Pout, LO Leakage (dBm) IMD Level (dBc) −10 −70 −3 −80 30 28 26 RC1x21 Po, PLO, IM3 (G) 24 22 20 18 16 14 Gain State 12 10 8 6 4 2 0 Figure 5. Output Power, LO Leakage and IMD Level vs Gain State 10 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): TRF1121 TRF1221 TRF1121 TRF1221 www.ti.com SLWS170B – APRIL 2005 – REVISED JANUARY 2008 −10 2 −20 1 Pout with Vin =500mVppdiff −30 −40 0 −1 LO1 Leakage at IF2 port −50 −60 −70 −40 −2 IMD Level with two input tones at 250mVppdiff each Pout (dBm) Pout, LO leakage (dBm), IMD Level (dBc) All measurements are made at Max. Gain −3 −4 −30 −20 −10 0 10 20 30 o 40 50 60 70 80 90 Temperature ( C) Figure 6. Power Level, IMD and LO1 Leakage Variation vs Temperature at Maximum Gain Setting RC1x21 Output Power vs Input Voltage 14.00 12.00 Output Power (dBm) 10.00 8.00 Input at 26 MHz Output at 325 MHz T=25 degrees Input Impedance