TRF371109
SLWS225B – DECEMBER 2010 – REVISED MAY 2011
www.ti.com
Direct Downconversion Receiver
Check for Samples: TRF371109
FEATURES
DESCRIPTION
•
•
The TRF371109 is a highly linear direct-conversion
quadrature receiver. The TRF371109 integrates
balanced I and Q mixers, LO buffers, and phase
splitters to convert an RF signal directly to I and Q
baseband. The on-chip programmable gain amplifiers
allow adjustment of the output signal level without the
need for external variable gain (attenuator) devices.
The TRF371109 integrates programmable baseband
low-pass filters that attenuate nearby interference,
eliminating the need for an external baseband filter.
1
2
•
•
•
•
•
•
•
Frequency Range: 300 MHz to 1700 MHz
Integrated Baseband Programmable Gain
Amplifier
On-Chip Programmable Baseband Filter
High Cascaded IP3: 27 dBm at 900 MHz
High IP2: 68 dBm at 900 MHz
Hardware and Software Power Down
Three-Wire Serial Interface
Single Supply: 4.5-V to 5.5-V Operation
Silicon Germanium Technology
Housed in a 7-mm × 7-mm VQFN package, the
TRF371109 provides the smallest and most
integrated
receiver
solution
available
for
high-performance equipment.
APPLICATIONS
•
•
•
•
Multicarrier Wireless Infrastructure
WiMAX
High-Linearity Direct-Downconversion
Receiver
LTE (Long Term Evolution)
To Microcontroller
READBACK
41
40
39
38
NC
Gain_B2
42
Gain_B0
43
Gain_B1
44
NC
45
NC
46
MIXIOUTP
STROBE
47
MIXIOUTN
CLOCK
48
1
37
36
GNDDIG
VCCDIG
2
35
GND
CHIP_EN
3
34
BBIOUTP
VCCMIX1
4
33
BBIOUTN
GND
5
32
GND
MIXINP
6
31
LOIP
MIXINN
7
30
LOIN
GND
8
29
VCCLO
VCCMIX2
9
28
BBQOUTP
NC
10
27
BBQOUTN
NC
11
26
GND
12
13
14
15
16
17
18
23
25
24
GND
GND
MIXQOUTP
MIXQOUTN
NC
NC
VCM
VCCBBI
GND
20
21
22
REXT
GNDBIAS
19
VCCBIAS
GND
TRF371109
NC
RFIN
DATA
To Microcontroller
To ADC I
LOIN
To ADC Q
VCCBBQ
30 kW
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TRF371109
SLWS225B – DECEMBER 2010 – REVISED MAY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE DEVICE OPTIONS (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
TRF371109
VQFN-48
RGZ
–40°C to +85°C
TRF371109IRGZ
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
TRF371109IRGZR
Tape and Reel, 2500
TRF371109IRGZT
Tape and Reel, 250
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
space
MIXIOUTP
44
45
MIXIOUTN
FUNCTIONAL DIAGRAM
ADC Driver
33
VCC
PGA
34
BBIOUTP
BBIOUTN
GND
24
DC Offset Control I
30
0°
MIXINP
MIXINN
6
31
90°
VCM
LOIN
LOIP
7
DC Offset Control Q
27
PGA
28
BBQOUTN
BBQOUTP
ADC Driver
CHIP_EN
3
Power
Down
48
DC Offset Control
47
LPFADJ Control
SPI
46
37
2
DATA
STROBE
39
READBACK
Gain_B2
Gain_B1
40
41
Gain_B0
17
MIXQOUTN
MIXQOUTP
16
PGA Control
CLOCK
Copyright © 2010–2011, Texas Instruments Incorporated
TRF371109
SLWS225B – DECEMBER 2010 – REVISED MAY 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted). (1)
Supply voltage range
(2)
VALUE
UNIT
–0.3 to 5.5
V
–0.3 to VCC +0.5
V
Operating virtual junction temperature range, TJ
–40 to +150
°C
Operating ambient temperature range, TA
–40 to +85
°C
Storage temperature range, Tstg
–65 to +150
°C
Digital I/O voltage range
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
VCC
Power-supply voltage
MIN
NOM
4.5
5.0
Power-supply voltage ripple
MAX
UNIT
5.5
V
940
µVPP
TA
Operating free-air temperature range
–40
+85
°C
TJ
Operating virtual junction temperature range
–40
+150
°C
MAX
UNIT
THERMAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted).
PARAMETER (1)
TEST CONDITIONS
MIN
TYP
Soldered slug, no airflow
RθJA
Thermal resistance, junction-to-ambient
RθJA (2)
RθJB
(1)
(2)
Thermal resistance, junction-to-board
26
Soldered slug, 200-LFM airflow
20.1
Soldered slug, 400-LFM airflow
17.4
7-mm × 7-mm, 48-pin PDFP
25
7-mm × 7-mm 48-pin PDFP
12
°C/W
°C/W
Determined using JEDEC standard JESD-51 with high-K board
16 layers, high-K board
THERMAL INFORMATION
TRF371109
THERMAL METRIC (1)
RGZ
UNITS
48 PINS
θJA
Junction-to-ambient thermal resistance
26.9
θJCtop
Junction-to-case (top) thermal resistance
11.2
θJB
Junction-to-board thermal resistance
3.4
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
3.4
θJCbot
Junction-to-case (bottom) thermal resistance
0.6
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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TRF371109
SLWS225B – DECEMBER 2010 – REVISED MAY 2011
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ELECTRICAL CHARACTERISTICS
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C,unless otherwise noted.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PARAMETERS
ICC
Total supply current
360
mA
Power-down current
2
mA
IQ DEMODULATOR AND BASEBAND SECTION
fRF
Frequency range
300
Gain range
22
Gain step
See (1)
Maximum RF power input
1700
24
MHz
dB
1
dB
Before damage
25
dBm
OIP3
Gain setting = 24 (2)
30
dBVRMS
P1dBMin
One tone (3)
3
dBVRMS
PinMax
fMin
Minimum baseband low-pass filter
(LPF) cutoff frequency
1-dB point (4)
fMax
Maximum baseband LPF cutoff
frequency
3-dB point (4)
fBypass
Baseband LPF cutoff frequency in
bypass mode
3-dB point (5)
Fsel
Baseband relative attenuation at
LPF cutoff frequency (fC) (6)
700
15
MHz
1 × fC
1
dB
1.5 × fC
8
dB
2 × fC
32
dB
3 × fC
54
dB
4 × fC
75
dB
5 × fC
90
dB
–40
dB
Output BB attenuator
VCM
Output, common-mode
Baseband harmonic level
MHz
30
Image suppression
Output load impedance (7)
kHz
3
dB
1
kΩ
Parallel capacitance
20
pF
Measured at I- and Q-channel baseband
outputs
1.5
V
Parallel resistance
Second harmonic (8)
Third harmonic (8)
–100
dBc
–93
dBc
LOCAL OSCILLATOR PARAMETERS
Local oscillator frequency
300
(9)
–3
LO input level
See
LO leakage
At MIXINN/MIXINP at 0-dBm LO drive level
0
1700
MHz
6
dBm
–58
dBm
DIGITAL INTERFACE
VIH
High-level input voltage
0.6 × VCC
VIL
Low-level input voltage
0
VOH
High-level output voltage
VOL
Low-level output voltage
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
4
5
VCC
V
0.8
V
0.8 × VCC
V
0.2 × VCC
V
Two consecutive gain settings.
Two CW tones at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband
circuitry regardless of LO frequency.
Single CW tone at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband
circuitry regardless of LO frequency.
Baseband low-pass filter cutoff frequency is programmable through SPI register LPFADJ. LPFADJ = 0 corresponds to max bandwidth;
LPFADJ = 255 corresponds to minimum BW.
Filter Ctrl setting equal to 0.
Attenuation relative to passband gain.
The typical value for this parameter is the load impedance that the device is able to drive.
LO frequency set to 900 MHz. Power-in set to –40 dBm. Gain setting at 24. DC offset calibration engaged. Input signal set at 2.5-MHz
offset.
LO power outside of this range is possible but may introduce degraded performance.
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TRF371109
SLWS225B – DECEMBER 2010 – REVISED MAY 2011
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C,unless otherwise noted.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fLO = 300 MHz (10)
GMax
Maximum gain (11)
Gain setting = 24
48.7
NF
Noise figure
Gain setting = 24
8.7
dB
IIP3
Third-order input intercept point
Gain setting = 24 (12) (13)
13.9
dBm
IIP2
Second-order input intercept point
Gain setting = 24 (13) (14)
45
dBm
dB
dB
fLO = 700 MHz (10)
GMax
Maximum gain (11)
Gain setting = 24
43
NF
Noise figure
Gain setting = 24
10.7
IIP3
Third-order input intercept point
Gain setting = 24 (12) (13)
25
dBm
IIP2
Second-order input intercept point
Gain setting = 24 (13) (14)
70
dBm
Gain setting = 24
41
dB
Gain setting = 24
12.4
dB
Gain setting = 16
14.8
fLO = 900 MHz
GMax
dB
(10)
Maximum gain (11)
NF
Noise figure
IIP3
Third-order input intercept point
Gain setting = 24 (12) (13)
27
dBm
IIP2
Second-order input intercept point
Gain setting = 24 (13) (14)
68
dBm
fLO = 1425 MHz
dB
(10)
GMax
Maximum gain (11)
Gain setting = 24
36.9
NF
Noise figure
Gain setting = 24
15.5
IIP3
Third-order input intercept point
Gain setting = 24 (12) (13)
27
dBm
IIP2
Second-order input intercept point
Gain setting = 24 (13) (14)
65
dBm
fLO = 1700 MHz
dB
dB
(10)
GMax
Maximum gain (11)
Gain setting = 24
35.9
NF
Noise figure
Gain setting = 24
17.5
dB
IIP3
Third-order input intercept point
Gain setting = 24 (12) (13)
25.5
dBm
IIP2
Second-order input intercept point
Gain setting = 24 (13) (14)
60
dBm
dB
(10) For broadband frequency sweeps, the Picosecond balun (model #5310A) is used at the RF and LO input. For frequency bands between
600 MHz and 1250 MHz, the Murata balun LDB21897M005C-001 is used. Performance parameters adjusted for balun insertion loss.
Recommended baluns for respective frequency band are listed:
700 MHz and 900 MHz: Murata LDB21897M005C-001 (or equivalent)
1740 MHz: Murata LDB211G8005C-001 (or equivalent)
1950 MHz: Murata LDB211G9005C-001 (or equivalent)
2025 MHz: Murata LDB211G9005C-001 (or equivalent)
2500 MHz: Murata LDB212G4005C-001 (or equivalent)
3500 MHz: Johanson 3600BL14M050E (or equivalent)
(11) Gain defined as voltage gain from MIXIN (VRMS) to either baseband output: BBI/QOUT (VRMS)
(12) Two CW tones of –30 dBm at fRF1 = fLO ±(2 ● fc) and fRF2= fLO ±[(4 ● fc) + 100 kHz]; fc = Baseband filter 1-dB cutoff frequency.
(13) Because the two-tone interference sources are outside of the baseband filter bandwidth, the results are inherently independent of the
gain setting. Intermodulation parameters are recorded at maximum gain setting, where measurement accuracy is best.
(14) Two CW tones at –30 dBm at fRF1 = fLO ±(2 ● fc) and fRF2= fLO ±[(2 ● fc) + 100 kHz]; IM2 product measured at 100-kHz output
frequency. fC = Baseband filter 1-dB cutoff frequency.
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TRF371109
SLWS225B – DECEMBER 2010 – REVISED MAY 2011
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TIMING REQUIREMENTS
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t(CLK)
Clock period
50
ns
tSU1
Setup time, data
10
ns
tH
Hold time, data
10
ns
tW
Pulse width, STROBE
20
ns
tSU2
Setup time, STROBE
10
ns
DEVICE INFORMATION
PIN ASSIGNMENTS
space
Gain_B1
Gain_B2
READBACK
48
1
47
46
45
44
43
VCCDIG
2
35
GND
CHIP_EN
3
34
BBIOUTP
VCCMIX1
4
33
BBIOUTN
GND
5
32
GND
NC
NC
NC
MIXIOUTN
38
MIXIOUTP
39
STROBE
40
DATA
41
CLOCK
42
GNDDIG
37
36
VCCBBI
BBQOUTP
NC
10
27
BBQOUTN
NC
11
26
GND
14
15
16
17
18
19
20
21
22
23
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25
24
VCCBBQ
VCM
12
13
NC
VCCLO
28
GNDBIAS
29
9
VCCBIAS
8
NC
GND
VCCMIX2
REXT
LOIN
NC
30
MIXQOUTN
7
MIXQOUTP
LOIP
GND
31
GND
6
GND
MIXINP
MIXINN
GND
6
Gain_B0
RGZ PACKAGE
VQFN-48
(TOP VIEW)
Copyright © 2010–2011, Texas Instruments Incorporated
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TRF371109
SLWS225B – DECEMBER 2010 – REVISED MAY 2011
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PIN FUNCTIONS
PIN
NO.
NAME
I/O
DESCRIPTION
1
GNDDIG
2
VCCDIG
Digital ground
3
CHIP_EN
4
VCCMIX1
5
GND
6
MIXINP
I
Mixer input: positive terminal
7
MIXINN
I
Mixer input: negative terminal
8
GND
Ground
9
VCCMIX2
Mixer power supply
10
NC
No connect
11
NC
No connect
12
GND
Ground
13
GND
Ground
14
GND
Ground
15
GND
16
MIXQOUTP
O
Mixer Q output: positive terminal (test pin)
17
MIXQOUTN
O
Mixer Q output: negative terminal (test pin)
18
NC
19
NC
20
REXT
21
VCCBIAS
Bias block power supply
22
GNDBIAS
Bias block ground
23
NC
24
VCM
25
VCCBBQ
26
GND
27
BBQOUTN
O
Baseband Q (in quadrature) output: negative terminal
28
BBQOUTP
O
Baseband Q (in quadrature) output: positive terminal
29
VCCLO
30
LOIN
I
Local oscillator input: negative terminal
31
LOIP
I
Local oscillator input: positive terminal
32
GND
33
BBIOUTN
O
Baseband I (in-phase) output: positive terminal
34
BBIOUTP
O
Baseband I (in-phase) output: negative terminal
35
GND
Ground
36
VCCBBI
Baseband I (in phase) power supply
37
NC
38
READBACK
O
SPI readback data
39
Gain_B2
I
PGA fast gain control bit 2
40
Gain_B1
I
PGA fast gain control bit 1
41
Gain_B0
I
PGA fast gain control bit 0
42
NC
43
NC
44
MIXIOUTN
O
Mixer I output: negative terminal
45
MIXIOUTP
O
Mixer I output: positive terminal
46
STROBE
I
SPI enable
47
DATA
I
SPI data input
48
CLOCK
I
SPI clock input
Digital power supply
I
Chip enable
Mixer power supply
Ground
Ground
No connect
No connect
O
Reference bias external resistor
No connect
I
Baseband input common-mode voltage
Baseband Q chain power supply
Ground
Local oscillator power supply
Ground
No connect
No connect
No connect
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TYPICAL CHARACTERISTICS
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
Table of Graphs
Gain
vs LO frequency (1) (2) (3)
Figure 1, Figure 2, Figure 3
(1) (2) (3)
Figure 4, Figure 5, Figure 6
Noise figure
vs LO frequency
IIP3
vs LO frequency (4) (5) (6)
Figure 7, Figure 9, Figure 8
IIP2
vs LO frequency (4) (5) (6)
Figure 10, Figure 12, Figure 11
Gain
vs LO frequency
IIP3
vs LO frequency (5) (6)
Figure 16, Figure 17, Figure 18, Figure 19
IIP2
vs LO frequency (5) (6)
Figure 20, Figure 21, Figure 22, Figure 23
Figure 13, Figure 14, Figure 15
(3)
Noise figure
vs LO frequency
OIP3
vs Frequency offset (7) (3)
Figure 24, Figure 25, Figure 26
Noise figure
vs BB gain setting (8)
Figure 31
Gain
vs BB gain setting (8)
Figure 32
Figure 27, Figure 28, Figure 29, Figure 30
(9)
Gain
vs Frequency offset
Gain
vs Frequency offset (bypass mode) (9)
1-dB LPF corner frequency
vs LPFADJ setting
Figure 33, Figure 34
Figure 35, Figure 36
Figure 37
Relative LPF group delay
vs Frequency offset
(10)
Figure 38
Image rejection
vs BB frequency offset
Figure 39
DC offset limit
vs Temperature (11)
Out-of-band P1dB
vs Relative offset multiplier to corner frequency
Figure 40
(12)
Figure 41
(1)
Measured with broadband Picosecond 5310A balun on the LO input and single ended connection on the RF input. Performance gain
adjusted for the 3-dB differential to single-ended insertion loss.
(2) Performance ripple because of impedance mismatch on the RF input.
(3) Measured with the maximum baseband gain (BB gain) setting, unless otherwise noted.
(4) Measured with broadband Picosecond 5310A balun on the LO input and RF input. Balun insertion loss is compensated for in the
measurement.
(5) Out-of-band intercept point is defined with tones that are at least two times farther out than the programmed LPF corner frequency that
generate an intermodulation tone that falls inside the LPF passband.
(6) Out-of-band intercept point depends on the demodulator performance and not the baseband circuitry; the measurement is taken at max
gain but is valid across all PGA settings.
(7) Measured with filter in bypass mode to characterize the passband circuitry across baseband frequencies.
(8) Data taken with LO frequency = 900 MHz.
(9) Normalized gain.
(10) Relative to the low frequency offset group delay in bypass mode.
(11) Idet set to 50 µA; RF signal is off; LO at 2.4 GHz at 0 dBm; Det filter set to 1 kHz; Clk Div set to 1024.
(12) In-band tone set to 1 MHz; out-of-band jammer tone set to specified relative offset ratio from the programmed corner frequency. Jammer
tone is increased until in-band tone compresses 1 dB.
8
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TYPICAL CHARACTERISTICS
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
GAIN vs LO FREQUENCY
GAIN vs LO FREQUENCY
52
52
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
50
48
44
48
46
Gain (dB)
Gain (dB)
46
42
40
44
42
40
38
38
36
36
34
32
34
See Notes (1) and (2)
200
400
600
800
32
1000
1200
1400
1600
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
50
1800
See Notes (1) and (2)
200
400
800
1000
1200
LO Frequency (MHz)
Figure 1.
Figure 2.
GAIN vs LO FREQUENCY
1400
1600
1800
NOISE FIGURE vs LO FREQUENCY
20
52
48
46
44
42
40
38
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
18
Noise Figure (dBm)
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
50
Gain (dB)
600
LO Frequency (MHz)
16
14
12
10
36
34
32
8
See Notes (1) and (2)
200
400
600
800
6
1000
1200
1400
1600
See Notes (1) and (2)
200
1800
400
800
1000
1200
LO Frequency (Hz)
Figure 3.
Figure 4.
NOISE FIGURE vs LO FREQUENCY
1400
1600
1800
NOISE FIGURE vs LO FREQUENCY
20
20
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
18
Noise Figure (dBm)
18
Noise Figure (dBm)
600
LO Frequency (MHz)
16
14
12
10
8
16
14
12
10
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
8
See Notes (1) and (2)
6
200
400
600
800
1000
1200
1400
1600
1800
6
See Notes (1) and (2)
200
400
600
800
1000
1200
LO Frequency (Hz)
LO Frequency (Hz)
Figure 5.
Figure 6.
1400
1600
1800
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP3 vs LO FREQUENCY
IIP3 (dB)
I
36
34
32
30
28
26
24
22
20
18
16
14
12
10
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
200
400
600
800
1000
1200
1400
1600
1800
1400
1600
1800
LO Frequency (Hz)
IIP3 (dB)
Q
36
34
32
30
28
26
24
22
20
18
16
14
12
10
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
See Notes (3), (4) and (5)
200
400
600
800
1000
1200
LO Frequency (Hz)
Figure 7.
10
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP3 vs LO FREQUENCY
IIP3 (dB)
I
36
34
32
30
28
26
24
22
20
18
16
14
12
10
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
200
400
600
800
1000
1200
1400
1600
1800
LO Frequency (Hz)
IIP3 (dB)
Q
36
34
32
30
28
26
24
22
20
18
16
14
12
10
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
See Notes (3), (4) and (5)
200
400
600
800
1000
1200
1400
1600
1800
LO Frequency (Hz)
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP3 vs LO FREQUENCY
IIP3 (dB)
I
36
34
32
30
28
26
24
22
20
18
16
14
12
10
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
200
400
600
800
1000
1200
1400
1600
1800
LO Frequency (Hz)
IIP3 (dB)
Q
36
34
32
30
28
26
24
22
20
18
16
14
12
10
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
See Notes (3), (4) and (5)
200
400
600
800
1000
1200
1400
1600
1800
LO Frequency (Hz)
Figure 9.
12
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP2 vs LO FREQUENCY
I
100
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
90
IIP2 (dB)
80
70
60
50
40
30
200
400
600
800
1000
1200
1400
1600
1800
LO Frequency (Hz)
Q
100
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
90
IIP2 (dB)
80
70
60
50
40
30
See Notes (3), (4) and (5)
200
400
600
800
1000
1200
1400
1600
1800
LO Frequency (Hz)
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP2 vs LO FREQUENCY
I
100
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
90
IIP2 (dB)
80
70
60
50
40
30
200
400
600
800
1000
1200
1400
1600
1800
1400
1600
1800
LO Frequency (Hz)
Q
100
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
90
IIP2 (dB)
80
70
60
50
40
30
See Notes (3), (4) and (5)
200
400
600
800
1000
1200
LO Frequency (Hz)
Figure 11.
14
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP2 vs LO FREQUENCY
I
100
90
IIP2 (dB)
80
70
60
50
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
40
30
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Q
100
90
IIP2 (dB)
80
70
60
50
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
40
30
600
700
See Notes (4) and (5)
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
GAIN vs LO FREQUENCY
GAIN vs LO FREQUENCY
52
52
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
50
48
48
46
44
Gain (dB)
Gain (dB)
46
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
50
42
40
44
42
40
38
38
36
36
34
34
32
32
600
700
800
900
1000
1100
1200
600
700
800
900
1000
LO Frequency (MHz)
LO Frequency (MHz)
Figure 13.
Figure 14.
1100
1200
GAIN vs LO FREQUENCY
52
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
50
48
Gain (dB)
46
44
42
40
38
36
34
32
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 15.
16
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP3 vs LO FREQUENCY
IIP3 (dB)
I
36
34
32
30
28
26
24
22
20
18
16
14
12
10
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
IIP3 (dB)
Q
36
34
32
30
28
26
24
22
20
18
16
14
12
10
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
600
700
See Notes (4) and (5)
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP3 vs LO FREQUENCY
IIP3 (dB)
I
36
34
32
30
28
26
24
22
20
18
16
14
12
10
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
IIP3 (dB)
Q
36
34
32
30
28
26
24
22
20
18
16
14
12
10
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
600
700
See Notes (4) and (5)
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 17.
18
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP3 vs LO FREQUENCY
IIP3 (dB)
I
36
34
32
30
28
26
24
22
20
18
16
14
12
10
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
IIP3 (dB)
Q
36
34
32
30
28
26
24
22
20
18
16
14
12
10
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
See Notes (4) and (5)
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP3 vs LO FREQUENCY
IIP3 (dB)
I
36
34
32
30
28
26
24
22
20
18
16
14
12
10
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
IIP3 (dB)
Q
36
34
32
30
28
26
24
22
20
18
16
14
12
10
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
See Notes (4) and (5)
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 19.
20
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP2 vs lO FREQUENCY
I
100
90
IIP2 (dB)
80
70
60
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
50
40
30
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Q
100
90
IIP2 (dB)
80
70
60
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
50
40
30
600
700
See Notes (4) and (5)
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP2 vs LO FREQUENCY
I
100
90
IIP2 (dB)
80
70
60
50
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
40
30
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Q
100
90
IIP2 (dB)
80
70
60
50
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
40
30
600
700
See Notes (4) and (5)
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 21.
22
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP2 vs LO FREQUENCY
I
100
90
IIP2 (dB)
80
70
60
50
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
40
30
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Q
100
90
IIP2 (dB)
80
70
60
50
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
40
30
See Notes (4) and (5)
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
IIP2 vs LO FREQUENCY
I
100
90
IIP2 (dB)
80
70
60
50
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
40
30
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Q
100
90
IIP2 (dB)
80
70
60
50
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
40
30
See Notes (4) and (5)
600
700
800
900
1000
1100
1200
LO Frequency (MHz)
Figure 23.
24
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
NOISE FIGURE vs LO FREQUENCY
NOISE FIGURE vs LO FREQUENCY
20
20
TA = -40°C
TA = -10°C
TA = +25°C
TA = +85°C
16
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
18
Noise Figure (dBm)
Noise Figure (dBm)
18
14
12
10
8
16
14
12
10
8
See Notes (1) and (2)
6
600
700
See Notes (1) and (2)
6
800
900
1000
1100
1200
600
700
800
900
1000
LO Frequency (Hz)
LO Frequency (Hz)
Figure 24.
Figure 25.
NOISE FIGURE vs LO FREQUENCY
38
TA = -40°C
TA = +25°C
TA = +85°C
36
18
34
16
OIP3 (dBVRMS)
Noise Figure (dBm)
1200
OIP3 vs FREQUENCY OFFSET
20
14
12
10
LO Pwr = -3 dBm
LO Pwr = 0 dBm
LO Pwr = 3 dBm
LO Pwr = 6 dBm
8
See Notes (1) and (2)
6
32
30
28
26
24
22
See Note (6)
20
600
700
800
900
1000
1100
1200
5
0
10
15
20
LO Frequency (Hz)
Frequency Offset (MHz)
Figure 26.
Figure 27.
OIP3 vs FREQUENCY OFFSET
25
OIP3 vs FREQUENCY OFFSET
38
38
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
36
34
BB Gain = 12 dB
BB Gain = 16 dB
BB Gain = 20 dB
BB Gain = 24 dB
36
34
32
OIP3 (dBVRMS)
OIP3 (dBVRMS)
1100
30
28
26
24
32
30
28
26
24
22
22
See Note (6)
20
0
5
See Note (6)
20
10
15
20
25
0
5
10
15
Frequency Offset (MHz)
Frequency Offset (MHz)
Figure 28.
Figure 29.
20
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
OIP3 vs FREQUENCY OFFSET
NOISE FIGURE vs BB GAIN SETTING
28
38
3-dB Attn On
3-dB Attn Off
3-dB Attn On
3-dB Attn Off
36
25
Noise Figure (dB)
OIP3 (dBVRMS)
34
32
30
28
26
24
22
19
16
22
See Note (6)
20
13
5
0
10
15
20
0
25
2
4
6
8
10
12
14
Frequency Offset (MHz)
BB Gain Setting
Figure 30.
Figure 31.
16
18
20
22
24
GAIN vs BB GAIN SETTING
43
GAIN vs FREQUENCY OFFSET
3-dB Attn On
3-dB Attn Off
40
20
37
0
31
-20
28
Gain (dB)
Gain (dB)
34
25
22
19
-40
-60
16
13
-80
0
2
4
6
8
10
12
14
16
18
20
22
24
BB Gain Setting
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
-100
0.1
1
10
Frequency Offset (MHz)
Figure 32.
GAIN vs FREQUENCY OFFSET
GAIN vs FREQUENCY OFFSET
3
20
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
0
-20
1
Gain (dB)
Gain (dB)
2
0
-1
-40
-60
-2
-3
-80
-4
-5
0.1
1
10
Frequency Offset (MHz)
100
Filter Ctrl 0
Filter Ctrl 1
Filter Ctrl 2
Filter Ctrl 3
-100
0.1
G036
Figure 34.
26
G035
Figure 33.
5
4
100
1
10
100
Frequency Offset (MHz)
1000
G037
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 5 V, LO power = 0 dBm, and TA = +25°C, using balun Murata LDB21897M005C-001 (unless otherwise noted).
1-dB LPF CORNER FREQUENCY vs LPFADJ SETTING
GAIN vs FREQUENCY OFFSET
16
5
3
1-dB LPF Corner Frequency (MHz)
Filter Ctrl 0
Filter Ctrl 1
Filter Ctrl 2
Filter Ctrl 3
4
Gain (dB)
2
1
0
-1
-2
-3
-4
14
12
10
8
6
4
2
0
-5
0.1
1
10
Frequency Offset (MHz)
0
100
50
100
150
LPFADJ Setting
G038
Figure 36.
250
G039
Figure 37.
RELATIVE LPF GROUP DELAY vs FREQUENCY OFFSET
IMAGE REJECTION vs BB FREQUENCY OFFSET
500
0
See Note 8
Bypass
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
400
300
-10
Image Rejection (dB)
Relative LPF Group Delay (ns)
200
200
100
0
-20
-30
-40
-50
-100
0.1
1
10
Frequency Offset (MHz)
-60
-25
100
-20
-15
-10
-5
0
5
10
BB Frequency Offset (MHz)
G040
Figure 38.
15
20
25
G041
Figure 39.
OUT-OF-BAND P1dB vs RELATIVE OFFSET MULTIPLIER
TO CORNER FREQUENCY
15
DC OFFSET LIMIT vs TEMPERATURE
60
Out-of-Band P1dB (dBm)
See Note 9
40
DC Offset Limit (mV)
See Note (9)
10
20
0
-20
5
0
-5
-10
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
-15
-20
-25
-40
0
-60
-45 -35 -25 -15 -5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Relative Offset Multiplier to Corner Frequency
5 15 25 35 45 55 65 75 85
Temperature (°C)
G042
Figure 40.
Figure 41.
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REGISTER INFORMATION
SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION
The TRF371109 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift
register. There are three signals that must be applied: CLOCK (pin 48), serial DATA (pin 47), and STROBE (pin
46). DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of CLOCK. STROBE is asynchronous
to CLOCK, and at its rising edge the data in the shift register is loaded into the selected internal register. The first
two bits (DB0–DB1) are the address to select the available internal registers.
READBACK Mode
The TRF371109 implements the capability to read back the content of the serial programming interface registers.
In addition, it is possible to read back the status of the internal DAC registers that are automatically set after an
auto dc-offset calibration. Each readback is composed by two phases: writing followed by the actual reading of
the internal data (refer to Figure 42).
During the writing phase, a command is sent to the TRF371109 to set it in readback mode and to specify which
register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into
the READBACK pin and can be read at the following falling edge (LSB first). The first clock after LE goes high
(end of writing cycle) is idle, and the following 32 clock pulses transfer the internal register content to the
READBACK pin.
tSU1
Register Write
CLOCK
DATA
t(CLK)
tH
tCL
tCH
1st
Write
CLOCK
Pulse
DB0 (LSB)
Address Bit 0
32nd
Write
CLOCK
Pulse
DB1
Address Bit 1
DB3
Address Bit 3
DB2
Address Bit 2
DB30
DB29
READBACK DATA READBACK DATA
Bit 30
Bit 29
DB31 (MSB)
READBACK DATA
Bit 31
tSU2
tW
End of Write
Cycle Pulse
Latch
Enable
CLOCK
READBACK
tSU2
32nd
Write
CLOCK
Pulse
1st
Read
CLOCK
Pulse
tW
2nd
Read
CLOCK
Pulse
32nd
Read
CLOCK
Pulse
33rd
Read
CLOCK
Pulse
tD
STROBE
End of Write
Cycle Pulse
READBACK
Data Bit 0
READBACK
DATA
READ
BACK
Data
Bit 1
READ
BACK
Data
Bit 29
READBACK
Data Bit 30
READBACK
Data Bit 31
Figure 42. Serial Programming Timing Diagram
Table 1 shows the register summary. Table 2 through Table 6 list the device setup information for Register 1 to
Register 5, respectively. Table 7 lists the device setup for Register 0.
28
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Table 1. Register Summary (1)
Bit #
Reg 1
Reg 2
Bit #
Bit0
Bit1
Register address
Register address
Bit1
Bit2
Reg 5
Bit3
SPI bank addr
SPI bank addr
Bit5
PWD RF
En auto-cal
Bit6
NU
Bit6
Bit7
PWD buf
Bit7
Bit8
P
Bit8
Bit9
NU
Bit9
Bit10
PWD DC OFF DIG
Bit11
NU
Bit4
Bit4
Register address
Register address
SPI bank addr
SPI bank addr
Mix GM trim
ILoadA
Mix LO trim
LO trim
Bit10
Bit11
Bit12
Mix buf trim
Bit12
Bit13
Bit13
Bit14
BB gain
Bit14
Bit1
ILoadB
Fltr trim
Bit3
Bit4
Bit5
Bit6
Bit9
Bit11
Bit13
Bit14
Bit17
Bit17
Bit17
Bit18
Bit18
Bit19
Bit20
Bit20
LPFADJ
Bit21
Bit22
IDet
Bit23
Bit24
Bit25
Bit26
DC detector
bandwidth
Bit27
Fast gain
Bit28
Gain sel
Bit29
Osc test
Bit30
NU
Bit31
En 3dB attn
Bit21
Bit21
Bit22
Bit22
Bit25
Cal clk sel
Bit26
NU
Bit24
Bit25
QLoadB
Bit26
Bit27
Bit27
Bit28
Bit28
Bit29
Osc trim
Bit30
Bit31
DC offset Q DAC
Bit23
Bit24
CLK div ratio
Bit16
Bit20
Bit23
Cal sel
Bit15
Bit19
QLoadA
NU
Bit12
Bit16
Bit19
ID
Bit10
Bit15
Out buf trim
SPI bank addr
Bit8
Bit16
Bit18
Register address
Bit7
Bit15
QDAC for dc offset
Reg 0
Bit2
Bit5
IDAC for dc offset
Bit #
Bit0
Bit2
Bit3
(1)
Reg 3
Bit0
Bypass
DC offset I DAC
Bit29
Bit30
Fltr ctrl
Bit31
Register 4 is not used.
Table 2. Register 1 Device Setup
REGISTER 1
NAME
RESET VALUE
Bit0
ADDR
1
WORKING DESCRIPTION
Bit1
ADDR
0
Bit2
ADDR
0
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
PWD_MIX
0
Mixer power down (Off = '1')
Bit6
NU
0
Not used
Bit7
PWD_BUF
1
Mixer out test buffer power down (Off = '1')
Bit8
PWD_FILT
0
Baseband filter power down (Off = '1')
Bit9
NU
0
Not used
Bit10
PWD_DC_OFF_DIG
1
DC offset calibration power down (Off = '1')
Register address
SPI bank address
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Table 2. Register 1 Device Setup (continued)
REGISTER 1
NAME
RESET VALUE
Bit11
NU
1
WORKING DESCRIPTION
Bit12
BBGAIN_0
1
Bit13
BBGAIN_1
1
Bit14
BBGAIN_2
1
Bit15
BBGAIN_3
1
Bit16
BBGAIN_4
0
Bit17
LPFADJ_0
0
Bit18
LPFADJ_1
0
Bit19
LPFADJ_2
0
Bit20
LPFADJ_3
0
Bit21
LPFADJ_4
0
Bit22
LPFADJ_5
0
Bit23
LPFADJ_6
0
Bit24
LPFADJ_7
1
Bit25
EN_FLT_B0
0
Bit26
EN_FLT_B1
0
Selects dc offset detector filter bandwidth.
Setting {00, 01, 11} = {10 MHz, 10 kHz, 1 kHz}
Bit27
EN_FASTGAIN
0
Enable external fast-gain control
Bit28
GAIN_SEL
0
Fast-gain control multiplier bit (×2 = 1)
Bit29
OSC_TEST
0
Enables Osc out on readback pin if = 1
Bit30
NU
0
Not used
Bit31
EN 3dB Attn
0
Enables output 3-dB attenuator
Not used
Baseband gain setting. Default = 15. Range is from 0 (minimum gain
setting) to 24 (maximum gain setting). See the Application Information
section for more information on gain setting and fast gain control
options.
Sets programmable low-pass filter corner frequency. Range = 255
(lowest corner frequency) to 0 (highest corner frequency). Default value
is 128.
EN_FLT_B0/1: These bits control the bandwidth of the detector used to measure the dc offset during the
automatic calibration. There is an RC filter in front of the detector that can be fully bypassed. EN_FLT_B0
controls the resistor (bypass = 1), while EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff
frequencies of the detector bandwidth are summarized in Table 3 (see the Application Information section for
more detail on the dc offset calibration and the detector bandwidth).
Table 3. Detector Bandwidth Settings
EN_FLT_B1
EN_FLT_B0
TYPICAL 3-dB CUTOFF FREQ
x
0
10 MHz
Maximum bandwidth, bypass R, C
NOTES
0
1
10 kHz
Enable R
1
1
1 kHz
Minimum bandwidth, enable R, C
Table 4. Register 2 Device Setup
30
REGISTER 2
NAME
RESET VALUE
Bit0
ADDR
0
Bit1
ADDR
1
Bit2
ADDR
0
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
EN_AUTOCAL
0
WORKING DESCRIPTION
Register address
SPI bank address
Enable autocal when = '1'; reset to '0' when done.
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Table 4. Register 2 Device Setup (continued)
REGISTER 2
NAME
RESET VALUE
Bit6
IDAC_BIT0
0
WORKING DESCRIPTION
Bit7
IDAC_BIT1
0
Bit8
IDAC_BIT2
0
Bit9
IDAC_BIT3
0
Bit10
IDAC_BIT4
0
Bit11
IDAC_BIT5
0
Bit12
IDAC_BIT6
0
Bit13
IDAC_BIT7
1
Bit14
QDAC_BIT0
0
Bit15
QDAC_BIT1
0
Bit16
QDAC_BIT2
0
Bit17
QDAC_BIT3
0
Bit18
QDAC_BIT4
0
Bit19
QDAC_BIT5
0
Bit20
QDAC_BIT6
0
Bit21
QDAC_BIT7
1
Bit22
IDET_B0
1
Bit23
IDET_B1
1
Set reference current for digital calibration; Settings {00 to 11}
= {50 µA to 200 µA}. Setting '00' = highest resolution.
Bit24
CAL_SEL
1
DC offset calibration select. '0' = manual cal; '1' = autocal.
Bit25
Clk_div_ratio
0
Bit26
Clk_div_ratio
0
Bit27
Clk_div_ratio
0
Bit28
Cal_clk_sel
1
Bit29
Osc_trim
1
Bit30
Osc_trim
1
Bit31
Osc_trim
0
I-DAC bits to be set during manual dc offset cal
Q-DAC bits to be set during manual dc offset cal
Clk divider ratio. Setting {000 to 111} = {1, 8, 16, 128, 256, 1024, 2048,
16684}. A higher div ratio (slower clk) improves cal accuracy and
reduces speed.
Select internal oscillator when 1, SPI clk when '0'
Internal oscillator frequency trimming; Setting {000} = ~300 kHz;
Setting {111} = ~1.8 MHz. Nominal setting {110} = ~900 kHz.
Table 5. Register 3 Device Setup
REGISTER 3
NAME
RESET VALUE
Bit0
ADDR
1
Bit1
ADDR
1
Bit2
ADDR
0
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
ILOAD_a
0
Bit6
ILOAD_a
0
Bit7
ILOAD_a
0
Bit8
ILOAD_a
0
Bit9
ILOAD_a
0
Bit10
ILOAD_a
0
Bit11
ILOAD_b
0
Bit12
ILOAD_b
0
Bit13
ILOAD_b
0
Bit14
ILOAD_b
0
Bit15
ILOAD_b
0
Bit16
ILOAD_b
0
WORKING DESCRIPTION
Register address
SPI bank address
I mixer offset side A
I mixer offset side B
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Table 5. Register 3 Device Setup (continued)
REGISTER 3
NAME
RESET VALUE
Bit17
QLOAD_a
0
WORKING DESCRIPTION
Bit18
QLOAD_a
0
Bit19
QLOAD_a
0
Bit20
QLOAD_a
0
Bit21
QLOAD_a
0
Bit22
QLOAD_a
0
Bit23
QLOAD_b
0
Bit24
QLOAD_b
0
Bit25
QLOAD_b
0
Bit26
QLOAD_b
0
Bit27
QLOAD_b
0
Bit28
QLOAD_b
0
Bit29
Bypass
0
Engage filter bypass
Bit30
Fltr Ctrl_b
1
Bit31
Fltr Ctrl_b
0
Used to adjust for filter peaking response; set to 0 in bypass mode, 1
otherwise
Q mixer offset side A
Q mixer offset side B
I/Q Mixer Load A/B: these bits adjust the load on the mixer output. All values should be 0. No modification is
necessary.
Register 4: No programming required for Register 4.
Table 6. Register 5 Device Setup
32
REGISTER 5
NAME
RESET VALUE
Bit0
ADDR
1
Bit1
ADDR
0
Bit2
ADDR
1
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
MIX_GM_TRIM
1
Bit6
MIX_GM_TRIM
0
Bit7
MIX_LO_TRIM
1
Bit8
MIX_LO_TRIM
0
Bit9
LO_TRIM
1
Bit10
LO_TRIM
0
Bit11
MIX_BUFF_TRIM
1
Bit12
MIX_BUFF_TRIM
0
Bit13
FLTR_TRIM
1
Bit14
FLTR_TRIM
0
Bit15
OUT_BUFF_TRIM
1
Bit16
OUT_BUFF_TRIM
0
WORKING DESCRIPTION
Register address
SPI bank address
Mixer gm current trim
Mixer switch core VCM trim
LO buffers current trim
Mixer output buffer current trim
Filter current trim
Filter output buffer current trim
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Table 6. Register 5 Device Setup (continued)
REGISTER 5
NAME
RESET VALUE
Bit17
0
Bit18
0
Bit19
0
Bit20
0
Bit21
0
Bit22
0
Bit23
0
Bit24
NU
0
Bit25
0
Bit26
0
Bit27
0
Bit28
0
Bit29
0
Bit30
0
Bit31
0
WORKING DESCRIPTION
Not used
Readback (Write Command)
0
0
0
1
0
Zero Fill
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Zero fill
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit13
Bit14
Register address
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit15
1
Bit28
Bit29
Bit30
Bit31
Bit12
Bit13
Bit14
Bit15
Bit29
Bit30
Bit31
Reg 0:DAC/Device ID Readback
Register Address
Bit0
Bit1
SPI Bank Addr
Bit2
Bit3
Bit4
ID
Bit5
NU
DC offset Q DAC
Bit16
Bit17
Bit18
Bit19
Bit20
DC offset I DAC
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Table 7. Register 0 Device Setup (Read-Only)
READBACK REGISTER
NAME
RESET VALUE
Bit0
ADDR
0
Bit1
ADDR
0
Bit2
ADDR
0
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
ID
1
Bit6
ID
0
Bit7
0
Bit8
0
Bit9
0
Bit10
Bit11
WORKING DESCRIPTION
Select SPI register 1 to 5
Select SPI bank 1 to 3
Version ID: 01 = –25
0
NU
0
Bit12
0
Bit13
0
Bit14
0
Bit15
0
Not used
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Table 7. Register 0 Device Setup (Read-Only) (continued)
34
READBACK REGISTER
NAME
RESET VALUE
Bit16
DC_OFFSET_Q
0
Bit17
DC_OFFSET_Q
0
Bit18
DC_OFFSET_Q
0
Bit19
DC_OFFSET_Q
0
Bit20
DC_OFFSET_Q
0
Bit21
DC_OFFSET_Q
0
Bit22
DC_OFFSET_Q
0
Bit23
DC_OFFSET_Q
1
Bit24
DC_OFFSET_I
0
Bit25
DC_OFFSET_I
0
Bit26
DC_OFFSET_I
0
Bit27
DC_OFFSET_I
0
Bit28
DC_OFFSET_I
0
Bit29
DC_OFFSET_I
0
Bit30
DC_OFFSET_I
0
Bit31
DC_OFFSET_I
1
WORKING DESCRIPTION
DC offset DAC Q register
DC offset DAC I register
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APPLICATION INFORMATION
Gain Control
The TRF371109 integrates a baseband programmable gain amplifier (PGA) that provides 24 dB of gain range
with 1-dB steps. The PGA gain is controlled through SPI by a 5-bit word (register 1 bits). Alternatively,
the PGA can be programmed by a combination of five bits programmed through the SPI and three parallel
external bits (pins Gain_B2, Gain_B1, Gain_B0). The external bits are used to reduce the PGA setting quickly
without having to reprogram the SPI registers. The fast gain control multiplier bit (register 1, bit 28) sets the step
size of each bit to either 1 dB or 2 dB. This configuration allows a fast gain reduction of 0 dB to 7 dB in 1-dB
steps or 0 dB to 14 dB in 2-dB steps.
The PGA gain control word (BBgain) can be programmed to a setting between 0 and 24. This word is the
SPI programmed gain (register 1 bits) minus the parallel external three bits, as shown in Figure 43. Note
that the PGA gain setting rails at 0 and does not go any lower. Typical applications set the nominal PGA gain
setting to 17 and use the fast gain control bits to protect the analog-to-digital converter (ADC) in the event of a
strong input jammer signal.
SPI
Composite
PGA Setting
(min: 0, max 24)
+
Gain_B1
Gain_B0
Gain_B2
X
(x1, x2)
Fast Gain Select
Figure 43. PGA Gain Control Word
For example, if a PGA gain setting of 19 is desired, then the SPI can be programmed directly to a value of 19.
Alternatively, the SPI gain register can be programmed to 24 and the parallel external bits set to '101' (binary),
corresponding to 5-dB reduction.
Automated DC Offset Calibration
The TRF371109 provides an automatic calibration procedure for adjusting the dc offset in the baseband I/Q
paths. The internal calibration requires a clock in order to function. The TRF371109 can use the internal
relaxation oscillator or the external SPI clock. Using the internal oscillator is the preferred method, which is
selected by setting the Cal_Sel_Clk (register 2, bit 28) to '1'. The internal oscillator frequency is set through the
Osc_Trim bits (register 2, bits ). The oscillator frequency is detailed in Table 8.
Table 8. Internal Oscillator Frequency Control
OSC_TRIM
OSC_TRIM
OSC_TRIM
FREQUENCY
0
0
0
300 kHz
0
0
1
500 kHz
0
1
0
700 kHz
0
1
1
900 kHz
1
0
0
1.1 MHz
1
0
1
1.3 MHz
1
1
0
1.5 MHz
1
1
1
1.8 MHz
The default settings of these registers correspond to a 900-kHz oscillator frequency. This frequency is sufficient
for auto calibration and does not need to be modified.
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The output full-scale range of the internal dc offset correction digital-to-analog converters (DACs) is
programmable (IDET_B
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