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TRS202E
SLLS847E – JULY 2007 – REVISED NOVEMBER 2016
TRS202E 5-V Dual RS-232 Line Driver and Receiver With ±15-kV IEC ESD Protection
1 Features
3 Description
•
The TRS202E device consists of two line drivers, two
line receivers, and a dual charge-pump circuit.
TRS202E has IEC61000-4-2 (Level 4) ESD
protection pin-to-pin (serial-port connection pins,
including GND). The device meets the requirements
of TIA/EIA-232-F and provides the electrical interface
between an asynchronous communication controller
and the serial-port connector. The charge pump and
four small external capacitors allow operation from a
single 5-V supply. The device operates at data
signaling rates up to 120 kbit/s and a maximum of
30-V/µs driver output slew rate.
1
•
•
•
•
•
IEC61000-4-2 (Level 4) ESD Protection for
RS-232 Bus Pins:
– ±8-kV Contact Discharge
– ±15-k-V Air-Gap Discharge
– ±15-kV Human-Body Model
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
Operates at 5-V VCC Supply
Operates Up to 120 kbit/s
External Capacitors: 4 × 0.1 µF or 4 × 1 µF
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
Battery-Powered Systems
Notebooks
Laptops
Set-Top Boxes
Hand-Held Equipment
PACKAGE
BODY SIZE (NOM)
TRS202ECD
TRS202EID
SOIC (16)
9.90 mm × 3.91 mm
TRS202ECDW
TRS202EIDW
SOIC (16)
10.30 mm × 7.50 mm
TRS202ECN
TRS202EIN
PDIP (16)
19.30 mm × 6.35 mm
TRS202ECPW
TRS202EIPW
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
POWER
5V
DIN
2
2
TX
120 kb/s
2
ROUT
IEC61000-4-2
2
RX
DOUT
RS-232
RIN
RS-232
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TRS202E
SLLS847E – JULY 2007 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
4
4
4
5
5
5
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Electrical Characteristics: Driver ...............................
Electrical Characteristics: Receiver ..........................
Switching Characteristics: Driver ..............................
Switching Characteristics: Receiver..........................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
8
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (November 2012) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
•
Changed Package thermal impedance, RθJA, values in Thermal Information table From: 73°C/W To: 76.7°C/W (D),
From: 57°C/W To: 77.1°C/W (DW), From: 67°C/W To: 44.1°C/W (N), and From: 108°C/W To: 101.7°C/W (PW)............... 5
Changes from Revision C (May 2010) to Revision D
•
2
Page
Fixed IOS values typo in Electrical Characteristics table, changed – to ±............................................................................... 5
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SLLS847E – JULY 2007 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
C1+
1
16
VCC
V+
2
15
GND
C1–
3
14
DOUT1
C2+
4
13
RIN1
C2–
5
12
ROUT1
V–
6
11
DIN1
DOUT2
7
10
DIN2
RIN2
8
9
ROUT2
Not to scale
Pin Functions
PIN
NO.
1
NAME
C1+
I/O
DESCRIPTION
—
Positive lead of C1 capacitor
2
V+
O
Positive charge pump output for storage capacitor only
3
C1–
—
Negative lead of C1 capacitor
4
C2+
—
Positive lead of C2 capacitor
5
C2–
—
Negative lead of C2 capacitor
6
V–
O
Negative charge pump output for storage capacitor only
7
DOUT2
O
RS-232 line data output (to remote RS-232 system)
8
RIN2
I
RS-232 line data input (from remote RS-232 system)
9
ROUT2
O
Logic data output (to UART)
10
DIN2
I
Logic data input (from UART)
11
DIN1
I
Logic data input (from UART)
12
ROUT1
O
Logic data output (to UART)
13
RIN1
I
RS-232 line data input (from remote RS-232 system)
14
DOUT1
O
RS-232 line data output (to remote RS-232 system)
15
GND
—
Ground
16
VCC
—
Supply voltage, connect to external 5-V power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Supply voltage, VCC (2)
Positive charge pump voltage, V+
(2)
Negative charge pump voltage, V–
Drivers
Input voltage, VI
MIN
MAX
UNIT
–0.3
6
V
VCC – 0.3
14
V
–14
0.3
V
–0.3
V+ + 0.3
Receivers
Drivers
Output voltage, VO
Receivers
V– – 0.3
V+ + 0.3
–0.3
VCC + 0.3
Short-circuit duration, DOUT
Storage temperature, Tstg
(2)
V
Continuous
Operating virtual junction temperature, TJ
(1)
V
±30
–65
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network GND.
6.2 ESD Ratings
VALUE
Human-body model (HBM),
per ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
Electrostatic discharge
Pins 7, 8, 13, 14, 15
±15000
All other pins
±2000
Charged-device model (CDM),
per JEDEC specification JESD22-C101 (2)
All pins
±1500
IEC 61000-4-2 contact discharge
Pins 7, 8, 13, 14, 15
±8000
IEC 61000-4-2 air-gap discharge
Pins 7, 8, 13, 14, 15
±15000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
see Figure 9 (1)
Supply voltage
VIH
Driver high-level input voltage (DIN)
VIL
Driver low-level input voltage (DIN)
VI
TA
(1)
4
MIN
NOM
MAX
4.5
5
5.5
2
Receiver input voltage
TRS202EC
Operating free-air temperature
TRS202EI
V
V
0.8
Driver input voltage (DIN)
UNIT
0
5.5
–30
30
0
70
–40
85
V
V
°C
Test conditions are C1 to C4 = 0.1 µF at VCC = 5 V ±0.5 V.
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6.4 Thermal Information
TRS202E
THERMAL METRIC (1)
D (SOIC)
DW (SOIC)
N (PDIP)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
101.7
°C/W
RθJA
Junction-to-ambient thermal resistance
76.7
77.1
44.1
RθJC(top)
Junction-to-case (top) thermal resistance
37.4
39.9
30.8
37
°C/W
RθJB
Junction-to-board thermal resistance
34.2
41.8
24.2
46.6
°C/W
ψJT
Junction-to-top characterization parameter
7
12.9
15.2
2.8
°C/W
ψJB
Junction-to-board characterization parameter
33.9
41.3
24
46
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted; see Figure 9) (1)
PARAMETER
ICC
TEST CONDITIONS
Supply current
(1)
(2)
MIN
No load, VCC = 5 V
TYP (2)
MAX
8
15
UNIT
mA
Test conditions are C1 to C4 = 0.1 µF at VCC = 5 V + 0.5 V.
All typical values are at VCC = 5 V and TA = 25°C.
6.6 Electrical Characteristics: Driver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 9) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
MAX
UNIT
VOH
High-level output voltage
DOUT at RL = 3 kΩ to GND, DIN = GND
5
9
VOL
Low-level output voltage
DOUT at RL = 3 kΩ to GND, DIN = VCC
–5
–9
IIH
High-level input current
VI = VCC
15
200
µA
Low-level input current
VI at 0 V
–15
–200
µA
Short-circuit output current
VCC = 5.5 V and VO = 0 V
±10
±60
mA
Output resistance
VCC, V+, V– = 0 V, and VO = ±2 V
IIL
IOS
(3)
ro
(1)
(2)
(3)
V
V
300
Ω
Test conditions are C1 to C4 = 0.1 µF at VCC = 5 V + 0.5 V.
All typical values are at VCC = 5 V and TA = 25°C.
Short-circuit durations must be controlled to prevent exceeding the device absolute power-dissipation ratings, and not more than one
output must be shorted at a time.
6.7 Electrical Characteristics: Receiver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted; see Figure 9) (1)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –1 mA
VOL
Low-level output voltage
IOL = 1.6 mA
VIT+
Positive-going input threshold voltage
VCC = 5 V and TA = 25°C
VIT–
Negative-going input threshold voltage
VCC = 5 V and TA = 25°C
Vhys
Input hysteresis (VIT+ – VIT–)
ri
Input resistance
(1)
(2)
VI = ±3 V to ±25 V
MIN
TYP (2)
3.5
VCC – 0.4
1.7
MAX
UNIT
V
0.4
V
2.4
V
0.8
1.2
0.2
0.5
1
V
V
3
5
7
kΩ
Test conditions are C1 to C4 = 0.1 µF at VCC = 5 V + 0.5 V.
All typical values are at VCC = 5 V and TA = 25°C.
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6.8 Switching Characteristics: Driver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted; see Figure 9) (1)
PARAMETER
TYP (2)
TEST CONDITIONS
MIN
Maximum data rate
CL = 50 to 1000 pF, one DOUT switching, and RL =
3 kΩ to 7 kΩ (see Figure 6)
120
tPLH(D)
Propagation delay time, low- to highlevel output
CL = 2500 pF, all drivers loaded, and RL = 3 kΩ
(see Figure 6)
2
µs
tPHL(D)
Propagation delay time, high- to lowlevel output
CL = 2500 pF, all drivers loaded, and RL = 3 kΩ
(see Figure 6)
2
µs
tsk(p)
Pulse skew (3)
CL = 150 to 2500 pF and RL = 3 kΩ to 7 kΩ (see
Figure 7)
300
ns
SR(tr)
Slew rate, transition region
CL = 50 to 1000 pF, VCC = 5 V, and RL = 3 kΩ to 7
kΩ (see Figure 6)
(1)
(2)
(3)
MAX
UNIT
kbit/s
3
6
30
V/µs
Test conditions are C1 to C4 = 0.1 µF at VCC = 5 V + 0.5 V.
All typical values are at VCC = 5 V and TA = 25°C.
Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
6.9 Switching Characteristics: Receiver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted; see Figure 8) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
MAX
UNIT
tPLH(R)
Propagation delay time, low- to high-level output
CL = 150 pF
0.5
10
µs
tPHL(R)
Propagation delay time, high- to low-level output
CL = 150 pF
0.5
10
µs
tsk(p)
(1)
(2)
(3)
Pulse skew
(3)
300
ns
Test conditions are C1 to C4 = 0.1 µF at VCC = 5 V + 0.5 V.
All typical values are at VCC = 5 V and TA = 25°C.
Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
6.10 Typical Characteristics
0.7
5
0.6
4.8
0.5
4.6
ROUT Voltage (V)
ROUT Voltage (V)
TA = 25°C (unless otherwise noted)
0.4
0.3
0.2
0.1
4.4
4.2
4
3.8
0
3.6
0
1
2
3
4
5
6
7
ROUT Current (mA)
8
9
10
0
D001
Figure 1. Receiver VOL vs Output Current
6
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1
2
3
4
5
6
7
ROUT Current (mA)
8
9
10
D002
Figure 2. Receiver VOH vs Output Current
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
-2
10
9
DOUT Voltage (V)
DOUT Voltage (V)
-4
-6
-8
8
7
6
5
4
-10
3
0
1
2
3
4
5
6
7
DOUT Current (mA)
8
9
10
0
1
2
3
4
5
6
7
DOUT Current (mA)
D003
Figure 3. Driver VOL vs Output Current
8
9
10
D004
Figure 4. Driver VOH vs Output Current
15
DIN
DOUT
ROUT
12
Waveform (V)
9
6
3
0
-3
-6
-9
-12
0
2
4
6
8
10
Time (us)
12
14
16
18
D005
Figure 5. Driver and Receiver Loopback Waveforms
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7 Parameter Measurement Information
3V
Input
Generator
(see Note B)
1.5 V
RS-232
Output
50 W
RL
1.5 V
0V
tTHL (D)
CL
(see Note A)
Output
tTLH (D)
3V
3V
–3 V
–3 V
TEST CIRCUIT
SR(tf) =
6V
tTHL(D) or tTLH(D)
VOH
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 W, 50% duty cycle, tr £ 10 ns, tf £ 10 ns.
Figure 6. Driver Slew Rate
3V
Generator
(see Note B)
RS-232
Output
50 W
RL
Input
1.5 V
1.5 V
0V
CL
(see Note A)
tPHL (D)
tPLH (D)
VOH
50%
50%
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 W, 50% duty cycle, tr £ 10 ns, tf £ 10 ns.
Figure 7. Driver Pulse Skew
Input
Generator
(see Note B)
3V
1.5 V
1.5 V
-3 V
Output
50 W
CL
(see Note A)
tPHL (R)
tPLH (R)
VOH
50%
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 W, 50% duty cycle, tr £ 10 ns, tf £ 10 ns.
Figure 8. Receiver Propagation Delay Times
8
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8 Detailed Description
8.1 Overview
The TRS202E device is a dual driver and receiver that includes a capacitive voltage generator using four
capacitors to supply TIA/EIA-232-F voltage levels from a single 5-V supply. All RS-232 pins have 15-kV HBM
and IEC61000-4-2 Air-Gap discharge protection. RS-232 pins also have 8-kV IEC61000-4-2 contact discharge
protection. Each receiver converts TIA/EIA-232-F inputs to 5-V TTL/CMOS levels. These receivers have shorted
and open fail safe. The receiver can accept up to ±30-V inputs and decode inputs as low as ±3 V. Each driver
converts TTL/CMOS input levels into TIA/EIA-232-F levels. Outputs are protected against shorts to ground.
8.2 Functional Block Diagram
POWER
5V
DIN
2
2
TX
RS-232
120 kb/s
2
ROUT
DOUT
IEC61000-4-2
2
RX
RIN
RS-232
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Power
The power block increases and inverts the 5-V supply for the RS-232 driver using a charge pump that requires
four 0.1-µF or 1-µF external capacitors.
8.3.2 RS-232 Driver
Two drivers interface standard logic levels to RS-232 levels. The driver inputs do not have internal pullup
resistors. Do not float the driver inputs.
8.3.3 RS-232 Receiver
Two Schmitt trigger receivers interface RS-232 levels to standard logic levels. Each receiver has an internal 5-kΩ
load to ground. An open input results in a high output on ROUT.
8.4 Device Functional Modes
8.4.1 VCC Powered by 5 V
The device is in normal operation when powered by 5 V.
8.4.2 VCC Unpowered
When TRS202E is unpowered, it can be safely connected to an active remote RS-232 device.
8.4.3 Truth Tables
Table 1 and Table 2 list the function for each driver and receiver (respectively).
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Table 1. Function Table for Each Driver (1)
(1)
INPUT
DIN
OUTPUT
DOUT
L
H
H
L
H = high level, L = low level
Table 2. Function Table for Each Receiver (1)
(1)
10
INPUT
RIN
OUTPUT
ROUT
L
H
H
L
Open
H
H = high level, L = low level,
Open = input disconnected or connected driver off
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
For proper operation, add capacitors as shown in Figure 9. Pins 9 through 12 connect to UART or general
purpose logic lines. RS-232 lines on pins 7, 8, 13, and 14 connect to a connector or cable.
9.2 Typical Application
Two driver and two receiver channels are supported for full duplex transmission with hardware flow control. The
two 5kΩ-resistors are internal to the TRS202E.
1
C1 +
†
C3 +
0.1 mF,
–
0.1 mF
6.3 V
–
16 V
VCC
C1+
16
+ CBYPASS
– = 0.1 mF,
2
3
V+
GND
15
14
C1–
DOUT1
13
4
C2
0.1 mF,
16 V
C2+
5 kW
+
–
5
C2–
12
C4
0.1 mF,
16 V
RIN1
6
–
11
V–
ROUT1
DIN1
+
DOUT2
RIN2
7
10
8
9
DIN2
ROUT2
5 kW
†
C3 can be connected to VCC or GND.
NOTES: A . Resistor values shown are nominal.
B . Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be
connected as shown.
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Figure 9. Typical Operating Circuit and Capacitor Values
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Typical Application (continued)
9.2.1 Design Requirements
• VCC minimum is 4.5 V and maximum is 5.5 V.
• Maximum recommended bit rate is 120 kbps.
9.2.2 Detailed Design Procedure
9.2.2.1 Capacitor Selection
The capacitor type used for C1 through C4 is not critical for proper operation. The TRS202E requires 0.1-µF
capacitors. 1-µF capacitors are also acceptable. TI recommends ceramic dielectrics. When using the minimum
recommended capacitor values, ensure the capacitance value does not degrade excessively as the operating
temperature varies. If in doubt, use capacitors with a larger (for example, 2×) nominal value. The capacitors'
effective series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on V+
and V–.
Bypass VCC to ground with at least 0.1 µF. In applications sensitive to power-supply noise generated by the
charge pumps, decouple VCC to ground with a capacitor the same size as (or larger than) the charge-pump
capacitors (C1 to C4).
9.2.3 Application Curves
12
DIN
DOUT
ROUT
9
Waveform (V)
6
3
0
-3
-6
-9
-12
0
2
4
6
8
10
Time (us)
12
14
16
18
D006
120 kbit/s, 1-nF load
Figure 10. Driver and Receiver Loopback Signal
12
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SLLS847E – JULY 2007 – REVISED NOVEMBER 2016
10 Power Supply Recommendations
The VCC voltage must be connected to the same power source used for logic device connected to DIN and
ROUT pins. VCC must be between 4.5 V and 5.5 V.
11 Layout
11.1 Layout Guidelines
Keep the external capacitor traces short. This is more important on C1 and C2 nodes that have the fastest rise
and fall times. Make the impedance from TRS202E ground pin and circuit board's ground plane as low as
possible for best ESD performance. Use wide metal and multiple vias on both sides of ground pin.
11.2 Layout Example
Ground
C3
1 C1+
VCC 16
VCC
PF
C1
2 V+
GND 15
3 C1-
DOUT1 14
4 C2+
RIN1 13
5 C2-
ROUT1 12
Ground
C2
Ground
6 V-
DIN1 11
7 DOUT2
DIN2 10
C4
8 RIN2
ROUT2 9
Figure 11. TRS202E Layout
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Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TRS202E
13
TRS202E
SLLS847E – JULY 2007 – REVISED NOVEMBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TRS202E
PACKAGE OPTION ADDENDUM
www.ti.com
18-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TRS202ECD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS202EC
TRS202ECDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS202EC
TRS202ECDRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS202EC
TRS202ECDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TRS202EC
TRS202ECN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TRS202ECN
TRS202ECNE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TRS202ECN
TRS202ECPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RU02EC
TRS202ECPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RU02EC
TRS202ECPWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
RU02EC
TRS202EID
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRS202EI
TRS202EIDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRS202EI
TRS202EIDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRS202EI
TRS202EIDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TRS202EI
TRS202EIN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TRS202EIN
TRS202EINE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TRS202EIN
TRS202EIPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RU02EI
TRS202EIPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RU02EI
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Mar-2016
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TRS202EIPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RU02EI
TRS202EIPWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RU02EI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Mar-2016
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Mar-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TRS202ECDR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TRS202ECDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
TRS202ECPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TRS202EIDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TRS202EIDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
TRS202EIPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Mar-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TRS202ECDR
SOIC
D
16
2500
367.0
367.0
38.0
TRS202ECDWR
SOIC
DW
16
2000
367.0
367.0
38.0
TRS202ECPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
TRS202EIDR
SOIC
D
16
2500
367.0
367.0
38.0
TRS202EIDWR
SOIC
DW
16
2000
367.0
367.0
38.0
TRS202EIPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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