Product
Folder
Order
Now
Tools &
Software
Technical
Documents
Support &
Community
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
TS3L110 Quad SPDT High-Bandwidth 10/100 Base-T LAN Switch
Differential 8-Channel to 4-Channel Multiplexer/Demultiplexer
1 Features
•
•
•
1
•
•
•
•
•
•
•
•
Wide bandwidth (BW = 500 MHz typical)
Low crosstalk (XTALK = –30 dB typical)
Bidirectional data flow with near-zero propagation
delay
Low and flat ON-state resistance
(ron = 4 Ω typical, ron(flat) = 1 Ω)
Switching on Data I/O Ports (0 to 5 V)
VCC Operating range from 3 V to 3.6 V
Ioff Supports partial power-down-mode operation
Data and control inputs have undershoot clamp
diodes
Latch-up performance exceeds 100 mA Per
JESD 78, class II
ESD Performance tested per JESD 22
– 2000-V Human-body model
(A114-B, class II)
– 1000-V Charged-device model (C101)
Suitable for both 10 Base-T and 100 Base-T
signaling
2 Applications
•
To ensure the high-impedance state during power up
or power down, E should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Device Information(1)
PART NUMBER
TS3L110
PACKAGE
9.90 mm x 3.91 mm
SSOP (DBQ) 16
4.90 mm x 3.90 mm
TVSOP (DGV) 16
3.60 mm x 4.40 mm
TSSOP (PW) 16
5.00 mm x 4.40 mm
VQFN (RGV) 16
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2
4
IA0
YA
3
YB
7
IB0
6
3 Description
The TS3L110 device can be used to replace
mechanical relays in LAN applications. This device
has low and flat ON-state resistance (ron), wide
bandwidth, and low crosstalk, making it suitable for
10/100 Base-T and various other LAN applications.
The TS3L110 device can be used to route signals
from a 10/100 Base-T Ethernet transceiver to the RJ45 LAN connectors in laptops or in docking stations.
This device is designed for low channel-to-channel
skew and low crosstalk.
YC
9
11
10
YD
12
14
13
S
IA1
5
10 and 100 Base-T signal switching
The TS3L110 local area network (LAN) switch is a 4bit 1-of-2 multiplexer/demultiplexer with a single
switch-enable (E) input. When E is low, the switch is
enabled, and the I port is connected to the Y port.
When E is high, the switch is disabled, and the highimpedance state exists between the I and Y ports.
The select (S) input controls the data path of the
multiplexer/demultiplexer.
BODY SIZE (NOM)
SOIC (D) 16
IB1
IC0
IC1
ID0
ID1
1
15
Control
Logic
E
This device is fully specified for partial-power-down
applications using Ioff. The Ioff feature ensures that
damaging current does not backflow through the
device when it is powered down. The device has
isolation during power off.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1 Absolute Maximum Ratings ....................................
6.2 ESD Ratings..............................................................
6.3 Recommended Operating Conditions .....................
6.4 Thermal Information ..................................................
6.5 Electrical Characteristics .........................................
6.6 Switching Characteristics.........................................
6.7 Dynamic Characteristics ..........................................
6.8 Typical Characteristics ..............................................
4
4
4
5
5
6
6
7
Parameter Measurement Information .................. 8
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2019) to Revision B
•
Change pin 10 to IC1, pin 11 to IC0, pin 13 to ID1, and pin 14 to ID0 in the Pin Configuration and Functions....................... 3
Changes from Original (September 2004) to Revision A
•
2
Page
Page
Added Device Information table, ESD Ratings table, Thermal Information table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
TS3L110
www.ti.com
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
5 Pin Configuration and Functions
D, DBQ, DGV, or PW Package
SOIC, SSOP, TVSOP, TSSOP 16 Pins
Top View
S
VCC
RGY Package
VQFN 16 Pins
Top View
VCC
IA0
2
15
E
IA1
3
14
ID0
YA
4
13
ID1
IB0
5
12
YD
IB1
6
11
IC0
YB
7
10
IC1
GND
8
9
YC
16
IA0
2
15
E
IA1
3
14
ID0
YA
4
13
ID1
Th ermal
Pad
5
12
YD
IB1
6
11
IC0
YB
7
10
IC1
8
IB0
GND
No t to scale
9
16
YC
1
1
S
No t to scale
Pin Functions
PIN
NAME
DESCRIPTION
NO.
S
1
Select input
IA0
2
Data I/Os
IA1
3
Data I/Os
YA
4
Data I/Os
IB0
5
Data I/Os
IB1
6
Data I/Os
YB
7
Data I/Os
GND
8
Ground (0 V) reference
YC
9
Data I/Os
IC1
10
Data I/Os
IC0
11
Data I/Os
YD
12
Data I/Os
ID1
13
Data I/Os
ID0
14
Data I/Os
E
15
Enable input
VCC
16
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
3
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
www.ti.com
6 Specifications
Absolute Maximum Ratings (1)
6.1
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.5
4.6
V
VIN
Control input voltage range
(2) (3)
–0.5
7
V
VI/O
Switch I/O voltage range (2) (3) (4)
–0.5
7
IIK
Control input clamp current
VIN < 0
II/OK
I/O port clamp current
VI/O < 0
II/O
ON-state switch current (5)
Continuous current through VCC or GND
±100
mA
VCC
Supply voltage range
D package
Package thermal impedance
θJA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
V
–50
mA
–50
mA
±128
mA
(6)
73
DBQ package (6)
90
DGV package (6)
120
PW package (6)
108
RGY package (7)
Tstg
UNIT
°C/W
39
Storage temperature range
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
6.3
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002 (2)
UNIT
±2000
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. e.
Recommended Operating Conditions (1)
MIN
MAX
VCC
Supply voltage
3
3.6
V
VIH
High-level control input voltage (E, S)
2
5.5
V
VIL
Low-level control input voltage (E, S)
0
0.8
V
VI/O
Input/output voltage
0
5.5
V
TA
Operating free-air temperature
–40
85
°C
(1)
4
UNIT
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
TS3L110
www.ti.com
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
6.4 Thermal Information
TS3L110
THERMAL METRIC (1)
D (SOIC)
DBQ (SSOP)
DGV (TVSOP)
PW (TSSOP)
RGV (VQFN)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
92.0
114.5
139.3
111.5
50.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.3
60.5
57.4
42.0
48.1
°C/W
RθJB
Junction-to-board thermal resistance
50.3
58.2
73.7
57.8
26.7
°C/W
ψJT
Junction-to-top characterization parameter
17.3
15.3
7.2
4.2
2.1
°C/W
ψJB
Junction-to-board characterization parameter
50.0
57.6
73.0
57.2
26.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
-
-
-
-
10.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Electrical Characteristics (1)
6.5
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
E, S
VCC = 3.6 V,
IIN = –18 mA
IIH
E, S
VCC = 3.6 V,
IIL
E, S
MIN
TYP (2)
MAX
UNIT
–1.8
V
VIN = 5.5 V
±1
µA
VCC = 3.6 V,
VIN = GND
±1
µA
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0
ICC
VCC = 3.6 V,
II/O = 0,
Switch ON or OFF
E, S
f = 1 MHz,
VIN = 0
I port
VI = 0,
f = 1 MHz,
Outputs open,
Y port
VI = 0,
I or Y
port
Cin
Cio(OFF)
Cio(ON)
ron
ron(flat)
(3)
Δron (4)
(1)
(2)
(3)
(4)
1
µA
0.7
1.5
mA
2.5
3.5
pF
Switch OFF
3.5
5
f = 1 MHz,
Outputs open,
Switch OFF
5.5
7
VI = 0,
f = 1 MHz,
Outputs open,
Switch ON
10.5
13
pF
VCC = 3 V,
1.25 V ≤ VI ≤ VCC,
IO = –10 mA to –30 mA
4
8
Ω
VCC = 3 V,
VI = 1.25 V and VCC,
IO = –10 mA to –30 mA
1
VCC = 3 V,
1.25 V ≤ VI ≤ VCC,
IO = –10 mA to –30 mA
0.9
pF
Ω
2
Ω
VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
ron(flat) is the difference of ron in a given channel at specified voltages.
Δron is the difference of ron in a given device.
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
5
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
6.6
www.ti.com
Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, RL = 200 Ω, CL = 10 pF
(unless otherwise noted) (see Figure 5 and Figure 6)
FROM
(INPUT)
TO
(OUTPUT)
tpd (2)
I or Y
Y or I
tPZH, tPZL
E or S
I or Y
0.5
7
ns
tPHZ, tPLZ
E or S
I or Y
0.5
5
ns
tsk(p) (3)
I or Y
Y or I
0.2
ns
PARAMETER
(1)
(2)
(3)
MIN
TYP (1)
MAX
0.25
0.1
UNIT
ns
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
Skew between opposite transitions of the same output |tPHL – tPLH|. This parameter is not production tested.
6.7
Dynamic Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
TYP (1)
TEST CONDITIONS
UNIT
XTALK
RL = 100 Ω,
f = 250 MHz,
See Figure 7
–26
OIRR
RL = 100 Ω,
f = 250 MHz,
See Figure 8
–28
dB
BW
RL = 100 Ω,
See Figure 6
500
MHz
(1)
6
dB
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
TS3L110
www.ti.com
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
6.8 Typical Characteristics
0
20
0
120
Phase
−10
−1
100
−4
−40
−5
−50
−6
−60
−20
80
−40
60
Gain
−70
−7
10
100
40
−80
20
−100
700
1
10
Frequency (MHz)
Phase at 250 MHz, 88.2 Deg
Gain −28.5 dB at 250 MHz
Phase at 627 MHz, −36 Deg
Gain −3 dB at 627 MHz
Figure 2. OFF Isolation vs Frequency
−10
160
−20
140
−30
120
−40
100
Phase
−50
80
−60
60
Gain
−70
40
−80
20
−90
10
0
700
100
Output Voltage (V)
180
Phase (Deg)
Gain (dB)
Figure 1. Gain and Phase vs Frequency
0
1
0
700
100
Frequency (MHz)
5
20
4
16
VO
3
12
2
8
rON
1
ON-State Resistance (W)
1
−60
Phase (Deg)
−3
−30
Phase (Deg)
Gain (dB)
Gain (dB)
Phase
−20
Gain
−2
0
4
Frequency (MHz)
Phase at 250 MHz, 137.92 Deg
Gain −26 dB at 250 MHZ
0
0
0
1
2
3
4
5
Input Voltage (V)
Figure 3. Crosstalk vs Frequency
Figure 4. Output Voltage and ON-State Resistance vs Input
Voltage
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
7
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
www.ti.com
7 Parameter Measurement Information
VCC
Input Generator
VIN
50 (W)
50 (W)
VG1
TEST CIRCUIT
DUT
2 x VCC
Input Generator
VO
VI
S1
RL
Open
GND
50 (W)
50 (W)
VG2
CL
(see Note A)
TEST
VCC
S1
tPLZ/tPZL
3.3 V ± 0.3 V
2 x VCC
tPHZ/tPZH
3.3 V ± 0.3 V
GND
Output Control
(VIN)
RL
VI
CL
VD
200 (W)
GND
10 pF
0.3 V
200 (W)
VCC
10 pF
0.3 V
RL
2.5 V
1.25 V
Output
Waveform 1
S1 at 2 VCC tPZL
(see Note B)
0V
tPLZ
VOH
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
1.25 V
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH − 0.3 V
VOH
VOL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low. Waveform 2 is for an output with
internal conditions such that the output is high, except when disabled by the output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPLZ and tPHH are the same as ten.
Figure 5. Test Circuit and Voltage Waveforms
8
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
TS3L110
www.ti.com
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
Parameter Measurement Information (continued)
VCC
Input Generator
VIN
50 W
50 W
VG1
TEST CIRCUIT
DUT
2 x VCC
Input Generator
RL
VO
VI
S1
Open
GND
50 W
50 W
VG2
CL
(see Note A)
RL
TEST
VCC
S1
RL
VIN
(see Note B)
CL
tsk(p)
3.3 V ± 0.3 V
GND
200 W
VCC or GND
10 pF
3.5 V
Data Input
2.5 V
1.5 V
tPLH
tPHL
VOH
(VOH + VOL)/2
VOL
Data Output
tsk(p) = tPHL − tPLH
VOLTAGE WAVEFORMS
PULSE SKEW [tsk(p)]
A.
CL includes probe and jig capacitance.
B.
Switch is ON during the measurement of tsk(p), that is, voltage at E = 0 and S = VCC or GND.
Figure 6. Test Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
9
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
www.ti.com
Parameter Measurement Information (continued)
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
VBIAS
P1
P2
VCC
YA
IA0
CL = 10 pF
(see Note A)
RL = 100 W
S
DUT
VS
E
VE
A.
CL includes probe and jig capacitance.
Figure 7. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when VS = 0, VE = 0, and YA is
the input, the output is measured at IA0. All unused analog I/O ports are left open.
HP8753ES Setup
• Average = 4
• RBW = 3 kHz
• VBIAS = 0.35 V
• ST = 2 s
• P1 = 0 dBM
10
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
TS3L110
www.ti.com
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
Parameter Measurement Information (continued)
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
VBIAS
P1
P2
VCC
YA
IA0
S
RL = 100 W
CL = 10 pF
(see Note A)
RL = 100 W
CL = 10 pF
(see Note A)
50 W
(see Note B)
VS
E
DUT
VE
YB
IB0
A.
CL includes probe and jig capacitance.
B.
A 50-Ω termination resistor is needed to match the loading of the network analyzer
Figure 8. Test Circuit for Crosstalk (XTALK)
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VS = 0, VE = 0, and YA
is the input, the output is measured at IB0. All unused analog input (Y) ports are connected to GND, and output
(I) ports are connected to GND through 50-Ω pulldown resistors.
HP8753ES Setup
• Average = 4
• RBW = 3 kHz
• VBIAS = 0.35 V
• ST = 2 s
• P1 = 0 dBM
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
11
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
www.ti.com
Parameter Measurement Information (continued)
EXT TRIGGER
BIAS
Network Analyzer
(HP8753ES)
VBIAS
P1
P2
VCC
YA
IA0
S
RL = 100 W
CL = 10 pF
(see Note A)
RL = 100 W
CL = 10 pF
(see Note A)
DUT
VS
IA1
E
VE
A.
CL includes probe and jig capacitance.
B.
A 50-Ω termination resistor is needed to match the loading of the network analyzer
50 W
(see Note B)
Figure 9. Test Circuit for OFF Isolation (OIRR)
OFF isolation is measured at the output of the OFF channel. For example, when VS = VCC, VE = 0, and YA is the
input, the output is measured at IA0. All unused analog input (Y) ports are left open, and output (I) ports are
connected to GND through 50-Ω pulldown resistors.
HP8753FS Setup
• Average = 4
• RBW = 3 kHz
• VBIAS = 0.35 V
• ST = 2 s
• P1 = 0 dBM
12
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
TS3L110
www.ti.com
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
8 Detailed Description
8.1 Overview
The TI TS3L110 LAN switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (E) input.
When E is low, the switch is enabled, and the I port is connected to the Y port. When E is high, the switch is
disabled, and the high-impedance state exists between the I and Y ports. The select (S) input controls the data
path of the multiplexer/demultiplexer.
8.2 Functional Block Diagram
2
4
IA0
YA
3
YB
7
5
IB0
6
YC
9
11
10
YD
12
14
13
S
IA1
IB1
IC0
IC1
ID0
ID1
1
Control
Logic
15
E
8.3 Feature Description
Ioff supports Partial-Power-Down Mode Operation.
The TS3L110 device ensures the signal path is high impedance state when VCC = 0 V.
8.4 Device Functional Modes
The TS3L110 supports a power down mode which reduces the current consumption of the device and places all
the signal paths in a high impedance state. To place the TS3L100 in power down mode, set the E pin with a logic
high voltage as seen in Table 1.
Table 1. Function Table
INPUTS
S
INPUT/OUTPUT
YX
FUNCTION
L
L
IX0
YX = IX0
L
H
IX1
YX = IX1
H
X
Z
Disconnect
E
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
13
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many Local Area Network (LAN) applications in which the ethernet hubs or controllers have a limited
number of I/Os or need to route signals from a single ethernet PHY to multiple ethernet jacks. The TS3L110
solution can effectively expand the limited I/Os by switching between multiple Ethernet jacks to interface them to
a single Ethernet PHY.
9.2 Typical Application
VCC
TS3L110
Processor
4
4
Ethernet
PHY
IX
YX
RJ45 Port 1
4
IX
GPIO
S
GPIO
E
RJ45 Port 2
GND
Figure 10. Typical Application Schematic
9.2.1 Design Requirements
Ensure that all of the signals passing through the switch are within the recommended operating ranges. To
ensure proper performance, see Recommended Operating Conditions.
9.2.2 Detailed Design Procedure
The TS3L110 can be properly operated without any external components. TI recommends that the digital control
pins S and E be pulled up to VCC or down to GND to avoid undesired switch positions that could result from the
floating pin. Connect the exposed thermal pad to ground.
14
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
TS3L110
www.ti.com
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
Typical Application (continued)
9.2.3 Application Curves
0
0
Phase
−10
Gain
Gain (dB)
−2
−20
−3
−30
−4
−40
−5
−50
−6
−60
Phase (Deg)
−1
−70
−7
1
10
100
700
Frequency (MHz)
Phase at 627 MHz, −36 Deg
Gain −3 dB at 627 MHz
Figure 11. Gain and Phase vs Frequency
10 Power Supply Recommendations
Power to the device is supplied through the VCC pins. TI recommends placing a bypass capacitor as close to the
supply pin (VCC) as possible to help smooth out lower frequency noise to provide better load regulation across
the frequency spectrum.
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
15
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
www.ti.com
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
TI recommends keeping the high-speed signals as short as possible.
Each via introduces discontinuities in the transmission line of the signal and increases the chance of picking
up interference from the other layers of the board. Be careful when designing test points on twisted pair lines;
through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting
holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signals because they cause signal reflections. If a stub is unavoidable, then
the stub must be less than 200 mm.
Route all high-speed signal traces over continuous GND planes, with no interruptions. Avoid crossing over
anti-etch, commonly found with plane splits.
Due to high-frequency signals, a printed-circuit board with at least four layers is recommended; two signal
layers separated by a ground and power layer as shown in Figure 12.
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer
should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground
or power plane. When running across split planes is unavoidable, sufficient decoupling must be used.
Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 12. Four-Layer Board Stackup
16
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
TS3L110
www.ti.com
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
11.2 Layout Example
VDD
To
To
To
System System System
0603
42
41
40
39
1
38
To System
2
37
To System
3
36
To System
4
35
To System
5
34
To System
6
33
To System
7
32
8
31
Exposed Center
Pad
(GND)
9
To System
10
To System
11
28
To System
12
27
To System
13
26
14
25
To System
15
24
To System
16
23
To System
17
22
19
20
To System
To System
To System
To System
To System
To System
To System
30
To System
18
To System
29
To System
To System
To System
To System
To System
To System
To System
To System
21
To
To
To
System System System
Figure 13. Layout Example
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
17
TS3L110
SCDS176B – SEPTEMBER 2004 – REVISED OCTOBER 2019
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: TS3L110
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TS3L110D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TS3L110
Samples
TS3L110DBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TK110
Samples
TS3L110DE4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TS3L110
Samples
TS3L110DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TS3L110
Samples
TS3L110DGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TK110
Samples
TS3L110DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TS3L110
Samples
TS3L110PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TK110
Samples
TS3L110PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TK110
Samples
TS3L110PWRE4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TK110
Samples
TS3L110PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TK110
Samples
TS3L110RGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TK110
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
