TUSB1210
SLLSE09J – NOVEMBER 2009 – REVISED JULY 2021
TUSB1210 Stand-Alone USB Transceiver Chip Silicon
1 Features
2 Applications
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USB2.0 PHY transceiver chip, designed to
interface with a USB controller through a ULPI
interface, fully compliant with:
– Universal serial bus specification Rev. 2.0
– On-the-go supplement to the USB 2.0
specification Rev. 1.3
– UTMI+ low pin interface (ULPI) specification
Rev. 1.1
– ULPI 12-pin SDR interface
DP/DM line external component compensation
(patent #US7965100 B1)
Interfaces to host, peripheral and OTG device
cores; optimized for portable devices or system
ASICs with built-in USB OTG device core
Complete USB OTG physical front-end that
supports host negotiation protocol (HNP) and
session request protocol (SRP)
VBUS overvoltage protection circuitry protects VBUS
pin in range –2 V to 20 V
Internal 5-V short-circuit protection of DP, DM, and
ID pins for cable shorting to VBUS pin
ULPI interface:
– I/O interface (1.8 V) optimized for
nonterminated 50 Ω line impedance
– ULPI CLOCK pin (60 MHz) supports input and
output clock configurations
– Fully programmable ULPI-compliant register set
Full industrial grade operating temperature range
from –40°C to 85°C
Available in a 32-pin quad flat no lead [QFN
(RHB)] package
Mobile phones
Portable computers
Tablet devices
Video game consoles
Desktop computers
Portable music players
3 Description
The TUSB1210 is a USB2.0 transceiver chip,
designed to interface with a USB controller through
a ULPI interface. The device supports all USB2.0
data rates (high-speed 480 Mbps, full-speed 12 Mbps,
and low-speed 1.5 Mbps), and is compliant to both
host and peripheral modes. The device additionally
supports a UART mode and legacy ULPI serial
modes. TUSB1210 also supports the OTG (Ver1.3)
optional addendum to the USB 2.0 Specification,
including HNP and SRP.
The DP/DM external component compensation in the
transmitter compensates for variations in the series
impendence in order to match with the data line
impedance and the receiver input impedance, to limit
data reflections and thereby improve eye diagrams.
Device Information(1)
PART NUMBER
TUSB1210
(1)
PACKAGE
BODY SIZE (NOM)
VQFN (32)
5.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
TUSB1210
(PHY)
ULPI Interface
USB 2.0
LINK
USB 2.0 HOST,
OTG, or Device
Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB1210
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SLLSE09J – NOVEMBER 2009 – REVISED JULY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Analog I/O Electrical Characteristics...........................7
6.6 Digital I/O Electrical Characteristics............................7
6.7 Digital IO Pins (Non-ULPI).......................................... 7
6.8 PHY Electrical Characteristics.................................... 8
6.9 Pullup/Pulldown Resistors........................................ 10
6.10 OTG Electrical Characteristics................................10
6.11 OTG ID Electrical.....................................................11
6.12 Power Characteristics............................................. 11
6.13 Switching Characteristics........................................12
6.14 Timing Requirements.............................................. 13
6.15 Typical Characteristics............................................ 15
7 Detailed Description......................................................16
7.1 Overview................................................................... 16
7.2 Functional Block Diagram......................................... 16
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................20
7.5 Register Map.............................................................22
8 Application and Implementation.................................. 53
8.1 Application Information............................................. 53
8.2 Typical Application.................................................... 53
8.3 External Components............................................... 57
9 Power Supply Recommendations................................58
9.1 TUSB1210 Power Supply......................................... 58
9.2 Ground...................................................................... 58
9.3 Power Providers........................................................58
9.4 Power Modules......................................................... 58
9.5 Power Consumption..................................................59
10 Layout...........................................................................60
10.1 TUSB121x USB2.0 Product Family Board
Layout Recommendations...........................................60
10.2 Layout Guidelines................................................... 62
10.3 Layout Example...................................................... 62
11 Device and Documentation Support..........................63
11.1 Device Support........................................................63
11.2 Documentation Support.......................................... 63
11.3 Receiving Notification of Documentation Updates.. 63
11.4 Support Resources................................................. 63
11.5 Trademarks............................................................. 63
11.6 Electrostatic Discharge Caution.............................. 63
11.7 Glossary.................................................................. 63
12 Mechanical, Packaging, and Orderable
Information.................................................................... 63
4 Revision History
Changes from Revision I (December 2019) to Revision J (July 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed the tDC, tDD OUTPUT CLOCK delay value From: MAX = 9 ns To: MAX = 5 ns in the Timing
Requirements .................................................................................................................................................. 13
• Changed the tDC, tDD OUTPUT CLOCK delay value From: MIN = blank To: MIN = 1.2 ns in the Timing
Requirements .................................................................................................................................................. 13
• Added the Related Documentation section...................................................................................................... 63
Changes from Revision H (June 2015) to Revision I (December 2019)
Page
• Changed the document from a data manual format to a TI data sheet format .................................................. 1
• Changed RHB Package 32-Pin OFN To: RHB Package 32-Pin VQFN in Pin Configuration and Functions .....4
• Changed the HBM value From: ±2 V To : ±2000 V in the ESD Ratings ............................................................ 6
• Changed the tSC, tSD INPUT CLOCK value From: MAX = 3 ns To: MIN = 3 ns in the Timing Requirements ..13
• Changed the tSC, tSD OUTPUT CLOCK value From: MAX = 6 ns To: MIN = 6 ns in the Timing Requirements ..
13
• Deleted section Via Channel from the Mechanical Packaging and Orderable Information section ................. 63
Changes from Revision G (October 2014) to Revision H (June 2015)
Page
• Move Storage Temperature From: ESD Ratings To: Absolute Maximum Ratings .............................................6
• Changed the Handling Ratings table To: ESD Ratings ......................................................................................6
Changes from Revision F (July 2013) to Revision G (October 2014)
Page
• Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
2
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section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
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VDDIO
DIR
VDD18
STP
VDD18
RESETB
CLOCK
N/C
32
31
30
29
28
27
26
25
5 Pin Configuration and Functions
REFCLK
1
24
N/C
NXT
2
23
ID
DATA0
3
22
VBUS
DATA1
4
21
VBAT
GND
16
CPEN
N/C
17
15
8
N/C
N/C
14
DP
CFG
18
13
7
DATA7
DATA4
12
DM
VDD15
19
11
6
CS
DATA3
10
VDD33
DATA6
20
9
5
DATA5
DATA2
Not to scale
Figure 5-1. RHB Package Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
CFG
14
A/D
TYPE
LEVEL
DESCRIPTION
D
I
VDDIO
REFCLK clock frequency configuration pin. Two frequencies are supported: 19.2 MHz
when 0, or 26 MHz when 1.
ULPI 60 MHz clock on which ULPI data is synchronized.
Two modes are possible:
CLOCK
26
D
O
VDDIO
Input Mode: CLOCK defaults as an input.
Output Mode: When an input clock is detected on REFCLK pin (after 4 rising edges)
then CLOCK will change to an output.
4
CPEN
17
D
O
VDD33
CMOS active-high digital output control of external 5 V VBUS supply
CS
11
D
I
VDDIO
Active-high chip select pin. When low the IC is in power down and ULPI bus is
tri-stated. When high normal operation. Tie to VDDIO if unused.
DATA0
3
D
I/O
VDDIO
ULPI DATA input or output signal 0 synchronized to CLOCK
DATA1
4
D
I/O
VDDIO
ULPI DATA input or output signal 1 synchronized to CLOCK
DATA2
5
D
I/O
VDDIO
ULPI DATA input or output signal 2 synchronized to CLOCK
DATA3
6
D
I/O
VDDIO
ULPI DATA input or output signal 3 synchronized to CLOCK
DATA4
7
D
I/O
VDDIO
ULPI DATA input or output signal 4 synchronized to CLOCK
DATA5
9
D
I/O
VDDIO
ULPI DATA input or output signal 5 synchronized to CLOCK
DATA6
10
D
I/O
VDDIO
ULPI DATA input or output signal 6 synchronized to CLOCK
DATA7
13
D
I/O
VDDIO
ULPI DATA input or output signal 7 synchronized to CLOCK
DIR
31
D
O
VDDIO
ULPI DIR output signal
DM
19
A
I/O
VDD33
DM pin of the USB connector
DP
18
A
I/O
VDD33
DP pin of the USB connector
ID
23
A
I/O
VDD33
Identification (ID) pin of the USB connector
N/C
8, 15,16,
24, 25
—
—
—
No connection
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Table 5-1. Pin Functions (continued)
PIN
A/D
TYPE
LEVEL
2
D
O
VDDIO
ULPI NXT output signal
REFCLK
1
A
I
3.3 V
VDD33 Reference clock input (square-wave only). Tie to GND when pin 26 (CLOCK)
is required to be Input mode. Connect to square-wave reference clock of amplitude in
the range of 3 V to 3.6 V when Pin 26 (CLOCK) is required to be Output mode. See
pin 14 (CFG) description for REFCLK input frequency settings.
RESETB
27
D
I
VDDIO
When low, all digital logic (except 32 kHz logic required for power up sequencing)
including registers are reset to their default values, and ULPI bus is tri-stated. When
high, normal USB operation.
NAME
NO.
NXT
DESCRIPTION
STP
29
D
I
VDDIO
ULPI STP input signal
VBAT
21
A
power
VBAT
Input supply voltage or battery source
VBUS
22
A
power
VBUS
VBUS pin of the USB connector
VDD15
12
A
power
VDD18
28, 30
A
power
VDD18
External 1.8 V supply input. Connect to external filtering capacitor.
VDD33
20
A
power
VDD33
3.3 V internal LDO output. Connect to external filtering capacitor.
VDDIO
32
A
I
VDDIO
External 1.8 V supply input for digital I/Os. Connect to external filtering capacitor.
GND
Thermal
Pad
A
power
—
1.5 V internal LDO output. Connect to external filtering capacitor.
Reference Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
0
5
V
Where supply represents the voltage applied
to the power supply pin associated with the
input
–0.3 1 × VCC +0.3
V
–2
20
V
ID, DP, DM inputs
Stress condition guaranteed 24h
–0.3
5.25
V
VDDIO
IO supply voltage
Continuous
TA
Ambient temperature range
TJ
Ambient temperature range
Main battery supply voltage (2)
VCC
Voltage on any input(3)
VBUS input
Ambient temperature for parametric
compliance
Tstg
(1)
(2)
(3)
UNIT
1.98
V
–40
85
°C
Absolute maximum rating
–40
150
For parametric compliance
–40
125
–40
85
°C
5.25
V
With max 125°C as junction temperature
DP, DM, ID high voltage short circuit
DP, DM or ID pins short circuited to VBUS
supply, in any mode of TUSB1210 operation,
continuously for 24 hours
DP, DM, ID low voltage short circuit
DP, DM or ID pins short circuited to
GND in any mode of TUSB1210 operation,
continuously for 24 hours
0
Storage temperature range
°C
V
–55
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The product will have negligible reliability impact if voltage spikes of 5.5 V occur for a total (cumulative over lifetime) duration of 5
milliseconds.
Except VBAT input, VBUS, ID, DP, and DM pads
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge (ESD)
performance:
Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1)
±2000
Charged device model (CDM), per JESD22-C101 or ANSI/
ESDA/JEDEC JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
6
MIN
NOM
MAX
2.7
3.6
4.8
UNIT
VBAT
Battery supply voltage
VBAT CERT
Battery supply voltage for USB 2.0 compliancy
(USB 2.0 certification)
VDDIO
Digital IO pin supply
1.71
1.98
V
TA
Ambient temperature range
–40
85
°C
When VDD33 is supplied internally
3.15
When VDD33 is shorted to VBAT externally
3.05
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6.4 Thermal Information
RHB
THERMAL METRIC(1)
UNIT
(16 Pins)
RθJA
Junction-to-ambient thermal resistance
34.72
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
37.3
°C/W
RθJB
Junction-to-board thermal resistance
10.3
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
10.5
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
3.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Analog I/O Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
CPEN Output Pin
VOL
CPEN low-level output voltage
IOL = 3 mA
VOH
CPEN high-level output voltage
IOH = –3 mA
0.3
VDD33 – 0.3
V
V
6.6 Digital I/O Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.45
V
CLOCK
VOL
Low-level output voltage
VOH
High-level output voltage
Frequency = 60 MHz, Load = 10 pF
VDDIO - 0.45
V
STP, DIR, NXT, DATA0 to DATA7
VOL
Low-level output voltage
VOH
High-level output voltage
Frequency = 30 MHz, Load = 10 pF
0.45
VDDIO - 0.45
V
V
6.7 Digital IO Pins (Non-ULPI)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS, CFG, RESETB Input Pins
VIL
Maximum low-level input voltage
VIH
Minimum high-level input voltage
0.35 x VDDIO
V
0.65 x VDDIO
V
0.2
μs
RESETB Input Pin Timing Spec
tw(POR)
tw(RESET)
Internal power-on reset pulse
width
External RESETB pulse width
Applied to external RESETB pin
when CLOCK is toggling.
8
CLOCK
cycles
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6.8 PHY Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
TYP
MAX
–2
0
2
UNIT
LS/FS Single-Ended Receivers
USB single-ended receivers
SKWVP_VM
Skew between VP and VM
VSE_HYS
Single-ended hysteresis
VIH
High (driven)
VIL
Low
VTH
Switching threshold
Driver outputs unloaded
50
mV
2
0.8
ns
V
0.8
V
2
V
LS/FS Differential Receiver
VDI
Differential input sensitivity
Ref. USB2.0
200
VCM
Differential Common mode range
Ref. USB2.0
0.8
2.5
mV
V
VOL
Low
Ref. USB2.0
0
300
mV
VOH
High (driven)
Ref. USB2.0
2.8
3.6
V
VCRS
Output signal crossover voltage
Ref. USB2.0, covered by eye
diagram
1.3
2
V
tr
Rise time
Ref. USB2.0, covered by eye
diagram
75
300
ns
tf
Fall time
ns
tFRFM
Differential rise and fall time matching
tFDRATE
Low-speed data rate
LS Transmitter
tDJ1
Ref. USB2.0, covered by eye
diagram
To next transition
tDJ2
Source jitter total (including frequency
tolerance)
tFEOPT
Source SE0 interval of EOP
Ref. USB2.0, covered by eye
diagram
Downstream eye diagram
Ref. USB2.0, covered by eye
diagram
Differential common mode range
Ref. USB2.0
VCM
For paired
transitions
Ref. USB2.0, covered by eye
diagram
75
300
80%
125%
1.4775
1.5225
–25
25
–10
10
1.25
1.5
µs
0.8
2.5
V
Mb/s
ns
FS Transmitter
VOL
Low
Ref. USB2.0
0
300
mV
VOH
High (driven)
Ref. USB2.0
2.8
3.6
V
VCRS
Output signal crossover voltage
Ref. USB2.0, covered by eye
diagram
1.3
2
V
tFR
Rise time
Ref. USB2.0
4
20
ns
tFF
Fall time
Ref. USB2.0
4
20
ns
tFRFM
Differential rise and fall time matching
Ref. USB2.0, covered by eye
diagram
90%
111.11%
ZDRV
Driver output resistance
Ref. USB2.0
28
44
Full-speed data rate
Ref. USB2.0, covered by eye
diagram
11.97
12.03
–2
2
–1
1
160
175
TFDRATE
tDJ1
To next transition
tDJ2
Source jitter total (including frequency
tolerance)
TFEOPT
Source SE0 interval of EOP
Ref. USB2.0, covered by eye
diagram
Downstream eye diagram
Ref. USB2.0, covered by eye
diagram
For paired
transitions
Ref. USB2.0, covered by eye
diagram
Ω
Mb/s
ns
ns
Upstream eye diagram
8
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6.8 PHY Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
HS Differential Receiver
VHSSQ
High-speed squelch detection threshold (differential signal
amplitude)
Ref. USB2.0
100
150
mV
VHSDSC
High-speed disconnect detection threshold (differential signal
Ref. USB2.0
amplitude)
525
625
mV
High-speed differential input signaling levels
Ref. USB2.0, specified by eye
pattern templates
High-speed data signaling common mode voltage range
(guidelines for receiver)
Ref. USB2.0
Receiver jitter tolerance
Ref. USB2.0, specified by eye
pattern templates
VHSOI
High-speed idle level
Ref. USB2.0
VHSOH
High-speed data signaling high
Ref. USB2.0
VHSOL
High-speed data signaling low
VCHIRPJ
VHSCM
mV
–50
500
mV
150
ps
–10
10
mV
360
440
mV
Ref. USB2.0
–10
10
mV
Chirp J level (differential voltage)
Ref. USB2.0
700
1100
mV
VCHIRPK
Chirp K level (differential voltage)
Ref. USB2.0
-900
-500
mV
tr
Rise Time (10% - 90%)
Ref. USB2.0, covered by eye
diagram
500
ps
tf
Fall time (10% - 90%)
Ref. USB2.0, covered by eye
diagram
500
ps
ZHSDRV
Driver output resistance (which also serves as high-speed
termination)
Ref. USB2.0
40.5
49.5
THSDRAT
High-speed data range
Ref. USB2.0, covered by eye
diagram
479.76
480.24
Data source jitter
Ref. USB2.0, covered by eye
diagram
Downstream eye diagram
Ref. USB2.0, covered by eye
diagram
Upstream eye diagram
Ref. USB2.0, covered by eye
diagram
HS Transmitter
Ω
Mb/s
CEA-2011/UART Transceiver
UART Transmitter CEA-2011
tPH_UART_EDGE
Phone UART edge rates
DP_PULLDOWN asserted
VOH_SER
Serial interface output high
ISOURCE = 4 mA
VOL_SER
Serial interface output low
1
Μs
2.4
3.3
3.6
V
ISINK = –4 mA
0
0.1
0.4
V
2
UART Receiver CEA-2011
VIH_SER
Serial interface input high
DP_PULLDOWN asserted
VIL_SER
Serial interface input low
DP_PULLDOWN asserted
VTH
Switching threshold
0.8
V
0.8
V
2
V
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6.9 Pullup/Pulldown Resistors
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
0.9
1.1
1.575
kΩ
1.425
2.2
3.09
RPUI
Bus pullup resistor on upstream port
(idle bus)
Bus idle
RPUA
Bus pullup resistor on upstream port
(receiving)
Bus driven/driver's outputs unloaded
VIHZ
High (floating)
Pullups/pulldowns on both DP and DM
lines
VPH_DP_UP
Phone D+ pullup voltage
Driver's outputs unloaded
3
Phone D+/– pulldown
Driver's outputs unloaded
14.25
High (floating)
Pullups/pulldowns on both DP and DM
lines
2.7
3.6
V
3.3
3.6
V
18
24.8
kΩ
3.6
V
75
pF
0.342
V
Pulldown resistors
RPH_DP_DWN
RPH_DM_DWN
VIHZ
2.7
D+/– Data line
CINUB
Upstream facing port
[1.0]
VOTG_DATA_LKG
On-the-go device leakage
[2]
22
ZINP
Input impedance exclusive of pullup/
pulldown
Driver's outputs unloaded
300
kΩ
6.10 OTG Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
TYP
MAX UNIT
OTG VBUS Electrical
VBUS Comparators
VA_SESS_VLD
A-device session valid
0.8
1.4
2.0
V
VA_VBUS_VLD
A-device VBUS valid
4.4
4.5
4.625
V
VB_SESS_END
B-device session end
0.2
0.5
0.8
V
VB_SESS_VLD
B-device session valid
2.1
2.4
2.7
V
RA_BUS_IN
A-device VBUS input impedance SRP (VBUS pulsing) capable A-device not driving
to ground
VBUS
40
70
100
kΩ
RB_SRP_DWN
B-device VBUS SRP pulldown
5.25 V / 8 mA, Pullup voltage = 3 V
0.656
10
RB_SRP_UP
B-device VBUS SRP pullup
(5.25 V – 3 V) / 8 mA, Pullup voltage = 3 V
0.281
1
VBUS Line
tRISE_SRP_UP_MAX
10
B-device VBUS SRP rise
time maximum for OTG-A
communication
0 to 2.1 V with < 13 μF
load
kΩ
2
RVBUS = 0 Ω
and R1KSERIES = '0'
31.4
RVBUS = 1000 Ω ±10%
and R1KSERIES = '1'
57.8
RVBUS = 1200 Ω ±10%
and R1KSERIES = '1'
64
RVBUS = 1800 Ω ±10%
and R1KSERIES = '1'
85.4
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6.10 OTG Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
RVBUS = 0 Ω
and R1KSERIES = '0'
tRISE_SRP_UP_MIN
B-device VBUS SRP rise time
minimum for standard host
connection
0.8 to 2 V with > 97 μF
load
TYP
MAX UNIT
46.2
RVBUS = 1000 Ω ±10%
and R1KSERIES = '1'
96
RVBUS = 1200 Ω ±10%
and R1KSERIES = '1'
100
RVBUS = 1800 Ω ±10%
and R1KSERIES = '1'
100
ms
6.11 OTG ID Electrical
over operating free-air temperature range (unless otherwise noted)
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
12
20
28
kΩ
500
kΩ
286
kΩ
3.2
V
5.25
V
UNIT
ID Comparators — ID External Resistors Specifications
RID_GND
ID ground comparator
ID_GND interrupt
RID_FLOAT
ID Float comparator
ID_FLOAT interrupt
200
ID Line
RPH_ID_UP
Phone ID pullup to VPH_ID_UP
ID unloaded (VRUSB)
70
VPH_ID_UP
Phone ID pullup voltage
Connected to VRUSB
2.5
90
ID line maximum voltage
6.12 Power Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VDD33 Internal LDO Regulator Characteristics
VINVDD33
VVDD33
IVDD33
Input voltage
Output voltage
Rated output current
VBAT USB
ON mode,
VBAT USB
VVDD33 typ + 0.2
3.6
4.5
VUSB3V3_VSEL = ‘000
2.4
2.5
2.6
VUSB3V3_VSEL = ‘001
2.65
2.75
2.85
VUSB3V3_VSEL = ‘010
2.9
3.0
3.1
VUSB3V3_VSEL = ‘011 (default)
3.0
3.1
3.2
VUSB3V3_VSEL = ‘100
3.1
3.2
3.3
VUSB3V3_VSEL = ‘101
3.2
3.3
3.4
VUSB3V3_VSEL = ‘110
3.3
3.4
3.5
VUSB3V3_VSEL = ‘111
3.4
3.5
3.6
Active mode
V
V
15
Suspend/reset mode
mA
1
VDD15 Internal LDO Regulator Characteristics
VIN VDD15
Input voltage
On mode, VIN VDD15 = VBAT
2.7
3.6
4.5
V
VVDD15
Output voltage
VINVDD15 min – VINVDD15 max
1.45
1.56
1.65
V
IVDD15
Rated output current
On mode
30
mA
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6.13 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Electrical Characteristics: Clock Input
Clock input duty cycle
fCLK
40
Clock nominal frequency
Clock input rise/fall time
60%
60
In % of clock period tCLK ( = 1/fCLK )
MHz
10%
Clock input frequency accuracy
250
ppm
Clock input integrated jitter
600
ps rms
Electrical Characteristics: REFCLK
REFCLK input duty cycle
fREFCLK
REFCLK nominal frequency
REFCLK input rise/fall time
40
When CFG pin is tied to GND
60%
19.2
When CFG pin is tied to VDDIO
MHz
26
In % of clock period tREFCLK ( = 1/
fREFCLK )
20%
REFCLK input frequency accuracy
250
ppm
REFCLK input integrated jitter
600
ps rms
REFCLK HIZ Leakage current
3
REFCLK HIZ Leakage current
–3
µA
Digital IO Electrical Characteristics: CLOCK
tr
Rise time
Frequency = 60 MHz, Load = 10 pF
1
ns
tf
Fall time
Frequency = 30 MHz, Load = 10 pF
1
ns
1
ns
1
ns
Digital IO Electrical Characteristics: STP, DIR, NXT, DATA0 to DATA7
tr
Rise time
tf
Fall time
12
Frequency = 30 MHz, Load = 10 pF
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6.14 Timing Requirements
INPUT CLOCK
PARAMETER
MIN
OUTPUT CLOCK
MAX
MIN
MAX
UNIT
ULPI Interface Timing
tSC, tSD
Set-up time (control in, 8-bit data in)
tSC, tHD
Hold time (control in, 8-bit data in)
tDC, tDD
Output delay (control out, 8-bit data out)
3
6
1.5
0
6
1.2
ns
ns
5
ns
USB UART Interface Timing
tPH_DP_CON
Phone D+ connect time
100
tPH_DISC_DET
Phone D+ disconnect time
150
fUART_DFLT
Default UART signaling rate (typical rate)
ms
9600
VDDIO, VDD18
bps
ACTIVE
COLDRST
HWRST
OFF
NOPWR
VBAT , VDD33
ms
IORST
CS
TVBBDET (10us)
ICACT
TBGAP (2ms)
BGOK
TPWONVDD15 (100us)
VDD15
DIGPOR
CK32K
TCK32K_PWON (125us)
CK32KOK
TDELRSTPWR (61us)
RESETN_PWR
TDELMNTRVIOEN (91.5us)
TMNTR (183.1us)
MNTR_(VDD18,VIO)_OK
TDELVDD33EN (91.5us)
TMNTR (183.1us)
MNTR_VDD33_OK
(input 60M) CLOCK
RESETB
TDELRESETB (244.1us)
TPLL (300us)
PLL 480M LOCKED
DIR
TDEL_CS_SUPPLYOK (2.84ms)
TDEL_RST_DIR (0.54ms)
Figure 6-1. TUSB1210 Power-Up Timing (ULPI Clock Input Mode)
Table 6-1. Timers and Debounce
PARAMETER
TYP
MAX
UNIT
tDEL_CS_SUPPLYOK
Chip-select-to-supplies OK delay
COMMENTS
MIN
2.84
4.10
ms
tDEL_RST_DIR
RESETB to PHY PLL locked and DIR fallingedge delay
0.54
0.647
ms
tVBBDET
VBAT detection delay
tBGAP
Bandgap power-on delay
tPWONVDD15
VDD15 power-on delay
tPWONCK32K
32-KHz RC-OSC power-on delay
125
µs
tDELRSTPWR
Power control reset delay
61
µs
tDELMNTRVIOEN
Monitor enable delay
91.5
µs
tMNTR
Supply monitoring debounce
183.1
µs
tDELVDD33EN
VDD33 LDO enable delay
93.75
µs
tDELRESETB
RESETB internal delay
244.1
µs
tPLL
PLL lock time
300
µs
10
µs
2
ms
100
µs
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6.14.1 Timing Parameter Definitions
The timing parameter symbols used in the timing requirement and switching characteristic tables are created in
accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies
have been abbreviated as shown in Table 6-2.
Table 6-2. Timing Parameter Definitions
LOWERCASE SUBSCRIPTS
SYMBOL
PARAMETER
C
Cycle time (period)
D
Delay time
Dis
Disable time
En
Enable time
H
Hold time
Su
Setup time
START
Start bit
T
Transition time
V
Valid time
W
Pulse duration (width)
X
Unknown, changing, or don't care level
H
High
L
Low
V
Valid
IV
Invalid
AE
Active edge
FE
First edge
LE
Last edge
Z
High impedance
6.14.2 Interface Target Frequencies
Table 6-3 assumes testing over the recommended operating conditions.
Table 6-3. TUSB1210 Interface Target Frequencies
IO
INTERFACE
USB
14
INTERFACE DESIGNATION
Universal serial bus
TARGET FREQUENCY
1.5 V
High speed
480 Mbits/s
Full speed
12 Mbits/s
Low speed
1.5 Mbits/s
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6.15 Typical Characteristics
Figure 6-2. High-Speed Eye Diagram
Figure 6-3. Full-Speed Eye Diagram
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7 Detailed Description
7.1 Overview
The TUSB1210 is a USB2.0 transceiver chip, designed to interface with a USB controller through a ULPI
interface. It supports all USB2.0 data rates High-Speed, Full-Speed, and Low-Speed. Compliant to Host and
Peripheral (OTG) modes. It additionally supports a UART mode and legacy ULPI serial modes. TUSB1210
Integrates a 3.3-V LDO, which makes it flexible to work with either battery operated systems or pure 3.3 V
supplied systems. Also, it has an integrated PLL Supporting 2 Clock Frequencies 19.2 MHz/26 MHz. The ULPI
clock pin (60 MHz) supports input and output clock configurations. TUSB1210 has low power consumption,
optimized for portable devices, and complete USB OTG Physical Front-End that supports Host Negotiation
Protocol (HNP) and Session Request Protocol (SRP).
TUSB1210 is optimized to be interfaced through a 12-pin SDR UTMI Low Pin Interface (ULPI), supporting both
input clock and output clock modes, with 1.8 V interface supply voltage.
TUSB1210 integrates a 3.3 V LDO, which makes it flexible to work with either battery operated systems or pure
3.3 V supplied systems. Both the main supply and the 3.3 V power domain can be supplied through an external
switched-mode converter for optimized power efficiency.
TUSB1210 includes a POR circuit to detect supply presence on VBAT and VDDIO pins. TUSB1210 can be
disabled or configured in low power mode for energy saving.
TUSB1210 is protected against accidental shorts to 5 V or ground on its exposed interface (DP/DM/ID). It is also
protected against up to 20 V surges on VBUS.
TUSB1210 integrates a high-performance low-jitter 480 MHz PLL and supports two clock configurations.
Depending on the required link configuration, TUSB1210 supports both ULPI input and output clock mode:
input clock mode, in which case a square-wave 60 MHz clock is provided to TUSB1210-Q1 at the ULPI interface
CLOCK pin; and output clock mode in which case TUSB1210 can accept a square-wave reference clock at
REFCLK of either 19.2 MHz, 26 MHz. Frequency is indicated to TUSB1210 via the configuration pin CFG. This
can be useful if a reference clock is already available in the system.
7.2 Functional Block Diagram
VDDIO (32)
POR
VIO
POR
VBAT
CTRL
VBAT (21)
BGAP
& REF
1V5
POR
DIG
( 1) REFCLK
(11) CS
(14) CFG
(27) RESETB
32K
RST_DIG
VDD15 (12)
DIG
USB-IP
VDD18 (30)
VDD18 (28)
VDD33 (20)
DP (18)
DM (19)
ID (23)
VBUS (22)
1V8
PLL
3V3
OTG
PHY
ANA
PHY
DIG
+
ULPI
+
REGS
PWR_ FSM
( 8) N/C
(15 ) N/C
(16 ) N/C
(25 ) N/C
(24) N /C
OTG
TEST
(17) CPEN
PKG Substrate
(Ground )
(3:7,9:10,13)
DATA(7:0)
(2 ) NXT
(31) DIR
(29) STP
(26) CLOCK
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7.3 Feature Description
7.3.1 Processor Subsystem
7.3.1.1 Clock Specifications
7.3.1.1.1 USB PLL Reference Clock
The USB PLL block generates the clocks used to synchronize:
• The ULPI interface (60 MHz clock)
• The USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps, or 1.5 Mbps)
TUSB1210 requires an external reference clock which is used as an input to the 480 MHz USB PLL block.
Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at CLOCK
pin. By default CLK pin is configured as an input.
Two clock configurations are possible:
• Input clock configuration (see Section 7.3.1.1.2)
• Output clock configuration (see Section 7.3.1.1.3)
7.3.1.1.2 ULPI Input Clock Configuration
In this mode, REFCLK must be externally tied to GND. CLOCK remains configured as an input.
When the ULPI interface is used in input clock configuration, that is, the 60 MHz ULPI clock is provided to
TUSB1210 on Clock pin, then this is used as the reference clock for the 480 MHz USB PLL block. See Section
6.13.
7.3.1.1.3 ULPI Output Clock Configuration
In this mode, a reference clock must be externally provided on the REFCLK pin. When an input clock is detected
on the REFCLK pin, then CLK is automatically changed to an output. For example, 60 MHz ULPI clock is the
TUSB1210 devices output on the CLK pin.
Two reference clock input frequencies are supported. REFCLK input frequency is communicated to TUSB1210
through a configuration pin, CFG. See fREFCLK in Table 8-3 for frequency correspondence. TUSB1210 supports
square-wave reference clock input only. Reference clock input must be square-wave of amplitude in the range 3
V to 3.6 V. See Section 6.13.
7.3.1.1.4 Clock 32 kHz
An internal clock generator running at 32 kHz has been implemented to provide a low-speed, low-power clock to
the system See Section 7.3.1.1.4.
7.3.1.1.5 Reset
All logic is reset if CS = 0 or VBAT are not present.
All logic (except 32 kHz logic) is reset if VDDIO is not present.
PHY logic is reset when any supplies are not present (VDDIO, VDD15, VDD18, and VDD33) or if RESETB pin is low.
TUSB1210 may be reset manually by toggling the RESETB pin to GND for at least 200 ns.
If manual reset through RESETB is not required, then RESETB pin may be tied to VDDIO permanently.
7.3.1.2 USB Transceiver
The TUSB1210 device includes a universal serial bus (USB) on-the-go (OTG) transceiver that supports USB 480
Mb/s high-speed (HS), 12 Mb/s full-speed (FS), and USB 1.5 Mb/s low-speed (LS) through a 12-pin UTMI+ low
pin interface (ULPI).
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Note
LS device mode is not allowed by a USB2.0 HS capable PHY, therefore it is not supported by
TUSB1210. This is stated in USB2.0 standard Chapter 7, page 119, second paragraph: “A high-speed
capable upstream facing transceiver must not support low-speed signaling mode..” There is also some
related commentary in Chapter 7.1.2.3.
7.3.1.2.1 PHY Electrical Characteristics
The PHY is the physical signaling layer of the USB 2.0. It essentially contains all the drivers and receivers
required for physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through a standard 12-pin digital interface called UTMI+ low pin
interface (ULPI).
The transmitters and receivers inside the PHY are classified into two main classes.
• The full-speed (FS) and low-speed (LS) transceivers. These are the legacy USB1.x transceivers.
• The HS (HS) transceivers
To bias the transistors and run the logic, the PHY also contains reference generation circuitry which consists of:
• A DPLL which does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for USB and
also the clock required for the switched capacitor resistance block.
• A switched capacitor resistance block which is used to replicate an external resistor on chip.
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
Apart from this, the PHY also contains circuitry which protects it from accidental 5-V short on the DP and DM
lines.
7.3.1.2.1.1 LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data
lines D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the full-speed/
low-speed modes of operation. See Section 6.8.
7.3.1.2.1.2 LS/FS Differential Receiver
A differential input receiver (Rx) retrieves the LS/FS differential data signaling. The differential voltage on the line
is converted into digital data by a differential comparator on DP/DM. This data is then sent to a clock and data
recovery circuit which recovers the clock from the data. An additional serial mode exists in which the differential
data is directly output on the RXRCV pin. See Section 6.13.
7.3.1.2.1.3 LS/FS Transmitter
The USB transceiver (Tx) uses a differential output driver to drive the USB data signal D+/– onto the USB cable.
The driver's outputs support 3-state operation to achieve bidirectional half-duplex transactions. See Section
6.13.
7.3.1.2.1.4 HS Differential Receiver
The HS receiver consists of the following blocks:
A differential input comparator to receive the serial data
• A squelch detector to qualify the received data
• An oversampler-based clock data recovery scheme followed by a NRZI decoder, bit unstuffing, and serial-toparallel converter to generate the ULPI DATAOUT
See Section 6.13.
18
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7.3.1.2.1.5 HS Differential Transmitter
The HS transmitter is always operated via the ULPI parallel interface. The parallel data on the interface is
serialized, bit stuffed, NRZI encoded, and transmitted as a dc output current on DP or DM depending on the
data. Each line has an effective 22.5 Ω load to ground, which generates the voltage levels for signaling.
A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes the
impedance seen by the transmitter to double thereby doubling the differential amplitude seen on the DP/DM
lines of Section 6.13.
7.3.1.2.1.6 UART Transceiver
In this mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a direct
access to the FS/LS analog transmitter and receiver. See Section 6.13.
Figure 7-1. USB UART Data Flow
7.3.1.2.2 OTG Characteristics
The on-the-go (OTG) block integrates three main functions:
• The USB plug detection function on VBUS and ID
• The ID resistor detection
• The VBUS level detection
See Section 6.10.
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7.4 Device Functional Modes
7.4.1 TUSB1210 Modes vs ULPI Pin Status
Table 7-1, Table 7-2, and Table 7-3 show the status of each of the 12 ULPI pins including input or output
direction and whether output pins are driven to ‘0’ or to ‘1’, or pulled up or pulled down through the internal pullup
or pulldown resistors.
Note that pullup or pulldown resistors are automatically replaced by driven ‘1’/’0’ levels respectively once internal
IORST is released, with the exception of the pullup on STP which is maintained in all modes.
Pin assignment changes in ULPI 3-pin serial mode, ULPI 6-pin serial mode, and UART mode. Unused pins are
tied low in these modes as shown below.
Table 7-1. TUSB1210 Modes vs ULPI Pin Status:ULPI Synchronous Mode Power-Up
ULPI SYNCHRONOUS MODE POWER-UP
UNTIL IORST RELEASE
PLL OFF
PLL ON + STP HIGH
PLL ON + STP LOW
PIN NO.
PIN NAME
DIR
PU/PD
DIR
PU/PD
DIR
PU/PD
DIR
PU/PD
26
CLOCK
Hiz
PD
I
PD
IO
—
IO
—
31
DIR
Hiz
PU
O, (‘1’)
—
O, (‘0’)
—
O
—
2
NXT
Hiz
PD
O, (‘0’)
—
O, (‘0’)
—
O
—
29
STP
Hiz
PU
I
PU
I
PU
I
PU
3
DATA0
Hiz
PD
O, (‘0’)
—
I
PD
IO
—
4
DATA1
Hiz
PD
O, (‘0’)
—
I
PD
IO
—
5
DATA2
Hiz
PD
O, (‘0’)
—
I
PD
IO
—
6
DATA3
Hiz
PD
O, (‘0’)
—
I
PD
IO
—
7
DATA4
Hiz
PD
O, (‘0’)
—
I
PD
IO
—
9
DATA5
Hiz
PD
O, (‘0’)
—
I
PD
IO
—
10
DATA6
Hiz
PD
O, (‘0’)
—
I
PD
IO
—
13
DATA7
Hiz
PD
O, (‘0’)
—
I
PD
IO
—
Table 7-2. TUSB1210 Modes vs ULPI Pin Status: USB Suspend Mode
LINK / EXTERNAL RECOMMENDED SETTING DURING
SUSPEND MODE
SUSPEND MODE
(1)
20
PIN NO.
PIN NAME
DIR
PU/PD
DIR
PU/PD
26
CLOCK
I
—
O
—
31
DIR
O, (‘1’)
—
I
—
2
NXT
O, (‘0’)
—
I
—
29
STP
I
PU(1)
O, (‘0’)
—
3
DATA0
O, (LINESTATE0)
—
I
—
4
DATA1
O, (LINESTATE1)
—
I
—
5
DATA2
O, (‘0’)
—
I
—
6
DATA3
O, (INT)
—
I
—
7
DATA4
O, (‘0’)
—
I
—
9
DATA5
O, (‘0’)
—
I
—
10
DATA6
O, (‘0’)
—
I
—
13
DATA7
O, (‘0’)
—
I
—
Can be disabled by software before entering Suspend Mode to reduce current consumption
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Table 7-3. TUSB1210 Modes vs ULPI Pin Status: ULPI 6-Pin Serial Mode and UART Mode
ULPI 6-PIN SERIAL MODE
ULPI 3-PIN SERIAL MODE
UART MODE
PIN NO.
PIN NAME
DIR
PU/PD
PIN NAME
DIR
PU/PD
PIN NAME
DIR
PU/PD
26
CLOCK (1)
IO
—
CLOCK (1)
IO
—
CLOCK (1)
IO
—
31
DIR
O
—
DIR
O
—
DIR
O
—
2
NXT
O
—
NXT
O
—
NXT
O
—
29
STP
I
PU
STP
I
PU
STP
I
PU
3
TX_ENABLE
I
—
TX_ENABLE
I
—
TXD
I
—
4
TX_DAT
I
—
DAT
IO
—
RXD
IO
—
5
TX_SE0
I
—
SE0
IO
—
tie low
O
—
6
INT
O
—
INT
O
—
INT
O
—
7
RX_DP
O
—
tie low
O
—
tie low
O
—
9
RX_DM
O
—
tie low
O
—
tie low
O
—
10
RX_RCV
O
—
tie low
O
—
tie low
O
13
tie low
O
—
tie low
O
—
tie low
O
—
—
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7.5 Register Map
Table 7-4. USB Register Summary
22
REGISTER NAME
TYPE
REGISTER WIDTH
(BITS)
PHYSICAL
ADDRESS
VENDOR_ID_LO
R
8
0x00
VENDOR_ID_HI
R
8
0x01
PRODUCT_ID_LO
R
8
0x02
PRODUCT_ID_HI
R
8
0x03
FUNC_CTRL
RW
8
0x04
FUNC_CTRL_SET
RW
8
0x05
FUNC_CTRL_CLR
RW
8
0x06
IFC_CTRL
RW
8
0x07
IFC_CTRL_SET
RW
8
0x08
IFC_CTRL_CLR
RW
8
0x09
OTG_CTRL
RW
8
0x0A
OTG_CTRL_SET
RW
8
0x0B
OTG_CTRL_CLR
RW
8
0x0C
USB_INT_EN_RISE
RW
8
0x0D
USB_INT_EN_RISE_SET
RW
8
0x0E
USB_INT_EN_RISE_CLR
RW
8
0x0F
USB_INT_EN_FALL
RW
8
0x10
USB_INT_EN_FALL_SET
RW
8
0x11
USB_INT_EN_FALL_CLR
RW
8
0x12
USB_INT_STS
R
8
0x13
USB_INT_LATCH
R
8
0x14
DEBUG
R
8
0x15
SCRATCH_REG
RW
8
0x16
0x17
SCRATCH_REG_SET
RW
8
SCRATCH_REG_CLR
RW
8
0x18
Reserved
R
8
0x19 0x2E
ACCESS_EXT_REG_SET
RW
8
0x2F
Reserved
R
8
0x30 0x3C
VENDOR_SPECIFIC1
RW
8
0x3D
VENDOR_SPECIFIC1_SET
RW
8
0x3E
VENDOR_SPECIFIC1_CLR
RW
8
0x3F
VENDOR_SPECIFIC2
RW
8
0x80
VENDOR_SPECIFIC2_SET
RW
8
0x81
VENDOR_SPECIFIC2_CLR
RW
8
0x82
VENDOR_SPECIFIC1_STS
R
8
0x83
VENDOR_SPECIFIC1_LATCH
R
8
0x84
VENDOR_SPECIFIC3
RW
8
0x85
VENDOR_SPECIFIC3_SET
RW
8
0x86
VENDOR_SPECIFIC3_CLR
RW
8
0x87
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7.5.1 VENDOR_ID_LO
ADDRESS OFFSET
0x00
PHYSICAL ADDRESS
0x00
DESCRIPTION
Lower byte of vendor ID supplied
by USB-IF (TI Vendor ID =
0x0451)
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
VENDOR_ID
BITS
FIELD NAME
7:00
VENDOR_ID
DESCRIPTION
TYPE
RESET
R
0x51
7.5.2 VENDOR_ID_HI
ADDRESS OFFSET
0x01
PHYSICAL ADDRESS
0x01
DESCRIPTION
Upper byte of vendor ID supplied
by USB-IF (TI Vendor ID =
0x0451)
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
VENDOR_ID
BITS
FIELD NAME
7:00
VEN DOR_ID
DESCRIPTION
TYPE
RESET
R
0x04
7.5.3 PRODUCT_ID_LO
ADDRESS OFFSET
0x02
PHYSICAL ADDRESS
0x02
DESCRIPTION
Lower byte of Product ID supplied
by Vendor (TUSB1210 Product ID
is 0x1507).
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
PRODUCT_ID
BITS
FIELD NAME
DESCRIPTION
TYPE
7:00
PRODUCT_ID
R
0x07
RESET
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7.5.4 PRODUCT_ID_HI
ADDRESS OFFSET
0x03
PHYSICAL ADDRESS
0x03
DESCRIPTION
Upper byte of Product ID supplied
by Vendor (TUSB1210 Product ID
is 0x1507).
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
PRODUCT_ID
BITS
FIELD NAME
DESCRIPTION
TYPE
7:00
PRODUCT_ID
R
0x15
RESET
7.5.5 FUNC_CTRL
ADDRESS OFFSET
0x04
PHYSICAL ADDRESS
0x04
DESCRIPTION
Controls UTMI function settings
of the PHY.
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
Reserved
SUSPENDM
RESET
BITS
4
OPMODE
FIELD NAME
7
Reserved
6
SUSPENDM
5
RESET
3
2
1
TERMSELECT
DESCRIPTION
0
XCVRSELECT
TYPE
RESET
R
0
Active low PHY suspend. Put PHY into Low Power Mode. In Low Power
Mode the PHY power down all blocks except the full speed receiver, OTG
comparators, and the ULPI interface pins. The PHY automatically set this bit
to '1' when Low Power Mode is exited.
RW
1
Active high transceiver reset. Does not reset the ULPI interface or ULPI
register set.
RW
0
RW
0x0
RW
0
Once set, the PHY asserts the DIR signal and reset the UTMI core. When
the reset is completed, the PHY de-asserts DIR and clears this bit. After
de-asserting DIR, the PHY re-assert DIR and send an RX command update.
Note: This bit is auto-cleared, this explain why it can't be read at '1'.
4:03
2
24
OPMODE
TERMSELECT
Select the required bit encoding style during transmit
0x0:
Normal operation
0x1:
Non-driving
0x2:
Disable bit-stuff and NRZI encoding
0x3:
Reserved (No SYNC and EOP generation feature not supported)
Controls the internal 1.5KΩs pull-up resistor and 45Ωs HS terminations.
Control over bus resistors changes depending on XcvrSelect, OpMode,
DpPulldown and DmPulldown.
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BITS
SLLSE09J – NOVEMBER 2009 – REVISED JULY 2021
FIELD NAME
1:00
XCVRSELECT
DESCRIPTION
TYPE
RESET
RW
0x1
Select the required transceiver speed.
0x0:
Enable HS transceiver
0x1:
Enable FS transceiver
0x2:
Enable LS transceiver
0x3:
Enable FS transceiver for LS packets
(FS preamble is automatically pre-pended)
7.5.6 FUNC_CTRL_SET
ADDRESS OFFSET
0x05
PHYSICAL ADDRESS
0x05
DESCRIPTION
This register does not physically
exist.
It is the same as the
func_ctrl register with read/setonly property (write '1' to set a
particular bit, a write '0' has noaction).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
Reserved
SUSPENDM
RESET
OPMODE
TERMSELECT
DESCRIPTION
2
1
0
XCVRSELECT
BITS
FIELD NAME
TYPE
RESET
7
Reserved
R
0
6
SUSPENDM
RW
1
5
RESET
RW
0
4:03
OPMODE
RW
0x0
2
TERMSELECT
RW
0
1:00
XCVRSELECT
RW
0x1
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7.5.7 FUNC_CTRL_CLR
ADDRESS OFFSET
0x06
PHYSICAL ADDRESS
0x06
DESCRIPTION
This register does not physically
exist.
It is the same as the func_ctrl
register with read/clear-only
property (write '1' to clear a
particular bit, a write '0' has noaction).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
Reserved
SUSPENDM
RESET
OPMODE
TERMSELECT
BITS
26
FIELD NAME
DESCRIPTION
2
1
0
XCVRSELECT
TYPE
RESET
7
Reserved
R
0
6
SUSPENDM
RW
1
5
RESET
RW
0
4:03
OPMODE
RW
0x0
2
TERMSELECT
RW
0
1:00
XCVRSELECT
RW
0x1
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7.5.8 IFC_CTRL
ADDRESS OFFSET
0x07
PHYSICAL ADDRESS
0x07
DESCRIPTION
Enables alternative interfaces
and PHY features.
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
INTERFACE_P
INDICATORPA
ROTECT_DISA
SSTHRU
BLE
BITS
7
5
4
3
INDICATORCO
CLOCKSUSPE
AUTORESUME
MPLEMENT
NDM
FIELD NAME
2
CARKITMODE
1
0
FSLSSERIALM FSLSSERIALM
ODE_3PIN
ODE_6PIN
DESCRIPTION
INTERFACE_PROTECT_DISA Controls circuitry built into the PHY for protecting the ULPI interface when the link
BLE
tri-states stp and data.
TYPE
RESET
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
RW
0
0b: Enables the interface protect circuit
1b: Disables the interface protect circuit
6
INDICATORPASSTHRU
Controls whether the complement output is qualified with the internal vbusvalid
comparator before being used in the VBUS State in the RXCMD.
0b: Complement output signal is qualified with the internal VBUSVALID comparator.
1b: Complement output signal is not qualified with the internal VBUSVALID comparator.
5
INDICATORCOMPLEMENT
Tells the PHY to invert EXTERNALVBUSINDICATOR input signal, generating the
complement output.
0b: PHY will not invert signal EXTERNALVBUSINDICATOR (default)
1b: PHY will invert signal EXTERNALVBUSINDICATOR
4
AUTORESUME
Enables the PHY to automatically transmit resume signaling.
Refer to USB specification 7.1.7.7 and 7.9 for more details.
0 = AutoResume disabled
1 = AutoResume enabled (default)
3
CLOCKSUSPENDM
Active low clock suspend. Valid only in Serial Modes. Powers down the internal clock
circuitry only. Valid only when SuspendM = 1b. The PHY must ignore ClockSuspend
when SuspendM = 0b. By default, the clock will not be powered in Serial and Carkit
Modes.
0b : Clock will not be powered in Serial and UART Modes.
1b : Clock will be powered in Serial and UART Modes.
2
CARKITMODE
Changes the ULPI interface to UART interface. The PHY automatically clear this field
when UART mode is exited.
0b: UART disabled.
1b: Enable serial UART mode.
1
FSLSSERIALMODE_3PIN
Changes the ULPI interface to 3-pin Serial.
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 4-pin serial interface
0
FSLSSERIALMODE_6PIN
Changes the ULPI interface to 6-pin Serial.
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 6-pin serial interface
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7.5.9 IFC_CTRL_SET
ADDRESS OFFSET
0x08
PHYSICAL ADDRESS
0x08
DESCRIPTION
This register does not physically
exist.
It is the same as the
ifc_ctrl register with read/set-only
property (write '1' to set a
particular bit, a write '0' has noaction).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
INTERFACE_P INDICATORPA
ROTECT_DISA
SSTHRU
BLE
28
4
3
INDICATORCO AUTORESUME CLOCKSUSPE
MPLEMENT
NDM
BITS
FIELD NAME
7
6
DESCRIPTION
2
1
CARKITMODE
0
FSLSSERIALM FSLSSERIALM
ODE_3PIN
ODE_6PIN
TYPE
RESET
INTERFACE_PROTECT_DISABLE
RW
0
INDICATORPASSTHRU
RW
0
5
INDICATORCOMPLEMENT
RW
0
4
AUTORESUME
RW
1
3
CLOCKSUSPENDM
RW
0
2
CARKITMODE
RW
0
1
FSLSSERIALMODE_3PIN
RW
0
0
FSLSSERIALMODE_6PIN
R
0
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7.5.10 IFC_CTRL_CLR
ADDRESS OFFSET
0x09
PHYSICAL ADDRESS
0x09
DESCRIPTION
This register does not physically
exist.
It is the same as the ifc_ctrl
register with read/clear-only
property (write '1' to clear a
particular bit, a write '0' has noaction).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
INTERFACE_P
IN
INDICATORCO AUTORESUME CLOCKSUSPE
ROTECT_DISA DICATORPASS
MPLEMENT
NDM
BLE
THRU
BITS
FIELD NAME
7
6
CARKITMODE
DESCRIPTION
1
0
FSLSSERIALM FSLSSERIALM
ODE_3PIN
ODE_6PIN
TYPE
RESET
INTERFACE_PROTECT_DISABLE
RW
0
INDICATORPASSTHRU
RW
0
5
INDICATORCOMPLEMENT
RW
0
4
AUTORESUME
RW
1
3
CLOCKSUSPENDM
RW
0
2
CARKITMODE
RW
0
1
FSLSSERIALMODE_3PIN
RW
0
0
FSLSSERIALMODE_6PIN
R
0
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7.5.11 OTG_CTRL
ADDRESS OFFSET
0x0A
PHYSICAL ADDRESS
0x0A
DESCRIPTION
Controls UTMI+ OTG functions of
the PHY.
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
USEEXTERNA DRVVBUSEXT
LVBUSINDICAT
ERNAL
OR
5
4
DRVVBUS
CHRGVBUS
BITS
FIELD NAME
7
USEEXTERNALVBUSINDICATOR
3
2
1
0
DISCHRGVBU DMPULLDOWN DPPULLDOWN
S
DESCRIPTION
Tells the PHY to use an external VBUS over-current indicator.
IDPULLUP
TYPE
RESET
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
1
RW
0
0b: Use the internal OTG comparator (VA_VBUS_VLD) or internal VBUS valid
indicator (default)
1b: Use external VBUS valid indicator signal.
6
DRVVBUSEXTERNAL
Selects between the internal and the external 5 V VBUS supply.
0b: Pin17 (CPEN) is disabled (output GND level). TUSB1210 does not support
internal VBUS supply.
1b: Pin17 (CPEN) is set to ‘1’ (output VDD33 voltage level) if DRVVBUS bit is
‘1’, else Pin17 (CPEN) is disabled (output GND level) if DRVVBUS bit is ‘0’
5
DRVVBUS
VBUS output control bit
0b : do not drive VBUS
1b : drive 5V on VBUS
Note: Both DRVVBUS and DRVVBUSEXTERNAL bits must be set to 1 in order
to to set Pin17 (CPEN). CPEN pin can be used to enable an external VBUS
supply
4
CHRGVBUS
Charge VBUS through a resistor. Used for VBUS pulsing SRP. The Link must
first check that VBUS has been discharged (see DischrgVbus register bit), and
that both D+ and D- data lines have been low (SE0) for 2ms.
0b : do not charge VBUS
1b : charge VBUS
3
DISCHRGVBUS
Discharge VBUS through a resistor. If the Link sets this bit to 1, it waits for an
RX CMD indicating SessEnd has transitioned from 0 to 1, and then resets this
bit to 0 to stop the discharge.
0b : do not discharge VBUS
1b : discharge VBUS
2
DMPULLDOWN
Enables the 15k Ohm pull-down resistor on D-.
0b : Pull-down resistor not connected to D-.
1b : Pull-down resistor connected to D-.
1
DPPULLDOWN
Enables the 15k Ohm pull-down resistor on D+.
0b : Pull-down resistor not connected to D+.
1b : Pull-down resistor connected to D+.
0
IDPULLUP
Connects a pull-up to the ID line and enables sampling of the signal level.
0b : Disable sampling of ID line.
1b : Enable sampling of ID line.
30
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7.5.12 OTG_CTRL_SET
ADDRESS OFFSET
0x0B
PHYSICAL ADDRESS
0x0B
DESCRIPTION
This register does not physically
exist.
It is the same as the
otg_ctrl register with read/setonly property (write '1' to set a
particular bit, a write '0' has noaction).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
USEEXTERNA
DRVVBUSEXT
LVBUSINDICAT
ERNAL
OR
5
4
DRVVBUS
CHRGVBUS
BITS
FIELD NAME
7
6
3
2
1
DISCHRGVBU
DMPULLDOWN DPPULLDOWN
S
DESCRIPTION
0
IDPULLUP
TYPE
RESET
USEEXTERNALVBUSINDICATOR
RW
0
DRVVBUSEXTERNAL
RW
0
5
DRVVBUS
RW
0
4
CHRGVBUS
RW
0
3
DISCHRGVBUS
RW
0
2
DMPULLDOWN
RW
1
1
DPPULLDOWN
RW
1
0
IDPULLUP
RW
0
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7.5.13 OTG_CTRL_CLR
ADDRESS OFFSET
0x0C
PHYSICAL ADDRESS
0x0C
DESCRIPTION
This register does not physically
exist.
It is the same as the otg_ctrl
register with read/Clear-only
property (write '1' to clear a
particular bit, a write '0' has noaction).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
USEEXTERNA
DRVVBUSEXT
LVBUSINDICAT
ERNAL
OR
32
5
4
DRVVBUS
CHRGVBUS
BITS
FIELD NAME
7
6
3
2
1
DISCHRGVBU
DMPULLDOWN DPPULLDOWN
S
DESCRIPTION
0
IDPULLUP
TYPE
RESET
USEEXTERNALVBUSINDICATOR
RW
0
DRVVBUSEXTERNAL
RW
0
5
DRVVBUS
RW
0
4
CHRGVBUS
RW
0
3
DISCHRGVBUS
RW
0
2
DMPULLDOWN
RW
1
1
DPPULLDOWN
RW
1
0
IDPULLUP
RW
0
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7.5.14 USB_INT_EN_RISE
ADDRESS OFFSET
0x0D
PHYSICAL ADDRESS
0x0D
DESCRIPTION
If set, the bits in this
register cause an interrupt event
notification to be generated when
the corresponding PHY signal
changes from low to high.
By default, all transitions are
enabled.
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
IDGND_RISE
BITS
FIELD NAME
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_RISE
RW
1
SESSEND_RIS SESSVALID_RI VBUSVALID_RI HOSTDISCON
E
SE
SE
NECT_RISE
DESCRIPTION
Generate an interrupt event notification when IdGnd changes from
low to high.
Event is automatically masked if IdPullup bit is clear to 0 and for
50ms after IdPullup is set to 1.
3
SESSEND_RISE
Generate an interrupt event notification when SessEnd changes
from low to high.
RW
1
2
SESSVALID_RISE
Generate an interrupt event notification when SessValid changes
from low to high. SessValid is the same as UTMI+ AValid.
RW
1
1
VBUSVALID_RISE
Generate an interrupt event notification when VbusValid changes
from low to high.
RW
1
0
HOSTDISCONNECT_RISE
Generate an interrupt event notification when Hostdisconnect
changes from low to high. Applicable only in host mode (DpPulldown
and DmPulldown both set to 1b).
RW
1
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7.5.15 USB_INT_EN_RISE_SET
ADDRESS OFFSET
0x0E
PHYSICAL ADDRESS
0x0E
DESCRIPTION
This register does not physically
exist.
It is the same as the
usb_int_en_rise register with
read/set-only property (write '1' to
set a particular bit, a write '0' has
no-action).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
34
7
6
5
4
3
Reserved
Reserved
Reserved
IDGND_RISE
2
1
0
SESSEND_RIS SESSVALID_RI VBUSVALID_RI HOSTDISCON
E
SE
SE
NECT_RISE
BITS
FIELD NAME
TYPE
RESET
7
Reserved
DESCRIPTION
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_RISE
RW
1
3
SESSEND_RISE
RW
1
2
SESSVALID_RISE
RW
1
1
VBUSVALID_RISE
RW
1
0
HOSTDISCONNECT_RIS
E
RW
1
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7.5.16 USB_INT_EN_RISE_CLR
ADDRESS OFFSET
0x0F
PHYSICAL ADDRESS
0x0F
DESCRIPTION
This register does not physically
exist.
It is the same as the
usb_int_en_rise register with
read/clear-only property (write '1'
to clear a particular bit, a write '0'
has no-action).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
Reserved
Reserved
Reserved
IDGND_RISE
SESSEN
D_RISE
DESCRIPTION
2
1
0
SESSVALID_RI VBUSVALID_RI HOSTDISCON
SE
SE
NECT_RISE
BITS
FIELD NAME
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_RISE
RW
1
3
SESSEND_RISE
RW
1
2
SESSVALID_RISE
RW
1
1
VBUSVALID_RISE
RW
1
0
HOSTDISCONNECT_RISE
RW
1
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7.5.17 USB_INT_EN_FALL
ADDRESS OFFSET
0x10
PHYSICAL ADDRESS
0x10
DESCRIPTION
If set, the bits in this
register cause an interrupt event
notification to be generated when
the corresponding PHY signal
changes from low to high.
By default, all transitions are
enabled.
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
Reserved
Reserved
Reserved
IDGND_FALL
BITS
FIELD NAME
3
2
SESSEND_FAL SESSVALID_F
L
ALL
1
0
VBUSVALID_F
ALL
HOSTDISCON
NECT_FALL
TYPE
RESET
7
Reserved
DESCRIPTION
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_FALL
RW
1
Generate an interrupt event notification when IdGnd changes from
high to low.
Event is automatically masked if IdPullup bit is clear to 0 and for
50ms after IdPullup is set to 1.
36
3
SESSEND_FALL
Generate an interrupt event notification when SessEnd changes
from high to low.
RW
1
2
SESSVALID_FALL
Generate an interrupt event notification when SessValid changes
from high to low. SessValid is the same as UTMI+ AValid.
RW
1
1
VBUSVALID_FALL
Generate an interrupt event notification when VbusValid changes
from high to low.
RW
1
0
HOSTDISCONNECT_FALL
Generate an interrupt event notification when Hostdisconnect
changes from high to low. Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
RW
1
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7.5.18 USB_INT_EN_FALL_SET
ADDRESS OFFSET
0x11
PHYSICAL ADDRESS
0x11
DESCRIPTION
This register does not physically
exist.
It is the same as the
usb_int_en_fall register with read/
set-only property (write '1' to set
a particular bit, a write '0' has noaction)
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
Reserved
Reserved
Reserved
IDGND_FALL
3
2
SESSEND_FAL SESSVALID_F
L
ALL
DESCRIPTION
1
0
VBUSVALID_F
ALL
HOSTDISCON
NECT_FALL
BITS
FIELD NAME
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_FALL
RW
1
3
SESSEND_FALL
RW
1
2
SESSVALID_FALL
RW
1
1
VBUSVALID_FALL
RW
1
0
HOSTDISCONNECT_FALL
RW
1
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7.5.19 USB_INT_EN_FALL_CLR
ADDRESS OFFSET
0x12
PHYSICAL ADDRESS
0x12
DESCRIPTION
This register does not physically
exist.
It is the same as the
usb_int_en_fall register with read/
clear-only property (write '1' to
clear a particular bit, a write '0'
has no-action).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
Reserved
Reserved
Reserved
IDGND_FALL
BITS
38
FIELD NAME
3
2
SESSEND_FAL SESSVALID_F
L
ALL
DESCRIPTION
1
0
VBUSVALID_F
ALL
HOSTDISCON
NECT_FALL
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_FALL
RW
1
3
SESSEN D_FALL
RW
1
2
SESSVALID_FALL
RW
1
1
VBUSVALID_FALL
RW
1
0
HOSTDISCONNECT_FALL
RW
1
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7.5.20 USB_INT_STS
ADDRESS OFFSET
0x13
PHYSICAL ADDRESS
0x13
DESCRIPTION
Indicates the current value of the
interrupt source signal.
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
IDGND
SESSEND
SESSVALID
VBUSVALID
HOSTDISCON
NECT
BITS
TYPE
RESET
7
Reserved
FIELD NAME
DESCRIPTION
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND
R
0
Current value of UTMI+ IdGnd output.
This bit is not updated if IdPullup bit is reset to 0 and for 50 ms after IdPullup is set to
1.
3
SESSEND
Current value of UTMI+ SessEnd output.
R
0
2
SESSVALID
Current value of UTMI+ SessValid output. SessValid is the same as UTMI+ AValid.
R
0
1
VBUSVALID
Current value of UTMI+ VbusValid output.
R
0
0
HOSTDISCONNECT Current value of UTMI+ Hostdisconnect output.
R
0
Applicable only in host mode.
Automatically reset to 0 when Low Power Mode is entered.
NOTE: Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
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7.5.21 USB_INT_LATCH
ADDRESS OFFSET
0x14
PHYSICAL ADDRESS
0x14
DESCRIPTION
These bits are set by the PHY when an unmasked change
occurs on the corresponding internal signal. The PHY
will automatically clear all bits when the Link reads this
register, or when Low Power Mode is entered. The PHY
also clears this register when Serial Mode or Carkit Mode
is entered regardless of the value of ClockSuspendM.
The PHY follows the rules defined in Table 26 of the ULPI
spec for setting any latch register bit. It is important to
note that if register read data is returned to the Link in the
same cycle that a USB Interrupt Latch bit is to be set, the
interrupt condition is given immediately in the register read
data and the Latch bit is not set.
Note that it is optional for the Link to read the USB
Interrupt Latch register in Synchronous Mode because
the RX CMD byte already indicates the interrupt source
directly
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
Reserved
BITS
Reserved
FIELD NAME
5
Reserved
4
3
2
SESSEND_LAT SESSVALID_L
IDGND_LATCH
CH
ATCH
1
0
VBUSVALID_L
ATCH
HOSTDISCON
NECT_LATCH
DESCRIPTION
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
IDGND_LATCH
Set to 1 by the PHY when an unmasked event occurs on IdGnd. Cleared
when this register is read.
R
0
3
SESSEND_LATCH
Set to 1 by the PHY when an unmasked event occurs on SessEnd.
Cleared when this register is read.
R
0
2
SESSVALID_LATCH
Set to 1 by the PHY when an unmasked event occurs on SessValid.
Cleared when this register is read. SessValid is the same as UTMI+
AValid.
R
0
1
VBUSVALID_LATCH
Set to 1 by the PHY when an unmasked event occurs on VbusValid.
Cleared when this register is read.
R
0
0
HOSTDISCONNECT_LATC Set to 1 by the PHY when an unmasked event occurs on
H
Hostdisconnect. Cleared when this register is read. Applicable only in
host mode.
R
0
NOTE: As this IT is enabled by default, the reset value depends on the
host status
Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
40
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7.5.22 DEBUG
ADDRESS OFFSET
0x15
PHYSICAL ADDRESS
0x15
DESCRIPTION
Indicates the current value
of various signals useful for
debugging.
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
Reserved
BITS
FIELD NAME
0
LINESTATE
DESCRIPTION
TYPE
RESET
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
Reserved
R
0
3
Reserved
R
0
2
Reserved
1:00
LINESTATE
These signals reflect the current state of the single
ended receivers. They directly reflect the current
state of the DP (LineState[0]) and DM (LineState[1])
signals.
•
•
R
0
R
0x0
Read 0x0: SE0 (LS/FS), Squelch (HS/Chirp)
Read 0x1:
–
–
–
–
•
LS: 'K' State,
FS: 'J' State,
HS: !Squelch,
Chirp: !Squelch &
HS_Differential_Receiver_Output
Read 0x2:
–
–
–
–
•
LS: 'K' State,
FS: 'J' State,
HS: !Squelch,
Chirp: !Squelch &
HS_Differential_Receiver_Output
Read 0x3: SE1 (LS/FS), Invalid (HS/Chirp)
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7.5.23 SCRATCH_REG
ADDRESS OFFSET
0x16
PHYSICAL ADDRESS
0x16
DESCRIPTION
Empty register byte for testing
purposes. Software can read,
write, set, and clear this register
and the PHY functionality will not
be affected.
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:00
SCRATCH
Scratch data.
RW
0x00
7.5.24 SCRATCH_REG_SET
ADDRESS OFFSET
0x17
PHYSICAL ADDRESS
0x17
DESCRIPTION
This register does not physically
exist.
It is the same as the
scratch_reg register with read/
set-only property (write '1' to set
a particular bit, a write '0' has noaction).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
BITS
7:00
42
FIELD NAME
DESCRIPTION
SCRATCH
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TYPE
RESET
RW
0x00
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7.5.25 SCRATCH_REG_CLR
ADDRESS OFFSET
0x18
PHYSICAL ADDRESS
0x18
DESCRIPTION
This register does not physically
exist.
It is the same as the scratch_reg
with read/clear-only property
(write '1' to clear a particular bit,
a write '0' has no-action).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
4
3
2
1
0
SCRATCH
BITS
7:00
FIELD NAME
DESCRIPTION
SCRATCH
TYPE
RESET
RW
0x00
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7.5.26 VENDOR_SPECIFIC1
ADDRESS OFFSET
0x3D
PHYSICAL ADDRESS
0x3D
DESCRIPTION
Power Control register.
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
SPARE
BITS
5
MNTR_VUSBIN
ID_FLOAT_EN
_OK_EN
FIELD NAME
4
3
ID_RES_EN
BVALID_FALL
2
BVALID_RISE
1
0
SPARE
ABNORMALST
RESS_EN
DESCRIPTION
Reserved. The link must never write a 1b to this bit.
TYPE
RESET
7
SPARE
RW
0
6
MNTR_VUSBIN_OK_EN When set to 1, it enables RX CMDs for high to low or low to high transitions
on MNTR_VUSBIN_OK. This bit is provided for debugging purposes.
RW
0
5
ID_FLOAT_EN
When set to 1, it enables RX CMDs for high to low or low to high transitions
on ID_FLOAT. This bit is provided for debugging purposes.
RW
0
4
ID_RES_EN
When set to 1, it enables RX CMDs for high to low or low to high transitions
on ID_RESA, ID_RESB and ID_RESC. This bit is provided for debugging
purposes.
RW
0
3
BVALID_FALL
Enables RX CMDs for high to low transitions on BVALID. When BVALID
changes from high to low, the USB TRANS will send an RX CMD to the link
with the alt_int bit set to 1b.
RW
0
RW
0
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
2
BVALID_RISE
Enables RX CMDs for low to high transitions on BVALID. When BVALID
changes from low to high, the USB Trans will send an RX CMD to the link
with the alt_int bit set to 1b.
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
44
1
SPARE
Reserved. The link must never write a 1b to this bit.
RW
0
0
ABNORMALSTRESS_E
N
When set to 1, it enables RX CMDs for low to high and high to low
transitions on ABNORMALSTRESS. This bit is provided for debugging
purposes.
RW
0
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7.5.27 VENDOR_SPECIFIC1_SET
ADDRESS OFFSET
0x3E
PHYSICAL ADDRESS
0x3E
DESCRIPTION
This register does not physically
exist.
It is the same as the
func_ctrl register with read/setonly property (write '1' to set a
particular bit, a write '0' has noaction).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATEN CY
7
6
SPARE
5
MNTR_VUSBIN
ID_FLOAT_EN
_OK_EN
BITS
FIELD NAME
4
3
2
1
0
ID_RES_EN
BVALID_FALL
BVALID_RISE
SPARE
ABNORMALST
RESS_EN
TYPE
RESET
7
SPARE
DESCRIPTION
RW
0
6
MNTR_VUSBIN_OK_EN
RW
0
5
ID_FLOAT_EN
RW
0
4
ID_RES_EN
RW
0
3
BVALID_FALL
RW
0
2
BVALID_RISE
RW
0
1
SPARE
RW
0
0
ABNORMALSTRESS_EN
RW
0
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7.5.28 VENDOR_SPECIFIC1_CLR
ADDRESS OFFSET
0x3F
PHYSICAL ADDRESS
0x3F
DESCRIPTION
This register does not physically
exist.
It is the same as the func_ctrl
register with read/clear-only
property (write '1' to clear a
particular bit, a write '0' has noaction).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
SPARE
MNTR_VUSBIN
ID_FLOAT_EN
_OK_EN
BITS
46
5
FIELD NAME
4
3
2
1
0
ID_RES_EN
BVALID_FALL
BVALID_RISE
SPARE
ABNORMALST
RESS_EN
TYPE
RESET
7
SPARE
DESCRIPTION
RW
0
6
MNTR_VUSBIN_OK_EN
RW
0
5
ID_FLOAT_EN
RW
0
4
ID_RES_EN
RW
0
3
BVALID_FALL
RW
0
2
BVALID_RISE
RW
0
1
SPARE
RW
0
0
ABNORMALSTRESS_EN
RW
0
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7.5.29 VENDOR_SPECIFIC2
ADDRESS OFFSET
0x80
PHYSICAL ADDRESS
0x80
DESCRIPTION
Eye diagram programmability and
DP/DM swap control .
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
SPARE
DATAPOLARIT
Y
ZHSDRV
BITS
FIELD NAME
4
3
2
1
0
IHSTX
DESCRIPTION
TYPE
RESET
RW
0
7
SPARE
6
DATAPOLARITY
Control data polarity on dp/dm
RW
1
ZHSDRV
High speed output impedance configuration for eye diagram tuning :
RW
0x0
RW
0x1
5:04
00 45.455 Ω
01 43.779 Ω
10 42.793 Ω
11 42.411 Ω
3:00
IHSTX
High speed output drive strength configuration for eye diagram tuning :
0000 17.928 mA
0001 18.117 mA
0010 18.306 mA
0011 18.495 mA
0100 18.683 mA
0101 18.872 mA
0110 19.061 mA
0111 19.249 mA
1000 19.438 mA
1001 19.627 mA
1010 19.816 mA
1011 20.004 mA
1100 20.193 mA
1101 20.382 mA
1110 20.570 mA
1111 20.759 mA
IHSTX[0] is also the AC BOOST enable
IHSTX[0] = 0 à AC BOOST is disabled
IHSTX[0] = 1 à AC BOOST is enabled
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7.5.30 VENDOR_SPECIFIC2_SET
ADDRESS OFFSET
0x81
PHYSICAL ADDRESS
0x81
DESCRIPTION
This register does not physically
exist.
It is the same as the
VENDOR_SPECIFIC1 register
with read/set-only property (write
'1' to set a particular bit, a write '0'
has no-action).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
SPARE
DATAPOLARIT
Y
ZHSDRV
4
3
2
1
0
IHSTX
BITS
FIELD NAME
TYPE
RESET
7
SPARE
DESCRIPTION
RW
0
6
DATAPOLARITY
RW
1
5:04
ZHSDRV
RW
0x0
3:00
IHSTX
RW
0x1
7.5.31 VENDOR_SPECIFIC2_CLR
ADDRESS OFFSET
0x82
PHYSICAL ADDRESS
0x82
DESCRIPTION
This register does not physically
exist.
It is the same as the
VENDOR_SPECIFIC1 register
with read/clear-only property
(write '1' to clear a particular bit,
a write '0' has no-action).
TYPE
RW
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
5
SPARE
DATAPOLARIT
Y
ZHSDRV
BITS
48
FIELD NAME
4
3
2
1
0
IHSTX
DESCRIPTION
TYPE
RESET
7
SPARE
RW
0
6
DATAPOLARITY
RW
1
5:04
ZHSDRV
RW
0x0
3:00
IHSTX
RW
0x1
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7.5.32 VENDOR_SPECIFIC1_STS
ADDRESS OFFSET
0x83
PHYSICAL ADDRESS
0x83
DESCRIPTION
Indicates the current value of the
interrupt source signal.
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATEN CY
7
Reserved
6
5
4
3
2
MNTR_VUSBIN ABNORMALST
ID_FLOAT_STS ID_RESC_STS ID_RESB_STS
_OK_STS
RESS_STS
BITS
FIELD NAME
7
Reserved
DESCRIPTION
1
0
ID_RESA_STS
BVALID_STS
TYPE
RESET
R
0
6
MNTR_VUSBIN_OK_STS
Current value of MNTR_VUSBIN_OK output
R
0
5
ABNORMALSTRESS_STS
Current value of ABNORMALSTRESS output
R
0
4
ID_FLOAT_STS
Current value of ID_FLOAT output
R
0
3
ID_RESC_STS
Current value of ID_RESC output
R
0
2
ID_RESB_STS
Current value of ID_RESB output
R
0
1
ID_RESA_STS
Current value of ID_RESA output
R
0
0
BVALID_STS
Current value of VB_SESS_VLD output
R
0
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7.5.33 VENDOR_SPECIFIC1_LATCH
ADDRESS OFFSET
0x84
PHYSICAL ADDRESS
0x84
DESCRIPTION
These bits are set by the
PHY when an unmasked change
occurs on the corresponding
internal signal. The PHY will
automatically clear all bits when
the Link reads this register,
or when Low Power Mode is
entered. The PHY also clears
this register when Serial mode is
entered regardless of the value of
ClockSuspendM.
The PHY follows the rules
defined in Table 26 of the ULPI
spec for setting any latch register
bit.
TYPE
R
INSTANCE
USB_SCUSB
WRITE LATENCY
7
6
Reserved
BITS
50
5
4
3
MNTR_VUSBIN ABNORMALST ID_FLOAT_LAT ID_RESC_LAT
_OK_LATCH
RESS_LATCH
CH
CH
FIELD NAME
2
1
ID_RESB_LAT
CH
0
ID_RESA_LAT
BVALID_LATCH
CH
DESCRIPTION
TYPE
RESET
7
Reserved
R
0
6
MNTR_VUSBIN_OK_LATCH
Set to 1 when an unmasked event occurs on MNTR_VUSBIN_OK_LATCH.
Clear on read register.
R
0
5
ABNORMALSTRESS_LATCH
Set to 1 when an unmasked event occurs on ABNORMALSTRESS. Clear on
read register.
R
0
4
ID_FLOAT_LATCH
Set to 1 when an unmasked event occurs on ID_FLOAT. Clear on read
register.
R
0
3
ID_RESC_LATCH
Set to 1 when an unmasked event occurs on ID_RESC. Clear on read
register.
R
0
2
ID_RESB_LATCH
Set to 1 when an unmasked event occurs on ID_RESB. Clear on read
register.
R
0
1
ID_RESA_LATCH
Set to 1 when an unmasked event occurs on ID_RESA. Clear on read
register.
R
0
0
BVALID_LATCH
Set to 1 when an unmasked event occurs on VB_SESS_VLD. Clear on read
register.
R
0
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7.5.34 VENDOR_SPECIFIC3
ADDRESS OFFSET
0x85
PHYSICAL ADDRESS
0x85
INSTANCE
USB_SCUSB
DESCRIPTION
TYPE
RW
WRITE LATENCY
7
6
RESERVED
BITS
SOF_EN
5
CPEN_OD
4
CPEN_ODOS
FIELD NAME
7
Reserved
6
SOF_EN
3
2
IDGND_DRV
VUSB3V3_VSE
L
DESCRIPTION
0: HS USB SOF detector disabled.
1
0
TYPE
RESET
RW
0
RW
0
RW
0
RW
0
1: Enable HS USB SOF detection when PHY is set in device mode.
SOF are output on CPEN pin. HS USB SOF (start-of-frame) output
clock is available on CPEN pin when this bit is set. HS USB SOF
packet rate is 8 kHz.
This bit is provided for debugging purpose only. It must never been
write to ‘1’ in functional mode
5
CPEN_OD
This bit has no effect when CPEN_ODOS = ‘0’, else :
0: CPEN pad is in OS (Open Source) mode.
In this case CPEN pin has an internal NMOS driver, and will be active
LOW.
Externally there should be a pullup resistor on CPEN (min 1kΩ) to a
supply voltage (max 3.6V).
1: CPEN pad is in OD (Open Drain) mode
In this case CPEN pin has an internal PMOS driver, and will be active
HIGH.
Externally there should be a pull-down resistor on CPEN (min 1 kΩ to
GND.
4
CPEN_ODOS
Mode selection bit for CPEN pin.
0 : CPEN pad is in CMOS mode
1: CPEN pad is in OD (Open Drain) or OS (Open Source) mode
(controlled by CPEN_OD bit)
3
2:00
IDGND_DRV
Drives ID pin to ground
RW
0x0
VUSB3V3_VSEL
000 VRUSB3P1V = 2.5 V
RW
0x3
001 VRUSB3P1V = 2.75 V
010 VRUSB3P1V = 3.0 V
011 VRUSB3P1V = 3.10 V (default)
100 VRUSB3P1V = 3.20 V
101 VRUSB3P1V = 3.30 V
110 VRUSB3P1V = 3.40 V
111 VRUSB3P1V = 3.50 V
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7.5.35 VENDOR_SPECIFIC3_SET
ADDRESS OFFSET
0x86
PHYSICAL ADDRESS
0x86
INSTANCE
USB_SCUSB
DESCRIPTION
TYPE
RW
WRITE LATENCY
7
RESERVED
6
5
SOF_EN
CPEN_OD
BITS
FIELD NAME
7
6
4
CPEN_ODOS
3
2
IDGND_DRV
VUSB3V3_VSE
L
1
DESCRIPTION
0
TYPE
RESET
Reserved
RW
0
SOF_EN
RW
0
5
CPEN_OD
RW
0
4
CPEN _ODOS
RW
0
3
IDGND_DRV
RW
0x0
2:00
VUSB3V3_VSEL
RW
0x3
7.5.36 VENDOR_SPECIFIC3_CLR
ADDRESS OFFSET
0x87
PHYSICAL ADDRESS
0x87
INSTANCE
USB_SCUSB
DESCRIPTION
TYPE
RW
WRITE LATENCY
7
RESERVED
52
6
5
SOF_EN
CPEN_OD
4
CPEN_ODOS
3
2
IDGND_DRV
VUSB3V3_VSE
L
DESCRIPTION
1
0
BITS
FIELD NAME
TYPE
RESET
7
Reserved
RW
0
6
SOF_EN
RW
0
5
CPEN_OD
RW
0
4
CPEN_ODOS
RW
0
3
IDGND_DRV
RW
0x0
2:00
VUSB3V3_VSEL
RW
0x3
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
Figure 8-1 shows the suggested application diagram (Host or OTG, ULPI input-clock mode).
8.2 Typical Application
8.2.1 Host or OTG, ULPI Input Clock Mode Application
Figure 8-1 shows a suggested application diagram for TUSB1210 in the case of ULPI input-clock mode (60 MHz
ULPI clock is provided by link processor), in Host or OTG application. Note: this is just one example, it is of
course possible to operate as HOST or OTG while also in ULPI output-clock mode.
(See Note A)
14
CFG
11
CS
17
12
VBUS Switch
RESETB
CPEN
VDD15
CVDD15
EN
5V
IN
22
OUT
VBUS
3.1–5.5 V
Supply
21
CBYP
USB Receptacle
ESD
VBUS
ID
B.
C.
D.
E.
13
DATA6
10
DATA5
9
DATA4
7
DATA3
6
DATA2
5
DATA1
4
DATA0
3
STP
29
NXT
2
DIR
31
CLOCK
VDD33
CVDD33
23
DM
19
DP
18
ID
DM
RESETB
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
NXT
DIR
1 (See Note B)
CLOCK
DP
26
VDDIO
32
VDD18
28, 30
N/C
N/C
SHIELD
N/C
GND
N/C
GND
A.
DATA7
REFCLK
VBAT
CS_OUT
27 (See Note D)
(See Note C)
20
CVBUS
Link Controller
TUSB1210
VDDIO Supply
N/C
VDDIO Supply
1.8-V Supply
25
CVDDIO
CVDD18
24
16
15
8
(See Note E)
Pin 11 (CS): can be tied high to VIO if the CS_OUT pin is unavailable; Pin 14 (CFG): tie-high is do not care since the ULPI clock is used
in input mode
Pin 1 (REFCLK): must be tied low
Ext 3 V supply supported
Pin 27 (RESETB) can be tied to VDDIO if unused.
Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 8-1. Host or OTG, ULPI Input Clock Mode Application Diagram
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8.2.1.1 Design Requirements
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VBAT
3.3 V
VDDIO
1.8 V
VBUS
5.0 V
USB Support
HS, FS, LS
USB On the Go (OTG)
Yes
Clock Sources
60 MHz Clock
8.2.1.2 Detailed Design Procedure
Connect the TUSB1210 device as is shown in Figure 8-1.
Follow the Board Guidelines in the TUSB121x USB2.0 Board Guidelines application report.
8.2.1.2.1 Unused Pins Connection
•
•
•
VBUS: Input. Recommended to tie to GND if unused. However, leaving VBUS floating is also acceptable since
internally there is an 80 kΩ resistance to ground.
REFCLK: Input. If REFCLK is unused and 60 MHz clock is provided by MODEM (60 MHz should be
connected to CLOCK pin in this case), then tie REFCLK to GND.
CFG: Tie to GND if REFCLK is 19.2 MHz, or tie to VDDIO if REFCLK is 26 MHz. Tie to either GND or VDDIO
(does not matter which) if REFCLK is not used (for example, ULPI input clock configuration).
8.2.1.3 Application Curve
Figure 8-2. High-Speed Eye Diagram
54
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8.2.2 Device, ULPI Output Clock Mode Application
Figure 8-3 shows a suggested application diagram for TUSB1210 in the case of ULPI output clock mode (60
MHz ULPI clock is provided by TUSB1210, while link processor or another external circuit provides REFCLK), in
Device mode application. Note: this is just one example, it is of course possible to operate as Device while also
in ULPI input-clock mode. Refer also to Figure 8-1.
(See Note A)
RESETB
14
CFG
11
CS
17
12
CPEN
VDD15
CVDD15
22
21
USB Receptacle
ESD
VBUS
DATA6
DATA5
9
DATA4
7
DATA3
6
DATA2
5
DATA1
4
DATA0
3
VDD33
CVDD33
23
DIR
31
1
26
32
VDD18
28, 30
ID
DM
DM
N/C
DP
18
DP
N/C
N/C
N/C
GND
GND
B.
C.
D.
E.
2
VDDIO
SHIELD
A.
NXT
19
N/C
DATA6
DATA4
DATA3
29
CLOCK
DATA7
DATA5
STP
VBAT
(See Note C)
20
CVBUS
13
10
REFCLK
Supply
CS_OUT
RESETB
27 (See Note D)
DATA7
VBUS
3.1–5.5 V
CBYP
Link Controller
TUSB1210
VDDIO Supply
DATA2
DATA1
DATA0
STP
NXT
(See Note B)
DIR
CLKIN
REFCLK
VDDIO Supply
1.8-V Supply
25
CVDDIO
CVDD18
24
16
15
8
(See Note E)
Pin 11 (CS): can be tied high to VIO if CS_OUT pin unavailable; Pin 14 (CFG): Tied to VDDIO for 26 MHz REFCLK mode here, tie to
GND for 19.2 MHz mode.
Pin 1 (REFCLK): connect to external 3.3 V square-wave reference clock
Ext 3 V supply supported
Pin 27 (RESETB) can be tied to VDDIO if unused.
Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 8-3. Device, ULPI Output Clock Mode Application Diagram
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8.2.2.1 Design Requirements
Table 8-2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VBAT
3.3 V
VDDIO
1.8 V
VBUS
5.0 V
USB Support
HS, FS, LS
Clock Sources
26 MHz or 19.2 MHz Oscillator
8.2.2.2 Detailed Design Procedure
Connect the TUSB1210 device as is shown in Figure 8-3.
Follow the Board Guidelines in the TUSB121x USB2.0 Board Guidelines application report.
8.2.2.2.1 Unused Pins Connection
•
•
•
ID: Input. Leave floating if unused or TUSB1210 is Device mode only. Tie to GND through RID < 1 kΩ if Host
mode.
REFCLK: Input. If REFCLK is unused, and 60 MHz clock is provided by MODEM (60 MHz should be
connected to CLOCK pin in this case) then tie REFCLK to GND.
CFG: Tie to GND if REFCLK is 19.2 MHz, or tie to VDDIO if REFCLK is 26 MHz. Tie to either GND or VDDIO
(does not matter which) if REFCLK not used (for example, ULPI input clock configuration).
8.2.2.3 Application Curve
Figure 8-4. Full-Speed Eye Diagram
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8.3 External Components
Table 8-3. TUSB1210 External Components
FUNCTION
COMPONENT
REFERENCE
VALUE
NOTE
LINK
VDDIO
Capacitor
CVDDIO
100 nF
Suggested value, application
dependent
Figure 8-1
VDD33
Capacitor
CVDD33
2.2 μF
Range: [0.45 μF: 6.5 μF] ,
ESR = [0: 600 mΩ] for f> 10 kHz
Figure 8-1
VDD15
Capacitor
CVDD15
2.2 μF
Range: [0.45 μF: 6.5 μF] ,
ESR = [0: 600 mΩ] for f> 10 kHz
Figure 8-1
VDD18
Capacitor
Ext 1.8V supply
100 nF
Suggested value, application
dependent
Figure 8-1
CVDD18
(1)
VBAT
Capacitor
CBYP
100 nF(1)
Range: [0.45 μF: 6.5 μF] ,
ESR = [0: 600 mΩ] for f> 10 kHz
Figure 8-1
VBUS
Capacitor
CVBUS
See Table 8-4
Place close to USB connector
Figure 8-1
Recommended value but 2.2 µF may be sufficient in some applications
Table 8-4. TUSB1210 VBUS Capacitors
FUNCTION
COMPONENT
REFERENCE
VALUE
NOTE
LINK
VBUS – HOST
Capacitor
CVBUS
>120 μF
VBUS – DEVICE
Capacitor
CVBUS
4.7 μF
Range: 1.0 μF to 10.0 μF
Figure 8-1
Figure 8-1
VBUS – OTG
Capacitor
CVBUS
4.7 μF
Range: 1.0 μF to 6.5 μF
Figure 8-1
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9 Power Supply Recommendations
VBUS, VBAT, and VDDIO are needed to power the TUSB1210. Recommended operation is for VBAT to be present
before VDDIO. Applying VDDIO before VBAT to TUSB1210 is not recommended as there is a diode from VDDIO to
VBAT which will be forward biased when VDDIO is present but VBAT is not present. TUSB1210 does not strictly
require VBUS to function.
9.1 TUSB1210 Power Supply
•
•
•
•
The VDDIO pins of the TUSB1210 supply 1.8 V (nominal) power to the core of the TUSB1210. This power rail
can be isolated from all other power rails by a ferrite bead to reduce noise.
The VBAT pin of the TUSB1210 supply 3.3 V (nominal) power rail to the TUSB1210. This power rail can be
isolated from all other power rails by a ferrite bead to reduce noise.
The VBUS pin of the TUSB1210 supply 5.0 V (nominal) power rail to the TUSB1210. This pin is normally
connected to the VBUS pin of the USB connector.
The VBUS pin of the TUSB1210 supply 5.0 V (nominal) power rail to the TUSB1210. This pin is normally
connected to the VBUS pin of the USB connector.
9.2 Ground
It is recommended that almost one board ground plane be used in the design. This provides the best image
plane for signal traces running above the plane. An earth or chassis ground is implemented only near the USB
port connectors on a different plane for EMI and ESD purposes.
9.3 Power Providers
Table 9-1 is a summary of TUSB1210 power providers.
Table 9-1. Power Providers(1)
(1)
NAME
USAGE
TYPE
TYPICAL
VOLTAGE (V)
MAXIMUM
CURRENT (mA)
VDD15
Internal
LDO
1.5
50
VDD18
External
LDO
1.8
30
VDD33
Internal
LDO
3.1
15
VDD33 may be supplied externally or by shorting the VDD33 pin to VBAT pin, provided VBAT minimum
is in range [3.2 V: 3.6 V]. Note that the VDD33 LDO will always power-on when the chip is enabled,
irrespective of whether VDD33 is supplied externally or not. In the case the VDD33 pin is not supplied
externally in the application, the electrical specifications for this LDO are provided below.
9.4 Power Modules
9.4.1 VDD33 Regulator
The VDD33 internal LDO regulator powers the USB PHY, charger detection, and OTG functions of the USB
subchip inside TUSB1210. Section 6.12 describes the regulator characteristics.
VDD33 regulator takes its power from VBAT.
Since the USB2.0 standard requires data lines to be biased with pullups biased from a supply greater than 3 V,
and since VDD33 regulator has an inherent voltage drop from its input, VBAT, to its regulated output, TUSB1210
will not meet USB 2.0 Standard if operated from a battery whose voltage is lower than 3.3 V.
9.4.2 VDD18 Supply
The VDD18 supply is powered externally at the VDD18 pin. See Table 8-3 for external components.
9.4.3 VDD15 Regulator
The VDD15 internal LDO regulator powers the USB subchip inside TUSB1210. Section 6.12 describes the
regulator characteristics.
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9.5 Power Consumption
Table 9-2 describes the power consumption depending on the use cases.
Note
The typical power consumption is obtained in the nominal operating conditions and with the
TUSB1210 standalone.
Table 9-2. Power Consumption
MODE
OFF Mode
Suspend Mode
HS USB Operation
(Synchronous Mode)
FS USB Operation
(Synchronous Mode)
Reset Mode
CONDITIONS
VBAT = 3.6 V,
VDDIO = 1.8 V,
VDD18 = 1.8 V, CS = 0 V
VBUS = 5 V,
VBAT = 3.6 V,
VDDIO = 1.8 V, No clock
VBAT = 3.6 V,
VDDIO = 1.8 V,
VDD18 = 1.8 V, active USB transfer
VBAT = 3.6 V,
VDDIO = 1.8 V,
active USB transfer
RESETB = 0 V, VBUS = 5 V,
VBAT = 3.6 V,
VDDIO = 1.8 V, No clock
SUPPLY
TYPICAL
CONSUMPTION
IVBAT
8
IVDDIO
3
IVDD18
5
ITOTAL
16
IVBAT
204
IVDDIO
3
IVDD18
3
ITOTAL
210
IVBAT
24.6
IVDDIO
1.89
IVDD18
21.5
ITOTAL
48
IVBAT
25.8
IVDDIO
1.81
IVDD18
4.06
ITOTAL
31.7
IVBAT
237
IVDDIO
3
IVDD18
3
ITOTAL
243
UNIT
µA
µA
mA
mA
µA
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10 Layout
10.1 TUSB121x USB2.0 Product Family Board Layout Recommendations
Table 10-1. TUSB121x USB2.0 Product Family Board Layout Recommendations
Item
USB General Considerations
1.00
USB design requires symmetrical termination and symmetrical component placement along the DP and DM paths.
1.01
Place the USB host controller and major components on the unrouted board first.
1.02
Place the USB host controller, as close as possible to the transceiver device, that is, ULPI interface traces as short as possible.
1.03
Route high-speed clock and high-speed USB. Route differential pairs first.
Since these signals are critical and long length traces are to be avoided, it is therefore recommended to route DP/DM before routing less critical signals on the board. A
similar recommendation is true for CLK, and ULPI signals which should be routed with equalized trace length.
1.04
Maintain maximum possible distance between high-speed clocks/periodic signals to high speed USB differential pairs and any connector leaving the PCB (such as I/O
connectors, control, and signal headers or power connectors).
1.05
Place the USB receptacle at the board edge.
1.06
Maximum TI-recommended external capacitance on DP (or DM) lines is 4 pF
•
•
This capacitance is the sum of all external discrete components, that is, the total capacitance on DP (or DM) lines including trace capacitance can be larger than 4
pF.
All discrete components should be placed as close as possible to the USB receptacle.
1.07
Place the low-capacitance ESD protections as close as possible to the USB receptacle, with no other external devices in between.
1.08
Common mode chokes degrade signal quality, thus they should only be used if EMI performance enhancement is absolutely necessary.
1.09
Place the common mode choke (if required to improve EMI performance) as close as possible to the USB receptacle (but after one or more of the ESD devices).
USB Interface (DP, DM)
60
2.00
Separate signal traces into similar categories and route similar signal traces together, that is, DP/DM and ULPI.
2.01
Route the USB receptacle ground pin to the analog ground plane of the device with multiple via connections.
2.02
Route the DP/DM trace pair together.
2.03
For HS-capable devices, route the DP/DM signals from the device to the USB receptacle with an optimum trace length of 5 cm. Maximum trace length 1-way delay of 0.5
ns (7.5 cm for 67 ps/cm in FR-3).
2.04
Match the DP/DM trace lengths. Maximum mismatch allowable is 150 mils (≈0.4 cm).
2.05
Route the DP/DM signals with 90 Ω differential impedance, and 22.5≈30-Ω common-mode impedance (objective is to have Zodd ≈ Z0 = Zdiff/2 = 45 Ω).
2.06
Use an impedance calculator to determine the trace width and spacing required for the specific board stack up being used.
2.07
Keep the maximum possible distance between DP and DM signals from the other platform clocks, power sources and digital or analog signals.
2.08
Do not route DP/DM signals over or under crystals, oscillators, clock synthesizers, magnetic devices, or ICs that use clocks.
2.09
Avoid changing the routing layer for DP/DM traces. If unavoidable, use multiple vias.
2.10
Minimize bends and corners on DP/DM traces.
2.11
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal by minimizing impedance
discontinuities.
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Table 10-1. TUSB121x USB2.0 Product Family Board Layout Recommendations (continued)
Item
USB General Considerations
2.12
Avoid creating stubs on the DP/DM traces as stubs cause signal reflections and affect global signal quality.
2.13
If stubs are unavoidable, they must be less than 200 mils (≈0.5 cm).
2.14
Route DP/DM signals over continuous VCC or GND planes, without interruption, avoiding crossing anti-etch (plane splits), which increase both inductance and radiation
levels by introducing a greater loop area.
2.15
Route DP/DM signals with at least 25 mils (≈0.65 mm) away from any plane splits.
2.16
Follow the 20×h thumb rule by keeping traces at least 20×(height above the plane) away from the edge of the plane (VCC or GND, depending on the plane the trace is
over).
2.17
Changing signal layers is preferable to crossing plane splits if a choice must be made.
2.18
If crossing a plane split is completely unavoidable, proper placement of stitching capacitors can minimize the adverse effects on EMI and signal quality performance
caused by crossing the split.
2.19
Avoid anti-etch on the ground plane.
ULPI Interface (ULPIDATA, ULPICLK, ULPINXT, ULPIDIR, ULPISTP)
3.00
Route ULPI 12-pin bus as a 50 Ω single-ended adapted bus.
3.01
Route ULPI 12-pin bus with minimum trace lengths and a strict maximum of 90 mm, to ensure timing. (Timing budget 600 ps maximum 1-way delay assuming 66 ps/cm.)
3.02
Route ULPI 21-pin bus equalizing paths lengths as much as possible to have equal delays.
3.03
Route ULPI 12-pin bus as clock signals and set a minimum spacing of 3 times the trace width (S < 3W).
3.04
If the 3W minimum spacing is not respected, the minimum spacing for clock signals based on EMI testing experience is 50 mils (1.27 mm).
3.05
Route ULPI 12-pin bus with a dedicated ground plane.
3.06
Place and route the ULPI monitoring buffers as close as possible from the device ULPI bus (on test boards).
USB Clock (USBCLKIN, CLK_IN1, CLK_IN0)
4.00
Route the USB clock with the minimum possible trace length.
4.01
Keep the maximum possible distance between the USB clock and the other platform clocks, power sources, and digital and analog signals.
4.02
Route the USBCLKIN, CLK_IN1 and CLK_IN0 inputs as 50 Ω single-ended signals.
USB Power Supply (VBUS, REG3V3, REG1V5, VBAT)
5.00
VBUS must be a power plane from the device VBUS ball to the USB receptacle, or if a power plan is not possible, VBUS must be as large as possible.
5.01
Power signals must be wide to accommodate current level.
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10.2 Layout Guidelines
•
•
•
•
The VDDIO pins of the TUSB1210 supply 1.8 V (nominal) power to the core of the TUSB1210. This power rail
can be isolated from all other power rails by a ferrite bead to reduce noise.
The VBAT pin of the TUSB1210 supply 3.3 V (nominal) power rail to the TUSB1210. This power rail can be
isolated from all other power rails by a ferrite bead to reduce noise.
The VBUS pin of the TUSB1210 supply 5 V (nominal) power rail to the TUSB1210. This pin is normally
connected to the VBUS pin of the USB connector.
All power rails require 0.1 μF decoupling capacitors for stability and noise immunity. The smaller decoupling
capacitors should be placed as close to the TUSB1210 power pins as possible with an optimal grouping of
two of differing values per pin.
10.3 Layout Example
Figure 10-1. TUSB1210 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.2 Documentation Support
SLLZ066 Silicon Errata. Describes the known exceptions to the functional specifications for the TUSB1210Q1.
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, TUSB121x USB2.0 Board Guidelines application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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14-May-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TUSB1210BRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
T1210B
TUSB1210BRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
T1210B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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