UC2914DW


  SLUS425C − DECEMBER 2003 − REVISED JULY 2004         FEATURES D 5-V to 35-V Operation D Precision Maximum Current Control D Precision Fault Threshold D Programmable Average Power Limiting D Programmable Overcurrent Limit D Shutdown Control D Charge Pump for Low RDS(on) High-Side The UC3914 family of hot swap power managers provides complete power management, hot swap and fault handling capability. Integrating this part and a few external components, allows a board to be swapped in or out upon failure or system modification without removing power to the hardware, while maintaining the integrity of the powered system. Complementary output drivers and diodes have been integrated for use with external capacitors as a charge pump to ensure sufficient gate drive to the external N-channel MOSFET transistor for low RDS(on). All control and housekeeping functions are integrated and externally programmable and include the fault current level, maximum output sourcing current, maximum fault time and average power limiting of the external FET. The UC3914 features a duty ratio current limiting technique, which provides peak load capability while limiting the average power dissipation of the external pass transistor during fault conditions. The fault level is fixed at 50 mV with respect to VCC to minimize total dropout. Drive Latch Reset Function Available Output Drive VGS Clamping Fault Output Indication 18-Pin DIL and SOIC Packages SIMPLIFIED APPLICATION DIAGRAM 6 9 18 16 OSC PMP REF 1 VCC IMAX PMPB VCC 2 SENSE 17 OUT 11 The fault current level is set with an external current sense resistor. The maximum allowable sourcing current is programmed by using a resistor divider from VCC to REF to set the voltage on IMAX. The maximum current level, when the output appears as a current source is (VVCC − VIMAX)/RSENSE. VOUTS 12 This part is offered in both 18-pin DW wide-body (SOIC) and dual-in-line (DIL) packages. UC2914/UC3914 5 OSCB 7 VPUMP 4 VOUT 10 SD FAULT PLIM 14 GND LR CT 1 13 15 VOUT VCC UDG−03114 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 
   !"  # #$% & '(#%  )$  !"*$  '$%+ &)"%$  '$*$, &!$- )""#$%# '"" "' )$ %&$##" % "$ '$%+ + ",%- $."% %(!$% $%$*$% )$ +)  #)"+$  '%# ($ )$%$ & '(#% /) (  #$- Copyright  2003, Texas Instruments Incorporated www.ti.com 1 PRODUCT PREVIEW D D D D DESCRIPTION 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 DESCRIPTION (continued) When the output current is less than the fault level, the external output transistor remains switched on. When the output current exceeds the fault level, but is less than the maximum sourcing level programmed by IMAX, the output remains switched on, and the fault timer starts to charge CT, a timing capacitor. Once CT charges to 2.5 V, the output device is turned off and CT is slowly discharged. Once CT is discharged to 0.5 V, the device performs a retry and the output transistor is switched on again. The UC3914 offers two distinct reset modes. In one mode with LR left floating or held low, the device tries to reset itself repeatedly if a fault occurs as described above. In the second mode with LR held high, once a fault occurs, the output is latched off until either LR is toggled low, the part is shutdown then re−enabled using SD, or the power to the part is turned off and then on again. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted.(1)(2) UC2914 UC3914 Input supply voltage PRODUCT PREVIEW Maximum forced voltage Maximum current Maximum voltage VCC 40 SD, LR 12 IMAX VCC FAULT 20 PLIM 10 FAULT Reference output current UNIT V mA 40 V internally limited A Storage temperature range, Tstg −65 to 150 Junction temperature range, TJ −55 to 150 °C C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability (2) Currents are positive into and negative out of the specifief terminal unless otherwise noted. All voltage values are with respect to the network ground terminal. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT 5 35 V UC2914 −40 85 UC3914 0 70 Supply voltage, VCC Operating free-air temperature range, TA 2 www.ti.com NOM °C 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C for the UC3914, −40°C to 85°C for the UC2914, VCC = 12V, VPUMP = VPUMP(max), SD = 5 V, CP1 = CP2 = CPUMP= 0.01 µF. TA = TJ. (Unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS ICC Supply current(2) ICCSD Shutdown supply current 8 15 12 20 500 900 µA 4.0 4.4 V 55 120 250 mV −55 −50 −45 −57 −50 −42 1 3 −140 −100 −60 −6.0 −3.0 −1.5 mA 2.0 3.0 4.5 µA VCC = 35 V SD = 0 V, UVLO turn−on threshold voltage UVLO hysteresis mA FAULT TIMING TJ = 25°C, wrt VCC Over operating temperature wrt VCC IMAX input bias ICT_CHG CT charge current VCT = 1 V VCT = 1 V, ICT_DSCH VCT_FLT CT discharge current VCT = 1 V CT fault threshold voltage 2.25 2.50 2.75 VCT_RST CT reset threshold voltage 0.45 0.50 0.55 1.5% 3.0% 4.5% −1.5 −1.0 −2.0 −1.5 Output duty cycle overload condition Fault condition, IPL = 0 A VVOUTS = VCC, wrt VPUMP VPUMP = VPUMP(max), mV µA A PRODUCT PREVIEW Overcurrent threshold V OUTPUT VOH VOL VOUT(cl) tRISE High-level output voltage Low-level output voltage VVOUTS = VCC, VPUMP = VPUMP(max), IOUT = −2 mA, wrt VPUMP IOUT = 0 A IOUT = 5 mA IOUT = 25 mA, VVOUTS = 0 V overload condition Output clamp voltage Rise time(1) VOUTS = 0 V COUT = 1 nF tFALL Fall time(1) LINEAR CURRENT AMPLIFIER COUT = 1 nF VIO 11.5 Input offset voltage Voltage gain VIMAX IMAX control voltage VIMAX = VOUT, VIMAX = VOUT, VSENSE = VVCC, wrt VCC VSENSE = VREF, wrt REF 0.8 1.3 1 2 1.2 1.8 13.0 14.5 750 1250 250 500 −15 0 15 60 80 −20 0 20 −20 0 20 1.5 3.5 SENSE input bias V ns mV dB mV µA SHUTDOWN Shutdown threshold voltage input current 0.6 SD = 5 V Delay to output time(1) 1.5 2.0 V 150 300 µA 0.5 2.0 µs (1) Ensured by design. Not production tested. (2) A mathematical averaging is used to determine this value. See Application Section for more information. www.ti.com 3 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C for the UC3914, −40°C to 85°C for the UC2914, VCC = 12V, VPUMP = VPUMP(max), SD = 5 V, CP1 = CP2 = CPUMP= 0.01 µF. TA = TJ. (Unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CHARGE PUMP fOSC, fOSCB VOH VOL Oscillator frequency OSC, OSCB High-level output voltage Low-level output voltage Output clamp voltage ILIM Output current limit Pump diode voltage drop PMP clamp voltage PRODUCT PREVIEW VPUMP maximum voltage VPUMP hysteresis 60 150 250 IOSC = −5 mA IOSC = 5 mA 10.0 11.0 11.6 0.2 0.5 VCC = 25 V High side only 18.5 20.5 22.5 −20 −10 −3 0.5 0.9 1.3 18.5 20.5 22.5 20 22 24 VVOUTS = VCC charge pump disable threshold, VCC = 35 V 42 45 48 VVOUTS = VCC charge pump re-enable threshold, VCC = 12 V 0.3 0.7 1.4 VVOUTS = VCC charge pump re-enable threshold, VCC = 35 V 0.25 0.70 1.40 −2.25 −2.00 −1.75 V 12.5 20.0 50.0 mA IDIODE = 10 mA, measured from PMP to PMPB, PMPB to VPUMP VCC = 25 V VVOUTS = VCC charge pump disable threshold, VCC = 12 V kHz V V mA V REFERENCE REF output voltage wrt VCC REF current limit Load regulation 1 mA ≤ IVREF ≤ 5 mA 25 60 Line regulation 5 V ≤ VVCC ≤ 35 V 25 100 Low-level output voltage IFAULT = 1 mA VFAULT = 35 V 100 200 mV Output leakage 10 500 nA Latch release threshold voltage High-to-low Input current VLR = 5 V mV FAULT LATCH 0.6 1.4 2.0 V 500 750 µA POWER LIMITING Duty cycle control IPLIM = 200 µA IPLIM = 3 mA In fault mode 0.6% 1.3% 2.0% In fault mode 0.05% 0.12% 0.20% 500 1250 ns −250 −200 −150 mV OVERLOAD Delay-to-output time(1) Threshold voltage wrt IMAX (1) Ensured by design. Not production tested. (2) A mathematical averaging is used to determine this value. See Application Section for more information. 4 www.ti.com 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC DIL−18 (N) PLASTIC SOIC (DW)(1) −40°C to 85°C UC2914N UC2914DW 0°C to 70°C UC3914N UC3914DW (1) The DW package is available taped and reeled. Add an TR suffix to the device type (e.g. UC2914DWTR) to order quantities of 2,000 devices per reel. DIL−18 N PACKAGE (TOP VIEW) GND VCC N/C SD OSCB OSC VPUMP PMPB PMP 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 REF SENSE IMAX CT PLIM LR VOUTS OUT FAULT GND VCC N/C SD OSCB OSC VPUMP PMPB PMP 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 REF SENSE IMAX CT PLIM LR VOUTS OUT FAULT PRODUCT PREVIEW SOIC−18 DW PACKAGE (TOP VIEW) BLOCK DIAGRAM UDG−95134−2 www.ti.com 5 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 TERMINAL FUNCTIONS TERMINAL NAME NO. PRODUCT PREVIEW DESCRIPTION CT 15 I/O A capacitor is connected to this pin in order to set the maximum fault time. The minimum fault time must be more than the time to charge external load capacitance. The fault time is defined as shown in equation (1) where ICH = 100 µA + IPL, where IPL is the current into the power limit pin. Once the fault time is reached the output shuts down for a time given by equation (2) where IDIS is nominally 3 µA.. FAULT 10 O Open collector output which pulls low upon any of the following conditions: timer fault, shutdown, UVLO. This pin MUST be pulled up to VVCC or another supply through a suitable impedance. GND 1 − Ground reference for the device. I This pin programs the maximum allowable sourcing current. Since REF is a −2-V reference (with respect to VCC), a voltage divider can be derived from VCC to REF in order to generate the program level for the IMAX pin. The current level at which the output appears as a current source is equal to the voltage on the IMAX pin, with respect to VCC, divided by the current sense resistor. If desired, a controlled current startup can be programmed with a capacitor on IMAX to VCC. IMAX 16 LR 13 I If this pin is held high and a fault occurs, the timer is prevented from resetting the fault latch when CT is discharged below the reset comparator threshold. The part does not retry until this pin is brought to a logic low or a power-on-reset occurs. Pulling this pin low before the reset time is reached does not clear the fault until the reset time is reached. Floating or holding this pin low results in the part repeatedly trying to reset itself if a fault occurs. OUT 11 O Output drive to the MOSFET pass element. Internal clamping ensures that the maximum VGS drive is 15 V. OSC 6 O OSCB 5 O Complementary output drivers for intermediate charge pump stages. A 0.01-µF capacitor should be placed between OSC and PMP, and OSCB and PMPB. PLIM 14 I PMP 9 I PMPB 8 I REF 18 O −2-V reference with respect to VCC used to program the IMAX pin voltage. A 0.1-µF ceramic or tantalum capacitor MUST be tied between this pin and VCC to ensure proper operation of the device. SD 4 I When this TTL-compatible input is brought to a logic low, the output of the linear amplifier is driven low, FAULT is pulled low and the device is put into a low power mode. The ABSOLUTE maximum voltage that can be placed on this pin is 12 V. SENSE 17 I Input voltage from the current sense resistor. When there is greater than 50 mV on this pin with respect to VCC, a fault is sensed and CT begins to charge. VCC 2 I Input voltage to the device. The voltage range is from 4.5 V to 35 V. The minimum input voltage required for operation is 4.5 V. VOUTS 12 O Source connection of external N-channel MOSFET and sensed output voltage of load. VPUMP 7 O Charge pump output voltage. A capacitor should be tied between this pin and VOUTS with a typical value being 0.01-µF. T FAULT + T SD + 2 2 This feature ensures that the average MOSFET power dissipation is controlled. A resistor is connected from this pin to VCC. Current flows into PLIM, adding to the fault timer charge current, reducing the duty cycle from the typical 3% level. When IPL >> 100 µA then the average MOSFET power dissipation is given by equation (3). Complementary pins which couple charge pump capacitors to internal diodes and are used to provide charge to the reservoir capacitor tied to VPUMP. Typical capacitor values used are 0.01-µF. CT I CH (1) CT I DIS P FET(avg) + I MAX 6 I/O (2) 3 10 *6 R PL (3) www.ti.com 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION The UC3914 is to be used in conjunction with external passive components and an N-channel MOSFET to facilitate hot swap capability of application modules. A typical application setup is given in Figure 1. C1 R1 PMP OSC 9 REF 6 VCC 18 T CP2 16 Overload Comparator 250 kHz Oscillator Q 8 VCC IMAX VCC − 2 V Reference Toggle PMPB R2 + Q 200 mV + CP1 − 5 + Overcurrent Comparator − To Linear Amplifier 7 + VCC VCC 2 C2 − Undervoltage Lockout 4.0 V/ 3.8 V CPUMP 103 µA 3 mA To VOUT SD VFAULT = 50 mV VCC 50 mV VPUMP 4 SENSE H = Close FAULT 10 To Linear Amplifier 2.5 V Fault Latch − Q S + Q R 17 H = Close OUT + − RSENSE 11 15 V RFAULT Fault Timing Circuitry To VCC GND VOUTS − 12 0.5 V + 3 µA PLIM 1.4 V − RPL 14 + 1 13 15 LR CT CT To VOUT UDG−98194 Figure 1. Typical Application The term hot swap refers to the system requirement that submodules be swapped in or out upon failure or system modification without removing power to the operating hardware. The integrity of the power bus must not be compromised due to the addition of an unpowered module. Significant power bus glitches can occur due to the substantial initial charging current of on-board module bypass capacitance and other load conditions (for more information on hot swapping and power management applications, see SLUA157). The UC3914 provides protection by monitoring and controlling the output current of an external N-channel MOSFET to charge this capacitance and provide load current. The addition of the N-channel MOSFET, a sense resistor, RSENSE, and two other resistors, R1 and R2, sets the programmed maximum current level the N-channel MOSFET can source to charge the load in a controlled manner. The equation for this current, IMAX, is: I MAX + V VCC * V IMAX R SENSE (4) where D VIMAX is the voltage generated at the IMAX pin www.ti.com 7 PRODUCT PREVIEW VPUMP VOUT + 10 V (45 VMAX) + OSCB 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION Analysis of the application circuit shows that VIMAX (with respect to GND) can be defined as: V IMAX + V REF ) ǒVCC * VREFǓ R1 R1 ) R2 + 2V R1 ) V REF R1 ) R2 (5) where D VREF is the voltage on the REF pin, an internally generated potential 2-V below VCC The UC3914 also has an internal overcurrent comparator which monitors the voltage between SENSE and VCC. If this voltage exceeds 50 mV, the comparator determines that a fault has occurred, and a timing capacitor, CT, begins to charge. This can be rewritten as a current which causes a fault, IFAULT: I FAULT + 50 mV R SENSE (6) FAULT TIMING To VCC Overload Comparator RPL PLIM 14 VCC I3 VCC IPL I1 103 µA SENSE + + 2 S1 + S2 2.5 V RSENSE H=CLOSE SENSE IMAX 0.2 V 3 mA 50 mV VCC + PRODUCT PREVIEW Figure 2 shows the circuitry associated with the fault timing function of the UC3914. A typical fault mode, where the overload comparator and current source I3 do not factor into operation (switch S2 is open), is first considered. Once the voltage across RSENSE exceeds 50 mV, a fault has occurred. This causes the timing capacitor, CT, to charge with a combination of 100 µA (I1) plus the current from the power limiting circuitry (IPL). H=CLOSE Fault Comparator FAULT LATCH + S Q R Q 17 I2 3 µA + Reset Comparator VOUTS To Output 0.5 V To Output Drive H=OFF 12 15 To LOAD CT CT UDG−03158 Figure 2. Fault Timing Circuitry Including Power Limit and Overcurrent 8 www.ti.com 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION UDG−97054 Figure 3. Typical Timing Diagram Table 1. Fault Timing Conditions TIME CONDITION t0 Normal conditions. Output current is nominal, output voltage is at positive rail, VCC t1 Fault control reached. Output current rises above the programmed fault value, CT begins to charge at 100-µA + IPL. t2 Maximum current reached. Output current reaches the programmed maximum level and becomes a constant current with value IMAX. t3 Fault occurs. CT has charged to 2.5 V, fault output goes low, the FET turns off allowing no output current to flow, VVOUTS discharges to GND. t4 Retry. CT has discharged to 0.5 V, but fault current is still exceeded, CT begins charging again, FET is on, VOUT increases. t5 = t3 Illustrates < 3% duty cycle depending upon RPL selected. t6=t4 t7=t0 Fault released, normal condition. Return to normal operation of the load. www.ti.com 9 PRODUCT PREVIEW Figure 3 shows typical fault timing waveforms for the external N-channel MOSFET output current, the voltage on the CT pin, and the output load voltage, VOUT, with LR left floating or grounded. 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION The output voltage waveforms have assumed an R-C characteristic load and time constants vary depending upon the component values. Prior to time t0, the load is fully charged to almost VVCC and the N-channel MOSFET is supplying the current, IOUT, to the load. At t0, the current begins to ramp up due to a change in the load conditions until, at t1, the fault current level, IFAULT, has been reached to cause switch S1 to close. This results in CT being charged with the current sources I1 and IPL. During this time, VOUT remains almost equal to VVCC except for small losses from voltage drops across the sense resistor and the N-channel MOSFET. The output current reaches the programmed maximum level, IMAX, at t2. The CT voltage continues to rise since IMAX is still greater than IFAULT. The load output voltage drops because the current load requirements have become greater than the controlled maximum sourcing current. The CT voltage reaches the upper comparator threshold (Figure 2) of 2.5 V at t3, which promptly shuts off the gate drive to the N-channel MOSFET (not shown but can be inferred from the fact that no output current is provided to the load), latches in the fault and opens switch S1 disconnecting the charging currents I1 and IPL from CT. PRODUCT PREVIEW Since no output current is supplied, the load voltage decays at a rate determined by the load characteristics and the capacitance. The 3-µA current source, I2, discharges CT to the 0.5-V reset comparator threshold. This time is significantly longer than the charging time and is the basis for the duty cycle current limiting technique. When the CT voltage reaches 0.5 V at t4, the part performs a retry, allowing the N-channel MOSFET to again source current to the load and cause VOUT to rise. In this particular example, IMAX is still sourced by the N-channel MOSFET at each attempted retry and the fault timing sequence is repeated until time t7 when the load requirements change to IOUT. Since IOUT is less than the fault current level at this time, switch S1 is opened, I2 discharges CT and VOUT rises almost to the level of VCC. Figure 4 shows fault timing waveforms similar to those depicted in Figure 3 except that the latch reset (LR) function is utilized. Operation is the same as described above until t4 when the voltage on CT reaches the reset threshold. Holding LR high prevents the latch from being reset, preventing the device from performing a retry (sourcing current to the load). The UC3914 is latched off until either LR is pulled to a logic low, or the chip is forced into an under voltage lockout (UVLO) condition and back out of UVLO causing the latch to automatically perform a power on reset. Figure 4 illustrates LR being toggled low at t5, causing the part to perform a retry. Time t6 again illustrates what happens when a fault is detected. The LR pin is toggled low and back high at time t7, prior to the voltage on the CT pin hitting the reset threshold. This information tells the UC3914 to allow the part to perform a retry when the lower reset threshold is reached, which occurs at t8. Time t9 corresponds to when load conditions change to where a fault is not present as described for Figure 3. 10 www.ti.com 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 UDG−97055 Figure 4. Typical Timing Diagram Using Latch Reset (LR) Function Table 2. Fault Timing Conditions with Latch Reset Function TIME CONDITION t0 Normal conditions. Output current is nominal, output voltage is at positive rail, VCC t1 Fault control reached. Output current rises above the programmed fault value, CT begins to charge at 100-µA + IPL. t2 Maximum current reached. Output current reaches the programmed maximum level and becomes a constant current with value IMAX. t3 Fault occurs. CT has charged to 2.5 V, fault output goes low, the FET turns off allowing no output current to flow, VVOUTS discharges to GND. t4 Reset comparator threshold reached but no retry since LR pin held high. t5 LR toggled low, N-channel MOSFET turned on and sources current to load. t6=t3 t7 LR toggled low before VCT reaches reset comparator threshold, causing retry. t8 Since LR toggled low during present cycle, N-channel MOSFET turned on and sources current to load. t9=t0 Fault released, normal condition. Return to normal operation of the load. www.ti.com 11 PRODUCT PREVIEW APPLICATION INFORMATION 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION Power Limiting The power limiting circuitry is designed to only source current into the CT pin. To implement this feature, a resistor, RPL, should be placed between VCC and PLIM. The current, IPL (show in Figure 2) is given by the following expression: I PL + V VCC * V VOUTS , for V VOUTS u 1 V ) V CT R PL (7) where D VCT is the voltage on the CT pin For VVOUTS < 1 V + VCT the common mode range of the power limiting circuitry causes IPL = 0 A leaving only the 100-µA current source to charge CT. VVCC − VVOUTS represents the voltage across the N-channel MOSFET pass device. PRODUCT PREVIEW This feature limits average power dissipation in the pass device. Note that under a fault condition where the output current is just above the fault level, but less than the maximum level, VVOUTS ~ VVCC, IPL = 0 A and the CT charging current is 100 µA. During a fault, the CT pin charges at a rate determined by the internal charging current and the external timing capacitor, CT. Once CT charges to 2.5 V, the fault comparator trips and sets the fault latch. When this occurs, OUT is pulled down to VOUTS, causing the external N-channel MOSFET to shut off and the charging switch, S1, to open. CT is discharged with I2 until the VCT potential reaches 0.5 V. Once this occurs, the fault latch resets (unless LR is being held high, whereby a fault can only be cleared by pulling this pin low or going through a power-on-reset cycle), which re-enables the output of the linear amplifier and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the overcurrent comparator closes the charging switch causing the cycle to repeat. Under a constant fault the duty cycle is given by: Duty Cycle + 3 mA I PL ) 100 mA (8) Average power dissipation can be limited using the PLIM pin. Average power dissipation in the pass element is given by: P FET(avg) + ǒV VCC * V VOUTSǓ + ǒV VCC * V VOUTSǓ I MAX I MAX Duty Cycle (9) 3 mA I PL ) 100 mA VVCC − VVOUTS is the drain to source voltage across the MOSFET. When IPL >> 100 µA, the duty cycle equation given above can be rewritten as: Duty Cycle + R PL 3 mA ǒVVCC * VVOUTSǓ (10) and the average power dissipation of the MOSFET is given by: P FET(avg) + ǒV VCC * V VOUTSǓ I MAX R PL 3 mA ǒVVCC * VVOUTSǓ + I MAX R PL 3 mA The average power is limited by the programmed IMAX current and the appropriate value for RPL. 12 www.ti.com (11) 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION OVERLOAD COMPARATOR The linear amplifier in the UC3914 ensures that the external N-channel MOSFET does not source more than the current IMAX, defined in equation (4): V VCC * V IMAX R SENSE In the event that output current exceeds the programmed IMAX current by more than 200-mV/RSENSE, the output of the linear amplifier is immediately pulled low (with respect to VOUTS) providing no gate drive to the N-channel MOSFET, and preventing current from being delivered to the load. This situation could occur if the external N-channel MOSFET is not responding to a command from the UC3914 or output load conditions change quickly to cause an overload condition before the linear amplifier can respond. For example, if the N-channel MOSFET is sourcing current into a load and the load suddenly becomes short circuited, an overload condition may occur. The short circuit causes the VGS of the N-channel MOSFET to immediately increase, resulting in increased load current and voltage drop across RSENSE. If this drop exceeds the overload comparator threshold, the amplifier output is quickly pulled low. It also causes the CT pin to begin charging with I3, a 3-mA current source (refer to Figure 2) and continue to charge until approximately 1-V below VVCC, where it is clamped. This allows a constant fault to show up on FAULT and since the voltage on CT charges past 2.5 V only in an overload fault condition, it can be used for detection of output N-channel MOSFET failure or to build redundancy into the system. ESTIMATING MINIMUM TIMING CAPACITANCE The startup time of the device may not exceed the fault time for the application. Since the timing capacitor, CT, determines the fault time, its minimum value can be determined by calculating the startup time of the device. The startup time is dependent upon several external components. A load capacitor, CLOAD, should be tied between VOUTS and GND. Its value should be greater than that of CPUMP, the reservoir capacitor tied from VPUMP to VOUTS (see Figure 4). Given values of CLOAD, RLOAD, RSENSE, VVCC and the resistors determining the voltage on IMAX, the user can calculate the approximate startup time of the node VOUT. This time must be less than the time it takes for CT to charge to 2.5 V. Assuming the user has determined the fault current, RSENSE can be calculated by: R SENSE + 50 mV I FAULT (12) IMAX is the maximum current the UC3914 allows through the transistor, M1. During startup with an output capacitor, M1 can be modeled as a constant current source of value IMAX using equation (4). Given this information, calculation of startup time is now possible via the following: Using a constant-current load model, use this equation: T START + ǒCLOAD VVCCǓ ǒI MAX * I LOADǓ (13) Using a resistive load model, use this equation: T START + * R LOAD C LOAD ǒ ȏn 1 * V VCC I MAX R LOAD www.ti.com Ǔ (14) 13 PRODUCT PREVIEW I MAX + 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION The only remaining external component which may affect the minimum timing capacitor is the optional power limiting resistor, RPL. If the addition of RPL is desirable, its value can be determined from the Power Limiting section of this datasheet. The minimum timing capacitor values are now given by the following equations. Using a constant-current load model, use this equation: CT min + T START ȡ10*4 ȧ ȧ ȧ Ȣ R PL ) 2 ǒ Ǔȣȧ V VCC 2 R PL ȧ ȧ Ȥ (15) Using a resistive load model, use this equation: PRODUCT PREVIEW CT (min) + ǒ10*4 R PL ) V VCC * ǒI MAX 2 R LOADǓ Ǔ R PL T START ) V VCC 2 R PL R LOAD C LOAD (16) OUTPUT CURRENT SOFTSTART The external MOSFET output current can be increased at a user-defined rate to ensure that the output voltage comes up in a controlled fashion by adding capacitor CSS, as shown in Figure 5. The one constraint that the UC3914 places on the soft-start time is that the charge pump time constant must be much less than the soft-start time constant to ensure proper soft-start operation. The time constant determining the startup time of the charge pump is given by: t CP + R OUT C PUMP (17) ROUT is the output impedance of the charge pump given by: R OUT + 1 f PUMP CP (18) where fPUMP is the charge pump frequency (125 kHz) and CP = CP1 = CP2 are the charge pump flying capacitors. For typical values of CP1, CP2 and CPUMP (0.01-µF) and a switching frequency of 125 kHz, the output impedance is 800 Ω and the charge pump time constant is 8 µs. The charge pump should be close to being fully charged in 3 time constants or 24 µs. By placing a capacitor from VCC to IMAX, the voltage at IMAX, which sets the maximum output current of the MOSFET, exponentially decays from VCC to the desired value set by R1 and R2. The output current of the MOSFET is controlled via soft-start as long as the soft-start time constant (τSS) is much greater than the charge pump time constant τCP, given by: t SS + ǒR1 ø R2Ǔ 14 C SS (19) www.ti.com 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION MINIMIZING TOTAL DROPOUT UNDER LOW VOLTAGE OPERATION In a typical application, the UC3914 is used to control the output current of an external N-channel MOSFET during hot swapping situations. Once the load has been fully charged, the desired output voltage on the load, VOUT, needs to be as close to VCC as possible to minimize total dropout. For a resistive load, RLOAD, the output voltage is given by: R LOAD R LOAD ) R SENSE ) R DS(on) V VCC (20) RSENSE sets the fault current, IFAULT. RDS(on), the on-resistance of the N-channel MOSFET, should be made as small as possible to ensure VOUT is as close to VCC as possible. For a given N-channel MOSFET, the manufacturer specifies the RDS(on) for a certain VGS (i. e., between 7 V to 10 V). The source potential of the N-channel MOSFET is VOUT. In order to ensure sufficient VGS, this requires the gate of the N-channel MOSFET, which is the output of the linear amplifier, to be many volts higher than VVCC. The UC3914 provides the capability to generate this voltage through the addition of three capacitors, CP1, CP2 and CPUMP as shown in Figure 6. These capacitors should be used in conjunction with the complementary output drivers and internal diodes included on-chip to create a charge pump or voltage tripler. The circuit boosts VVCC by utilizing capacitors CP1, CP2 and CPUMP in such a way that the voltage at VPUMP approximately equals three times the voltage at VCC minus five times the voltage drop of the diodes, almost tripling the input supply voltage to the device. V VPUMP + ǒ3 V VCCǓ * ǒ5 V DIODEǓ (21) On each complete cycle, CP1 is charged to approximately (VVCC − VDIODE) (unless VCC is greater than 15 V causing internal clamping to limit this charging voltage to about 13 V) when the output Q of the toggle flip-flop is low. When Q is transitioned low (and Q correspondingly is brought high), the negative side of CP2 is pulled to ground, and CP1 charges CP2 up to approximately: V CP2 + ǒ2 V VCCǓ * ǒ3 V DIODEǓ (22) CP1 + C1 To VCC PMP CSS OSC VCC 9 2 6 D1 R1 18 REF R2 16 IMAX PMPB 2 VCC M1 6 OSC OUT 11 9 8 CP2 PMP VOUT OSCB PMPB D3 5 TOGGLE FLIP FLOP Q QT VOUTS 12 CPUMP 5 + CP2 OSCB UC2914 CP1 D3 8 VPUMP L O A D 7 250 kHz OSC 7 + CLOAD VPUMP CVPUMP UDG−03178 To VOUT Figure 5. MOSFET Softstart Diagram Figure 6. Charge Pump Block Diagram www.ti.com 15 PRODUCT PREVIEW V OUT + 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION When Q is toggled high, the negative side of CP2 is brought to (VCC − VDIODE). Since the voltage across a capacitor cannot change instantaneously with time, the positive side of the capacitor swings up to: V PMPB + 3 V CC * 4 V DIODE (23) This charges CPUMP up to: V CPUMP + 3 V CC * 5 V DIODE (24) The maximum output voltage of the linear amplifier is actually less than this because of the ability of the amplifier to swing to within approximately 1 V of VPUMP. Due to inefficiencies of the charge pump, the UC3914 may not have sufficient gate drive to fully enhance a standard power MOSFET when operating at input voltages below 7 V. Logic level MOSFETs could be used depending on the application but are limited by their lower current capability. For applications requiring operation below 7 V, there are two ways to increase the charge pump output voltage. Figure 7 shows the typical tripler of Figure 6 enhanced with three external schottky diodes. Placing the schottky diodes in parallel with the internal charge pump diodes decreases the voltage drop across each diode thereby increasing the overall efficiency and output voltage of the charge pump. PRODUCT PREVIEW Figure 8 shows a way to use the existing drivers with external diodes (or Schottky diodes for even higher pump voltages but with additional cost) and capacitors to make a voltage quadrupler. The additional charge pump stage provides a sufficient pump voltage to generate the maximum VGS: V VPUMP + 4 V CC * 7 V DIODE (25) CP2 CP1 CP1 D2 PMP 9 VCC 2 OSC 6 D3 D1 D2 PMPB 8 D3 CP2 OSCB 5 CP3 D1 OSCB VCC 5 Toggle Flip−Flop Q 8 Q D4 250 kHz Oscillator 9 PMP 7 7 VPUMP CPUMP CPUMP QT 250 kHz Oscillator To VOUT To VOUT Figure 8. Low Voltage Operation to Produce Higher Pump Voltage Figure 7. Enhanced Charge Pump 16 6 PMPB Toggle Flip−Flop QT VPUMP 2 OSC www.ti.com 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION Operation is similar to the case described above. This additional circuitry is not necessary for higher input voltages because the UC3914 has internal clamping which only allows VPUMP to be 10 V greater than VVOUTS. Table 3 characterizes the UCx914 charge pump in its standard configuration, with external schottky diodes, and configured as a voltage quadrupler. NOTE: The voltage quadrupler is unnecessary for input voltages above 7.0 V due to the internal clamping action. INPUT VOLTAGE (VCC) INTERNAL DIODES (VGS) EXTERNAL SCHOTTKY DIODES (VGS) QUADRUPLER (VGS) 4.5 4.57 6.8 8.7 5.0 5.80 7.9 8.8 5.5 6.60 8.6 8.9 6.0 7.60 8.8 9.0 6.5 8.70 8.8 9.0 7.0 8.80 9.0 9.0 9.0 9.20 9.4 9.1 10.0 9.30 9.4 9.3 ICC SPECIFICATIONS The ICC operating measurement is actually a mathematical calculation. The charge pump voltage is constantly being monitored with respect to both VCC and VOUTS to determine whether the pump requires servicing. If there is insufficient voltage on this pin, the charge pump drivers are alternately switched to raise the voltage of the pump (see Figure 9). Once the voltage on the pump is high enough, the drivers and other charge pump related circuitry are shutdown to conserve current. The pump voltage decays due to internal loading until it reaches a low enough level to turn the drivers back on. The chip requires significantly different amounts of current during these two modes of operation and the following mathematical calculation is used to calculate the average current: I CC + I CCdrivers(on) T ON ) I CCdrivers(off) T OFF T ON ) T OFF (26) Since the charge pump does not always require servicing, the user may think that the charge pump frequency is much less than the datasheet specification. This is not the case as the free-running frequency is guaranteed to be within the datasheet limits. The charge pump servicing frequency can make it appear as though the drivers are operating at a much lower frequency www.ti.com 17 PRODUCT PREVIEW Table 3. Charge Pump Characteristics 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 APPLICATION INFORMATION Pump Upper Level PUMP Pump Lower Level Oscillator Frequency Pump Servicing Frequency PRODUCT PREVIEW OSC OSCB TON TIME TOFF Figure 9. Charge Pump Waveforms 18 www.ti.com UDG−98144 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 TYPICAL CHARACTERISTICS LINEAR AMPLIFIER OFFSET VOLTAGE vs JUNCTION TEMPERATURE 3.5 −48.0 −48.5 2.5 2.0 1.5 1.0 0.5 −49.0 −49.5 −50.0 −50.5 −51.0 −51.5 −52.0 −25 5 35 65 95 125 −55 −25 2.040 VREF − Reference Voltage − V ICHG(CT) − Timing Capacitor Charge Current − µA TIMING CAPACITOR CHARGE CURRENT vs JUNCTION TEMPERATURE −96 −100 −104 −108 −112 −55 −25 5 35 35 65 95 125 Figure 11 Figure 10 −92 5 TJ − Junction Temperature − °C TJ − Junction Temperature − °C 65 95 125 TJ − Junction Temperature − °C REFERENCE VOLTAGE vs JUNCTION TEMPERATURE 2.035 2.030 2.025 2.020 2.015 −55 −25 5 35 65 95 125 TJ − Junction Temperature − °C Figure 12 Figure 13 www.ti.com 19 PRODUCT PREVIEW VFAULT − Fault Threshold − mV VIO − Input Offset Voltage − mV 3.0 0 −55 FAULT THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 

  SLUS425C − DECEMBER 2003 − REVISED JULY 2004 TYPICAL CHARACTERISTICS IDSHG(CT) − Timing Capacitor Discharge Current − µA INPUT BIAS CURRENT vs JUNCTION TEMPERATURE 2.0 PRODUCT PREVIEW IBIAS − Bias Current − µA SENSE Input Bias 1.5 1.0 0.5 IMAX Input Bias 0 −55 −25 5 35 65 95 125 TJ − Junction Temperature − °C 3.7 TIMING CAPACITOR DISCHARGE CURRENT vs JUNCTION TEMPERATURE 3.6 3.5 3.4 3.3 −55 −25 5 35 65 95 125 TJ − Junction Temperature − °C Figure 15 Figure 14 SAFETY RECOMMENDATIONS Although the UC3914 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. For this reason, if the UC3914 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the device. The UC3914 prevents the fuse from blowing in virtually all fault conditions, increasing system reliability and reducing maintainence cost, in addition to providing the hot swap benefits of the device. 20 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UC2914DW ACTIVE SOIC DW 18 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2914DW UC2914DWTR ACTIVE SOIC DW 18 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2914DW UC3914DW ACTIVE SOIC DW 18 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3914DW UC3914DWTR ACTIVE SOIC DW 18 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3914DW UC3914DWTRG4 ACTIVE SOIC DW 18 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3914DW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of