UCC12050
UCC12050
SNVSB38D – SEPTEMBER 2019 – REVISED JANUARY
2021
SNVSB38D – SEPTEMBER 2019 – REVISED JANUARY 2021
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UCC12050 High-Density, Low-EMI, 5-kVRMS Reinforced Isolation DC/DC Module
1 Features
2 Applications and Uses
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High-density DC/DC module with optimized
integrated transformer technology
Input voltage range: 4.5 V to 5.5 V
Output voltages (selectable): 5.4 V, 5.0 V, 3.7 V,
3.3 V
Output power: 500 mW
Peak efficiency: 60%
Line regulation (typical): 1%
Load regulation (typical): 1.5%
Meets CISPR32 Class B EMI limits without ferrite
beads on a 2-layer PCB
Spread spectrum modulation (SSM)
Robust isolation barrier:
– Isolation rating: 5 kVRMS
– Surge capability: 10 kVPK
– Working voltage: 1.2 kVRMS
– CMTI (typical): ±100 V/ns
Short circuit recovery
Thermal shutdown
16-pin wide-body SOIC package with > 8-mm
creepage and clearance
Extended temperature range: –40°C to 125°C
Safety-related certifications:
– 7071-VPK reinforced isolation per DIN V VDE V
0884-11:2017-01
– 5000-VRMS isolation for 1 minute per UL 1577
– UL certification per IEC 60950-1, IEC 62368-1
and IEC 60601-1 end equipment standards
– CQC approval per GB4943.1-2011
On-board charger
Battery management system
Traction inverter
DC/DC converter for HEV/EVs
3 Description
UCC12050 is an automotive qualified DC/DC power
module with 5-kVRMS reinforced isolation rating
designed to provide efficient, isolated power to
isolated circuits that require a bias supply with a
well-regulated output voltage. The device integrates
a transformer and DC/DC controller with a proprietary
architecture to provide 500 mW (typical) of isolated
power with low EMI.
The UCC12050 integrates protection features for
increased system robustness. The device also has an
enable pin, synchronization capability, and regulated
5-V or 3.3-V output options with headroom. The
UCC12050 is a low-profile, miniaturized solution
offered in a wide-body SOIC package with 2.65-mm
height (typical).
Device Information(1)
PART NUMBER
UCC12050
(1)
PACKAGE
DVE SOIC (16)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
70
GNDP
SYNC
SYNC_OK
60
VISO
Isolation Barrier
OFF
EN
COUT
50
GNDS
SEL
Simplified Application
Efficiency (%)
VINP
ON
CIN
40
30
20
VISO = 5.4 V
VISO = 5.0 V
VISO = 3.7 V
VISO = 3.3 V
10
0
0
20
VINP = 5.0 V
40
60
80
100
Load Current (mA)
120
140
D021
TA = 25°C
Typical Efficiency vs. Load
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications and Uses.................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 5
6.7 Safety-Related Certifications...................................... 6
6.8 Safety Limiting Values.................................................6
6.9 Electrical Characteristics.............................................7
6.10 Switching Characteristics..........................................8
6.11 Insulation Characteristics Curves..............................9
6.12 Typical Characteristics............................................ 10
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagram......................................... 15
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................17
8 Application and Implementation.................................. 18
8.1 Application Information............................................. 18
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................24
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Example...................................................... 25
11 Device and Documentation Support..........................26
11.1 Device Support........................................................26
11.2 Documentation Support.......................................... 26
11.3 Receiving Notification of Documentation Updates.. 26
11.4 Support Resources................................................. 26
11.5 Trademarks............................................................. 26
11.6 Electrostatic Discharge Caution.............................. 26
11.7 Glossary.................................................................. 26
12 Mechanical and Packaging Information.................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2020) to Revision D (February 2021)
Page
• Added updates to the text throughout the document. ........................................................................................1
• Updated ESD values. ........................................................................................................................................ 4
• Updated thermal footnote description.................................................................................................................4
• Updated voltage isolation specs per DIN V VDE V 0884-11:2017-01................................................................ 5
• Added certification numbers............................................................................................................................... 6
• Updated Switching Characteristics (non-sync)................................................................................................... 8
• Added Section number included ......................................................................................................................17
Changes from Revision B (December 2019) to Revision C (April 2020)
Page
• Added updates to the text throughout the document. ........................................................................................1
• Added footnote to Insulation Speficications table............................................................................................... 5
• Removed Pout_max as a Loading parameter. Removed Pout_max from graph............................................. 16
Changes from Revision A (September 2019) to Revision B (December 2019)
Page
• Changed marketing status from Advance Information to Initial Release............................................................ 1
2
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5 Pin Configuration and Functions
DVE Package 16-Pin SOIC Top View
1
16
GNDS
GNDP
2
15
GNDS
VINP
3
14
VISO
SYNC
4
13
SEL
SYNC_OK
5
12
NC
NC
6
11
NC
NC
7
10
NC
NC
8
9
EN
GNDS
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
EN
1
I
Enable pin. Forcing EN low disables the device. Pull high to enable normal device
functionality.
GNDP
2
P
Power ground return connection for VINP.
P
Connect to GNDS plane on printed circuit board. Do not use as only ground connection for
VISO. Ensure pin 15 is connected to circuit ground.
P
Secondary side ground return connection for VISO. Connect bypass capacitor from VISO to
this pin.
—
Pins internally connected together. No other electrical connection. Pins belong to primaryside voltage domain. Connect to GNDP on printed circuit board.
—
No internal connection. Pin belongs to isolated voltage domain. Connect to GNDS on printed
circuit board.
I
Synchronous clock input pin. Provide a clock signal to synchronize multiple devices or
connect to GNDP for standalone operation using the internal oscillator. If the SYNC pin is left
open make sure to it separate it from any switching noise to avoid false clock coupling.
O
Active-low, open-drain diagnostic output. Pin is asserted LOW if there is no external SYNC
clock or one that is outside of the operating range is detected. In this state, the external
clock is ignored and the DC/DC converter is clocked by the internal oscillator. The pin is in
high-impedance if a clock is applied on SYNC.
GNDS
GNDS
9
16
15
6
7
8
NC
10
11
12
SYNC
SYNC_OK
4
5
SEL
13
I
VISO selection pin. VISO setpoint is 5.0 V when SEL is shorted to VISO, 5.4 V when SEL is
connected to VISOthrough a 100-kΩ resistor, 3.3 V when SEL is shorted to GNDS, and 3.7
V when SEL is connected to GNDS through a 100-kΩ resistor. For more information see the
Section 7.4 section.
VINP
3
P
Primary side input supply voltage pin. A 10-μF ceramic capacitor to GNDP on pin 2, placed
close to the device pins, is required.
VISO
14
P
Isolated supply voltage pin. A 10-μF ceramic capacitor to GNDS on pin 15, placed close to
the device pins, is required. See Section 8.2.2.1 section.
(1)
P = Power, G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VINP to GNDP
MAX
UNIT
–0.3
6.0
V
EN, SYNC, SYNC_OK, to GNDP
–0.3
VINP + 0.3,
≤ 6.0
V
VISO to GNDS
–0.3
6.0
V
–0.3
VISO + 0.3,
≤ 6.0
V
Operating junction temperature range, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
SEL to GNDS
VISO output power at Ta = 25°C, POUT_MAX
(1)
(2)
(2)
675
mW
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
See the Section 7.3.3 section for maximum rated values across temperature and VINP conditions for each different VISO output mode.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
4.5
5.0
5.5
UNIT
VINP
Primary side supply voltage
VEN
EN pin input voltage
0
5.5
V
V
VSYNC
SYNC pin input voltage
0
5.5
V
VSYNC-OK
SYNC_OK pen drain pin voltage
0
5.5
V
VISO
Isolated power supply voltage
0
5.7
V
VSEL
Input voltage
fSYNC
External DC/DC converter synchronization signal frequency
PVISO
VISO output power at Ta = 25°C (1)
Ta
Ambient temperature
–40
TJ
Junction temperature
–40
(1)
0
14.4
16.0
5.7
V
17.6
MHz
500
mW
125
°C
150
°C
See the Section 7.3.3 section for maximum rated values across temperature and VINP conditions for each different VISO output mode.
6.4 Thermal Information
UCC12050
THERMAL METRIC(1)
DVE (SOIC)
UNIT
16 PINS
4
RθJA
Junction-to-ambient thermal resistance
63.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
21.4
°C/W
RθJB
Junction-to-board thermal resistance
38.5
°C/W
ψJT
Junction-to-top characterization parameter
10.2
°C/W
ψJB
Junction-to-board characterization parameter
37.2
°C/W
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UCC12050
THERMAL METRIC(1)
DVE (SOIC)
UNIT
16 PINS
RθJC(bot)
(1)
Junction-to-case (bottom) thermal resistance
—
°C/W
The value of R θJA given in this table is only valid for comparison with other packages and can not be used for design purposes. This
value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board when PDP = 129 mW, PDS = 142 mW
and PDT = 129 mW. The board temperature is taken from Pin 12. For more information about traditional and new thermal metrics, see
the Semiconductor and IC Package Thermal Metrics application report.
6.5 Power Ratings
VINP = 5.0V, CINP = COUT = 10 uF, TJ = 150°C, Internal Clock mode
PARAMETER
TEST CONDITIONS
VALUE
UNIT
PD
Power dissipation
460
mW
PDP
Power dissipation by driver side (primary)
148
mW
PDS
Power dissipation by rectifier side (secondary)
PDT
Power dissipation by transformer
SEL connected to GNDS (3.3-V VISO output mode), IISO =
135 mA
164
mW
148
mW
VALUE
UNIT
Shortest terminal-to-terminal distance through air
>8
mm
Shortest terminal-to-terminal distance across the package
surface
>8
mm
6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
GENERAL
CLR
External clearance(1)
CPG
External
creepage(1)
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
> 120
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
According to IEC 60664-1
Overvoltage Category
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN V VDE V 0884-11:2017-01(2)
VIORM
VIOWM
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1697
VPK
Maximum working isolation voltage
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test
1200
VRMS
DC voltage
1697
VDC
7071
VPK
6250
VPK
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM, t = 60s (qualification);
VTEST = 1.2 × VIOTM, t = 1s (100% production)
VIOSM
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)
qpd
CIO
RIO
Apparent charge(4)
Barrier capacitance, input to output(5)
Isolation resistance, input to output(5)
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1696 VPK, tm = 10 s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 2262 VPK, tm = 10 s
≤5
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 2651 VPK, tm = 1 s
≤5
VIO = 0.4 sin (2πft), f = 1 MHz
~3.5
VIO = 500 V, TA = 25°C
> 1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS = 150°C
>
pC
pF
Ω
109
Pollution degree
2
Climatic category
40/125/21
UL 1577
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PARAMETER
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
TEST CONDITIONS
VALUE
UNIT
VTEST = VISO = 5000 VRMS, t = 60 s (qualification); VTEST =
1.2 × VISO = 6000 VRMS, t = 1 s (100% production)
5000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device
6.7 Safety-Related Certifications
VDE
UL
CQC
Recognized under UL
Certified according to DIN V
VDE V 0884-11:2017- 01
Certified according to IEC
60601-1
Certified according to IEC
60950-1 and IEC 62368- 1
Reinforced insulation
Maximum transient isolation
voltage, 7071 VPK;
Maximum repetitive peak
isolation voltage, 1697 VPK;
Maximum surge isolation
voltage, 6250 VPK
Reinforced insulation per
AAMI ES 60601-1:2005/
(R)2012 and A1:2012,
C1:2009/(R)2012 and
A2:2010/(R)2012 CSA
C22.2 No. 60601-1:2014
IEC 60601-1:2012, 2
MOPP (Means of Patient
Protection), 250 VRMS
maximum working voltage
Reinforced insulation per
UL 60950-1-07+A1+A2, IEC
60950-1 2nd Ed.+A1+A2,
UL 62368-1- 14 and IEC
Single protection, 5000 VRMS
62368-1 2nd Ed., 1200
VRMS maximum working
voltage (pollution degree 1,
material group I
Reinforced insulation, Altitude ≤
5000 m, Tropical Climate, 700
VRMS maximum working voltage
Certificate number:
40040142
Certificate number:
US-36773-A1-UL
Certificate number:
File number: E181974
US-36706-UL, US-36707-UL
Certificate number:
CQC20001273822
1577 Component Recognition
Program
Certified according to
GB4943.1-2011
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
IS
Safety input current (1)
PS
Safety input power
TS
Safety temperature (1)
(1)
TEST CONDITIONS
MAX
RθJA = 63.8°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
356
RθJA = 63.8°C/W, VI = 4.5 V, TJ = 150°C, TA = 25°C
435
RθJA = 63.8°C/W, TJ = 150°C, TA = 25°C
UNIT
mA
1960
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the Thermal Information
table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value
for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is
the maximum allowed junction temperature. PS = IS × VI, where VI is the maximum input voltage.
6
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6.9 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 150°C), VINP = 4.5V to 5.5V, CINP = COUT = 10 µF, SEL connected to VISO,
internal clock mode, unless otherwise noted. All typical values at TJ = 25°C and VINP = 5.0V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
uA
INPUT SUPPLY
IVINQ
VINP quiescent current,disabled
EN=LOW
IVINO
VINP operating current, no load
IVIN_SC
DC current from VINP supplyunder
short circuit on VISO
VUVPR
EN=HI; SEL shorted to VISO (5.0V output)
50
EN=HI; SEL 100kΩ to VISO (5.4V output)
45
EN=HI; SEL shorted to GNDS (3.3V output)
90
EN=HI; SEL 100kΩ to GNDS (3.7V output)
80
VISO short to GNDS
mA
245
mA
VINP under-voltage lockout rising
threshold
4.2
V
VUVPF
VINP under-voltage lockout falling
threshold
3.7
V
VUVPH
VINP under-voltage lockout
hysteresis
0.5
V
EN, SYNC INPUT PINS
VIR
Input voltage threshold, logic HIGH
Rising edge
2.2
V
5
10
uA
1
uA
1
uA
VIF
Input voltage threshold, logic LOW
Falling edge
IEN
Enable Pin Input Current
VEN = 5.0 V
0.8
V
ISYNC
SYNC Pin Input Current
VSYNC = 5.0 V
0.02
0.15
SYNC_OK PIN
VOL
SYNC_OK output low voltage
ISYNC_OK = - 2 mA
ILKG_SYNC_OK
SYNC_OK pin leakage current
VSYNC_OK = 5.0 V
V
DC/DC CONVERTER
VISO
VISO(RIP)
VISO(LINE)
Isolated supply output voltage
Voltage ripple on isolated supply
output (pk-pk)
VISO DC line regulation
SEL shorted to VISO (5.0V output); IISO = 55
mA (2)
4.7
5
5.3
V
SEL 100kΩ to VISO (5.4 V output); IISO = 45
mA (2)
5.1
5.4
5.7
V
SEL shorted to GNDS (3.3V output); IISO =
100 mA (2)
3.1
3.3
3.5
V
SEL 100kΩ to GNDS (3.7 V output); IISO = 90
mA (2)
3.5
3.7
3.9
V
20-MHz bandwidth, CLOAD = 10 uF || 0.1
uF, SEL shorted to VISO (5.0V output); IISO =
100 mA
50
mV
20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF,
SEL 100kΩ to VISO (5.4V output); IISO = 90
mA
50
mV
20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF,
SEL shorted to GNDS (3.3V output); IISO =
145 mA
50
mV
20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF,
SEL shorted to GNDS (3.7V output); IISO =
130 mA
50
mV
SEL shorted to VISO (5.0 V output); IISO = 50
mA, VINP = 4.5 V to 5.5 V
1%
SEL shorted to GNDS (3.3 V output); IISO =
75 mA, VINP = 4.5 V to 5.5 V
1%
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Over operating temperature range (TJ = –40°C to 150°C), VINP = 4.5V to 5.5V, CINP = COUT = 10 µF, SEL connected to VISO,
internal clock mode, unless otherwise noted. All typical values at TJ = 25°C and VINP = 5.0V.
PARAMETER
TYP
SEL shorted to VISO (5.0 V output); IISO = 0
to 100 mA
1.5%
VISO DC load regulation
SEL shorted to GNDS (3.3 V output); IISO = 0
to 145 mA
1.5%
SEL shorted to VISO (5.0 V output); IISO =
100 mA
60%
SEL 100kΩ to VISO (5.4V output); IISO = 90
mA
60%
SEL shorted to GNDS (3.3V output); IISO =
145 mA
50%
SEL 100kΩ to GNDS (3.7V output); IISO =
130 mA
53%
Efficiency at maximum
recommended load (1)
tRISE
MIN
VISO DC load regulation
VISO(LOAD)
EFF
TEST CONDITIONS
VISO rise time, 10% - 90%
MAX
UNIT
EN = change from LO to HI, SEL shorted to
VISO (5.0V output); IISO = 1 mA
750
µs
EN = change from LO to HI, SEL 100kΩ to
GNDS (3.3V output); IISO = 1 mA
300
µs
THERMAL SHUTDOWN
TSDTHR
Thermal shutdown threshold
Junction Temperature, Rising
165
°C
TSDHYST
Thermal shutdown hysteresis
Junction Temperature, Falling
27
°C
(1)
(2)
Efficiency calculation: EFF = (VISO x IISO) / (VINP x IINP)
See the Section 7.3.3 section for discussion of VISO regulation across load and temperature conditions for all output voltage settings.
6.10 Switching Characteristics
Over operating temperature range (TJ = –40°C to 150°C), VINP = 4.5V to 5.5V, CINP = COUT = 10 µF, SEL connected to VISO,
internal clock mode, unless otherwise noted. All typical values at TJ = 25°C and VINP = 5.0V.
PARAMETER
8
TEST CONDITIONS
fSW_INT
DC/DC Converter Clock
Internal clock mode
CMTI
Static common-mode
transient immunity
Slew Rate of GNDP versus GNDS, VCM =
1000 V
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MIN
TYP
MAX
UNIT
7.2
8
8.8
MHz
100
V/ns
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6.11 Insulation Characteristics Curves
1E+12
TDDB Line ( < 1 PPM Failure Rate)
Safety Margin Zone: 1440 VRMS, 143 Years
Operating Zone: 1200 VRMS, 76 Years
1E+11
1E+10
Time to Failure (sec)
1E+9
1E+8
1E+7
1E+6
1E+5
1E+4
1E+3
1E+2
1E+1
500
1000
1500
2000
2500
3000
3500
Stress Voltage (VRMS)
4000
4500
5000
5500
6000
D057
Working isolation voltage = 1200 VRMS
Projected lifetime = 76 years
TA up to 150°C
Stress voltage frequency = 60 Hz
Figure 6-1. Insulation Lifetime Projection Data
450
2000
VINP = 4.5 V
VINP = 5.5 V
1750
Safety Limiting Power (mW)
Safety Limiting Current (mA)
400
350
300
250
200
150
100
1500
1250
1000
750
500
250
50
0
0
0
20
40
60
80
100
120
Ambient Temperature (ºC)
140
160
0
D029
Figure 6-2. Thermal Derating Curve for Safety
Limiting Current per VDE
20
40
60
80
100
120
Ambient Temperature (ºC)
140
160
D031
Figure 6-3. Thermal Derating Curve for Safety
Limiting Power per VDE
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700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-40
VISO Output Power (mW)
VISO Output Power (mW)
6.12 Typical Characteristics
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
-20
0
20
40
60
80 100
Ambient Temperature (ºC)
120
140
160
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-40
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
-20
0
D022
VISO = 5.0 V
550
VISO Output Power (mW)
VISO Output Power (mW)
500
450
400
350
300
250
200
150
0
-40
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
-20
0
20
40
60
80 100
Ambient Temperature (ºC)
120
140
160
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-40
160
D023
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
-20
D024
VISO = 3.3 V
0
20
40
60
80 100
Ambient Temperature (ºC)
120
140
160
D025
VISO = 3.7 V
Figure 6-6. Maximum VISO Output Power vs.
Temperature
10
140
Figure 6-5. Maximum VISO Output Power vs.
Temperature
600
50
120
VISO = 5.4 V
Figure 6-4. Maximum VISO Output Power vs.
Temperature
100
20
40
60
80 100
Ambient Temperature (ºC)
Figure 6-7. Maximum VISO Output Power vs.
Temperature
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140
140
120
120
VISO Output Current (mA)
VISO Output Current (mA)
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100
80
60
40
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
20
0
-40
-20
0
100
80
60
40
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
20
20
40
60
80 100
Ambient Temperature (ºC)
120
140
0
-40
160
-20
0
D026
180
180
160
160
140
140
120
100
80
60
0
-40
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
-20
0
160
D027
120
100
80
60
40
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
20
20
40
60
80 100
Ambient Temperature (ºC)
120
140
0
-40
160
-20
0
D028
VISO = 3.3 V
20
40
60
80 100
Ambient Temperature (ºC)
120
140
160
D029
VISO = 3.7 V
Figure 6-10. Maximum VISO Output Current vs.
Temperature
Figure 6-11. Maximum VISO Output Current vs.
Temperature
70
70
60
60
50
50
Efficiency (%)
Efficiency (%)
140
Figure 6-9. Maximum VISO Output Current vs.
Temperature
VISO Output Current (mA)
VISO Output Current (mA)
Figure 6-8. Maximum VISO Output Current vs.
Temperature
20
120
VISO = 5.4 V
VISO = 5.0 V
40
20
40
60
80 100
Ambient Temperature (ºC)
40
30
40
30
20
20
10
10
0
0
0
10
VINP = 5.0 V
20
30
40
50
60
70
Load Current (mA)
VISO = 5.0 V
80
90
100
0
10
D006
TA = 25°C
Figure 6-12. Power Supply Efficiency vs Load
Current (IISO)
VINP = 5.0 V
20
30
40
50
60
70
Load Current (mA)
VISO = 5.4 V
80
90
100
D008
TA = 25°C
Figure 6-13. Power Supply Efficiency vs Load
Current (IISO)
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60
60
50
50
40
40
Efficiency (%)
Efficiency (%)
SNVSB38D – SEPTEMBER 2019 – REVISED JANUARY 2021
30
20
30
20
10
10
0
0
0
20
40
VINP = 5.0 V
60
80
100
Load Current (mA)
VISO = 3.3 V
120
0
140
20
40
60
80
100
Load Current (mA)
D007
TA = 25°C
VINP = 5.0 V
Figure 6-14. Power Supply Efficiency vs Load
Current (IISO)
VISO = 3.7 V
120
D009
TA = 25°C
Figure 6-15. Power Supply Efficiency vs Load
Current (IISO)
5.5
5.1
VINP = 4.5 V
VINP = 5.0 V
VINP = 5.5 V
VINP = 4.5 V
VINP = 5.0 V
VINP = 5.5 V
5.05
5.45
Output Voltage (V)
Output Voltage (V)
140
5
4.95
5.4
5.35
4.9
5.3
0
10
20
30
40
50
60
70
Load Current (mA)
VISO = 5.0 V
80
90
100
0
10
20
30
D012
TA = 25°C
40
50
60
70
Load Current (mA)
VISO = 5.4 V
80
90
100
D013
TA = 25°C
Figure 6-16. Isolated Supply Voltage (VISO) vs Load Figure 6-17. Isolated Supply Voltage (VISO) vs Load
Current (IISO)
Current (IISO)
3.4
3.8
VINP = 4.5 V
VINP = 5.0 V
VINP = 5.5 V
VINP = 4.5 V
VINP = 5.0 V
VINP = 5.5 V
3.75
Output Voltage (V)
Output Voltage (V)
3.35
3.3
3.7
3.65
3.25
3.6
3.2
0
20
40
60
80
100
Load Current (mA)
VISO = 3.3 V
120
0
140
D011
TA = 25°C
20
40
60
80
100
Load Current (mA)
VISO = 3.7 V
120
140
D010
TA = 25°C
Figure 6-18. Isolated Supply Voltage (VISO) vs Load Figure 6-19. Isolated Supply Voltage (VISO) vs Load
Current (IISO)
Current (IISO)
12
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5.20
5.60
5.10
5.50
Output Voltage (V)
Output Voltage (V)
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5.00
4.90
4.80
-40
5.40
5.30
-20
0
VINP = 5.0 V
20
40
60
80
100
Free-Air Temperature (ºC)
VISO = 5.0 V
120
5.20
-40
140
-20
0
D014
IISO = 50 mA
VINP = 5.0 V
20
40
60
80
100
Free-Air Temperature (ºC)
VISO = 5.4 V
120
140
D015
IISO = 50 mA
3.50
3.90
3.40
3.80
Output Voltage (V)
Output Voltage (V)
Figure 6-20. Isolated Supply Voltage (VISO) vs Free- Figure 6-21. Isolated Supply Voltage (VISO) vs FreeAir Temperature
Air Temperature
3.30
3.60
3.20
3.10
-40
3.70
-20
0
VINP = 5.0 V
20
40
60
80
100
Free-Air Temperature (ºC)
VISO = 3.3 V
120
3.50
-40
140
-20
0
D016
VINP = 5.0 V
IISO = 75 mA
20
40
60
80
100
Free-Air Temperature (ºC)
VISO = 3.7 V
120
140
D017
IISO = 75 mA
Figure 6-22. Isolated Supply Voltage (VISO) vs Free- Figure 6-23. Isolated Supply Voltage (VISO) vs FreeAir Temperature
Air Temperature
250
Input Supply Current (mA)
Short-Circuit Supply Current (mA)
280
260
240
220
200
4.5
200
150
100
VISO = 3.3 V
VISO = 3.7 V
VISO = 5.0 V
VISO = 5.4 V
50
0
4.6
4.7
4.8 4.9
5
5.1 5.2
Input Suppy Voltage (V)
5.3
5.4
5.5
0
20
D018
TA = 25°C
Figure 6-24. Short-Circuit Supply Current (IVIN_SC)
vs Supply Voltage (VINP)
VINP = 5.0 V
40
60
80
100
Load Current (mA)
120
140
160
D019
TA = 25°C
Figure 6-25. Input Supply Current (IVINP) vs Load
Current (IISO)
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VINP UVLO Threshold (V)
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4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3
-40
Falling Threshold
RisingThreshold
-20
0
20
40
60
80
Temperature (ºC)
100
120
140
Figure 6-26. Typical VINP UVLO Threshold vs Junction Temperature (TJ)
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7 Detailed Description
7.1 Overview
The UCC12050 device integrates a high-efficiency, low-emissions isolated DC/DC converter. This approach
provides typically 500 mW of clean, steady power across a 5000 VRMS reinforced isolation barrier.
The integrated DC/DC converter uses switched mode operation and proprietary circuit techniques to reduce
power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of an
on-chip transformer provide high efficiency and low radiated emissions.
The VINP supply is provided to the primary power controller that switches the power stage connected to the
integrated transformer. Power is transferred to the secondary side, rectified, and regulated to a level set by the
SEL pin condition.
A fast feedback control loop monitors VISO and the output load, and ensures low overshoots and undershoots
during load transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VINP supply, which
ensures robust system performance under noisy conditions.
UCC12050 is suitable for applications that have limited board space and require more integration. These devices
are also suitable for very-high voltage applications, where power transformers meeting the required isolation
specifications are bulky and expensive.
7.2 Functional Block Diagram
VINP
Control
UVLO
EN
OSC
SYNC
SYNC_OK
Transformer
Driver
SEL
VISO
Rectifier
GNDS
÷2
Ext CLK
Detect
GNDP
7.3 Feature Description
7.3.1 Enable and Disable
Forcing EN low disables the device, which greatly reduces the VINP power consumption. Pull the EN pin high to
enable normal device functionality. The EN pin has a weak internal pull-down resistor, so the device floats to the
disable state if the pin is left open.
7.3.2 UVLO, Power-Up, and Power-Down Behavior
The UCC12050 has an undervoltage lockout (UVLO) on the VINP power supply. Upon power-up, while the VINP
voltage is below the threshold voltage VUVPR, the primary side transformer driver is disabled, and VISO output
is off. The output powers up once the threshold is met. Likewise, if VINP falls below VUVPF, the converter is
disabled and there is no output at VISO. Both UVLO threshold voltages have hysteresis to avoid chattering.
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7.3.3 VISO Load Recommended Operating Area
Figure 7-1 depicts the device VISO regulation behavior across the output load range, including when the output
is overloaded. For proper device operation, ensure that the device VISO output load does not exceed the
maximum output current (IOUT_MAX). The value for IOUT_MAX over different temperature and VINP conditions are
shown from Figure 6-8 to Figure 6-11. The following protection mechanisms will be engaged if the UCC12050 is
loaded beyond the recommended operating area:
1. The device limits the maximum output power. If a load exceeding IOUT_MAX is applied, VISO drops accordingly
to meet the maximum power limit.
2. If VISO drops below nominal 3.8 V while operating in the constant power limit region, the over-power
fold-back feature will switch the power converter from active rectification to passive rectification, and the
built-in recovery hysteresis will ensure the UCC12050 recovers at a lower output power. The device returns
to active rectification when load drops and VISO increases above nominal 4.3V.
3. The device triggers a soft-start reset if VISO drops below the nominal 1.8-V threshold. This reset is designed
to protect the device during VISO short-circuit conditions.
4. Thermal shutdown protection disables the converter if the device is operated in any of the above regions
long enough to raise the silicon junction temperature above the thermal shutdown threshold. See the Section
7.3.4 section for more details on this device feature.
VISO
1
Consta nt Power Limit
VISO_SET
Active Re ctif ica tion
2
Pas siv e Rect ification
Recomme nded
Operating
Are a
Reset Threshold
3
Ove rload
Protection
IOUT_MAX
IOUT
Figure 7-1. VISO Load Recommended Operating Area Description
7.3.4 Thermal Shutdown
Thermal protection is also integrated to help prevent the device from getting damaged during overload and shortcircuit conditions on the isolated output. Under these conditions, the device temperature starts to increase. When
the silicon junction temperature Tj sensed at the primary side die goes above the threshold TSDTHR(typical
165°C), thermal shutdown activates and the primary controller turns off which removes the energy supplied
to the VISO load, which causes the device to cool off. When the junction temperature drops approximately
27°C (TSDHYST) from the shutdown point, the device starts to function normally. If an overload or output shortcircuit condition prevails, this protection cycle is repeated. Make sure the design prevents the device junction
temperatures from reaching such high values.
7.3.5 External Clocking and Synchronization
The UCC12050 has an internal oscillator trimmed to drive the transformer at 8.0 MHz. An external clock may be
applied at the SYNC pin to override the internal oscillator. This external clock will be divided by 2, so the target
range for the external clock signal at SYNC is 16 MHz ±10%. When a valid external clock signal is detected,
the internal spread spectrum modulation (SSM) algorithm is disabled. This allows an external clock signal with a
unique SSM to be applied. The depth and frequency of SSM is a tradeoff verses low frequency modulated VISO
voltage ripple. The SYNC_OK pin is asserted LOW if there is no external SYNC clock or one that is outside of
16
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the operating range of the device is detected. In this state, the external clock is ignored and the DC/DC converter
is clocked by the internal oscillator. The pin is in high impedance if a valid clock is applied on SYNC.
7.3.6 VISO Output Voltage Selection
The SEL pin is monitored during power-up — within the first 1 ms after applying VINP above the UVLO rising
threshold or enabling via the EN pin — to detect the desired regulation voltage for the VISO output. Note that
after this initial monitoring, the SEL pin no longer affects the VISO output level. In order to change the output
mode selection, either the EN pin must be toggled or the VINP power supply must be cycled off and back on.
Section6.4 provides more details on the SEL pin functionality.
7.3.7 Electromagnetic Compatibility (EMC) Considerations
UCC12050 devices use spread spectrum modulation for the internal oscillator and advanced internal layout
scheme to minimize radiated emissions at the system level.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the device
incorporates many chip-level design improvements for overall system robustness.
7.4 Device Functional Modes
Table 7-1 lists the supply functional modes for this device.
Table 7-1. Device Functional Modes
INPUTS
(1)
Isolated Supply Output Voltage (VISO) Setpoint
EN
SEL
HIGH
Shorted to VISO
5.0 V
HIGH
100 kΩ to VISO
5.4 V
HIGH
Shorted to GNDS
3.3 V
HIGH
100 kΩ to GNDS
3.7 V
HIGH
OPEN(1)
UNSUPPORTED
LOW
X
0V
The SEL pin has an internal weak pull-down resistance to ground, but leaving this pin open is not recommended.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The UCC12050 device is suitable for applications that have limited board space and desire more integration.
This device is also suitable for very high voltage applications, where power transformers meeting the required
isolation specifications are bulky and expensive.
8.2 Typical Application
Figure 8-1 shows the typical application schematic for the UCC12050 device supplying an isolated load.
5V
10 F
0.1 F
1
EN
GNDS 16
2
GNDP
GNDS 15
3
VINP
VISO 14
4
SYNC
5
SYNC_OK
6
NC
7
NC
8
NC
0.1 F
10 F
Load
PWM
RSYNC
Isolation Barrier
RPU
RSEL
SEL 13
NC 12
NC 11
NC 10
GNDS
9
Figure 8-1. Typical Application
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8.2.1 Design Requirements
To design using UCC12050, a few simple design considerations must be evaluated. Table 8-1 shows some
recommended values for a typical application. See Section 9 and Section 10 sections to review other key design
considerations for the UCC12050.
Table 8-1. Design Parameters
PARAMETER
RECOMMENDED VALUE
Input supply voltage, VINP
4.5 V to 5.5 V
Decoupling capacitance between VINP and GNDP
10 µF, 16 V, ± 10%, X7R
Decoupling capacitance between VISO and GNDS (1)
10 µF, 16 V, ± 10%, X7R
Optional additional capacitance on VISO or VINP to reduce high-frequency ripple
0.1 µF, 50 V,± 10%, X7R
Pull-up resistor from SYNC_OK to VINP, RPU
100 kΩ
Pull-up resistor from SEL to VISO for 5.0V output voltage mode, RSEL
0Ω
Pull-up resistor from SEL to VISO for 5.4V output voltage mode, RSEL
100 kΩ
Optional SYNC signal impedance-matching resistor, RSYNC
External clock signal applied on SYNC
(1)
Match source — typical values are 50 Ω, 75 Ω,
100 Ω, or 1 kΩ
16 MHz
See Section 8.2.2.1 section.
8.2.2 Detailed Design Procedure
Place ceramic decoupling capacitors as close as possible to the device pins. For the input supply, place the
capacitor(s) between pin 3 (VINP) and pin 2 (GNDP). For the isolated output supply, place the capacitor(s)
between pin 14 (VISO) and pin 15 (GNDS). This location is of particular importance to the input decoupling
capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms of
the power drive circuits. The recommended capacitor value is 10 µF. Ensure the capacitor dielectric material is
compatible with the target application temperature.
8.2.2.1 VISO Output Capacitor Selection
The UCC12050 is optimized to run with an effective output capacitance of 5 µF to 20 µF. A ceramic capacitor is
recommended. Ceramic capacitors have DC-Bias and temperature derating effects, which both have influence
the final effective capacitance. Choose the right capacitor carefully in combination with considering its package
size, dielectric and voltage rating. It is good design practice to include one 0.1-µF capacitor close to the device
for high-frequency noise reduction.
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VISO Ripple (10 mV / div)
VISO Ripple (10 mV / div)
8.2.3 Application Curves
Time (2.0 Ps/div)
Time (2.0 Ps/div)
D033
VINP = 5.0 V
VISO = 5.4 V
Bandwidth = 20 MHz
D034
VINP = 5.0 V
Bandwidth = 20 MHz
Figure 8-3. VISO Ripple, 5.4-V Output, 90% Load
VISO Ripple (10 mV / div)
VISO Ripple (10 mV / div)
Figure 8-2. VISO Ripple, 5.4-V Output, 10% Load
VISO = 5.4 V
Time (2.0 Ps/div)
Time (2.0 Ps/div)
D035
VINP = 5.0 V
VISO = 5.0 V
Bandwidth = 20 MHz
D036
VINP = 5.0 V
Bandwidth = 20 MHz
Figure 8-5. VISO Ripple, 5.0-V Output, 90% Load
VISO Ripple (10 mV / div)
VISO Ripple (10 mV / div)
Figure 8-4. VISO Ripple, 5.0-V Output, 10% Load
VISO = 5.0 V
Time (2.0 Ps/div)
Time (2.0 Ps/div)
D037
VINP = 5.0 V
VISO = 3.7 V
Bandwidth = 20 MHz
Figure 8-6. VISO Ripple, 3.7-V Output, 10% Load
20
D038
VINP = 5.0 V
VISO = 3.7 V
Bandwidth = 20 MHz
Figure 8-7. VISO Ripple, 3.7-V Output, 90% Load
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VISO Ripple (10 mV / div)
VISO Ripple (10 mV / div)
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Time (2.0 Ps/div)
Time (2.0 Ps/div)
D039
Bandwidth = 20 MHz
IISO load (20 mA / div)
Figure 8-8. VISO Ripple, 3.3-V Output, 10% Load
VISO (50 mV / div)
D040
VINP = 5.0 V
VISO = 3.3 V
Bandwidth = 20 MHz
Figure 8-9. VISO Ripple, 3.3-V Output, 90% Load
IISO load (20 mA / div)
VISO = 3.3 V
VISO (50 mV / div)
VINP = 5.0 V
VISO
IISO load
VISO
IISO load
Time (200 Ps/div)
Time (200 Ps/div)
D041
D042
IISO load (20 mA / div)
VISO (50 mV / div)
VISO (50 mV / div)
IISO load (20 mA / div)
Figure 8-10. VISO Load Transient Response, 10% to Figure 8-11. VISO Load Transient Response, 90% to
90% Load Step, 5.0-V Input, 5.4-V Output
10% Load Step, 5.0-V Input, 5.4-V Output
VISO
IISO load
VISO
IISO load
Time (200 Ps/div)
Time (200 Ps/div)
D043
D044
Figure 8-12. VISO Load Transient Response, 10% to Figure 8-13. VISO Load Transient Response, 90% to
90% Load Step, 5.0-V Input, 5.0-V Output
10% Load Step, 5.0-V Input, 5.0-V Output
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IISO load (30 mA / div)
VISO (50 mV / div)
VISO (50 mV / div)
IISO load (30 mA / div)
SNVSB38D – SEPTEMBER 2019 – REVISED JANUARY 2021
VISO
IISO load
VISO
IISO load
Time (200 Ps/div)
Time (200 Ps/div)
D045
D046
IISO load (30 mA / div)
VISO (50 mV / div)
VISO (50 mV / div)
IISO load (30 mA / div)
Figure 8-14. VISO Load Transient Response, 10% to Figure 8-15. VISO Load Transient Response, 90% to
90% Load Step, 5.0-V Input, 3.7-V Output
10% Load Step, 5.0-V Input, 3.7-V Output
VISO
IISO load
VISO
IISO load
Time (200 Ps/div)
Time (200 Ps/div)
D047
D047
7
7
6
6
5
5
VISO (1.0 V / div)
VISO (1.0 V / div)
Figure 8-16. VISO Load Transient Response, 10% to Figure 8-17. VISO Load Transient Response, 90% to
90% Load Step, 5.0-V Input, 3.3-V Output
10% Load Step, 5.0-V Input, 3.3-V Output
4
3
2
4
3
2
1
1
0
0
-1
-1
Time (400 Ps/div)
Time (400 Ps/div)
D049
Figure 8-18. VISO Soft Start at 10% Rated Load,
5.0-V Input, 5.4-V Output
22
D050
Figure 8-19. VISO Soft Start at 90% Rated Load,
5.0-V Input, 5.4-V Output
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7
7
6
6
5
5
VISO (1.0 V / div)
VISO (1.0 V / div)
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4
3
2
4
3
2
1
1
0
0
-1
-1
Time (400 Ps/div)
Time (400 Ps/div)
D051
Figure 8-21. VISO Soft Start at 90% Rated Load,
5.0-V Input, 5.0-V Output
5
5
4
4
3
3
VISO 1.0 V / div)
VISO 1.0 V / div)
Figure 8-20. VISO Soft Start at 10% Rated Load,
5.0-V Input, 5.0-V Output
D052
2
1
0
2
1
0
-1
-1
Time (400 Ps/div)
Time (400 Ps/div)
D053
Figure 8-23. VISO Soft Start at 90% Rated Load,
5.0-V Input, 3.7-V Output
5
5
4
4
3
3
VISO 1.0 V / div)
VISO 1.0 V / div)
Figure 8-22. VISO Soft Start at 10% Rated Load,
5.0-V Input, 3.7-V Output
D054
2
1
0
2
1
0
-1
-1
Time (400 Ps/div)
Time (400 Ps/div)
D055
Figure 8-24. VISO Soft Start at 10% Rated Load,
5.0-V Input, 3.3-V Output
D056
Figure 8-25. VISO Soft Start at 90% Rated Load,
5.0-V Input, 3.3-V Output
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9 Power Supply Recommendations
The recommended input supply voltage (VINP) for the UCC12050 is between 4.5 V and 5.5 V. To help ensure
reliable operation, adequate decoupling capacitors must be located as close to supply pins as possible. Place
local bypass capacitors between the VINP and GNDP pins at the input, and between VISO and GNDS at the
isolated output supply. Low ESR, ceramic surface mount capacitors are recommended. It is further suggested
that one place two such capacitors: one with a value of 10 µF for supply bypassing, and an additional 100-nF
capacitor in parallel for high frequency filtering. The input supply must have an appropriate current rating to
support output load required by the end application.
10 Layout
10.1 Layout Guidelines
The UCC12050 integrated isolated power solution simplifies system design and reduces board area usage.
Proper PCB layout is important in order to achieve optimum performance. Here is a list of recommendations:
1. Place decoupling capacitors as close as possible to the device pins. For the input supply, place the
capacitor(s) between pin 3 (VINP) and pin 2 (GNDP). For the isolated output supply, place the capacitor(s)
between pin 14 (VISO) and pin 15 (GNDS). This location is of particular importance to the input decoupling
capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms
of the power drive circuits.
2. Because the device does not have a thermal pad for heat-sinking, the device dissipates heat through the
respective GND pins. Ensure that enough copper (preferably a connection to the ground plane) is present on
all GNDP and GNDS pins for best heat-sinking.
3. If space and layer count allow, it is also recommended to connect the VINP, GNDP, VISO and GNDS pins to
internal ground or power planes through multiple vias of adequate size. Alternatively, make traces for these
nets as wide as possible to minimize losses.
4. TI also recommends grounding the no-connect pins (NC) to their respective ground planes. For pins 6, 7,
and 8, connect to GNDP. For pins 10, 11, and 12, connect to GNDS. This will allow more continuous ground
planes and larger thermal mass for heat-sinking.
5. A minimum of four layers is recommended to accomplish a low-EMI PCB design. Inner layers can be spaced
closer than outer layers and used to create a high-frequency bypass capacitor between GNDP and GNDS
to reduce radiated emissions. Ensure proper spacing, both inter-layer and layer-to-layer, is implemented to
avoid reducing isolation capabilities. These spacings will vary based on the printed circuit board construction
parameters, such as dielectric material and thickness.
6. Pay close attention to the spacing between primary ground plane (GNDP) and secondary ground plane
(GNDS) on the PCB outer layers. The effective creepage and or clearance of the system will be reduced if
the two ground planes have a lower spacing than that of the device package.
7. To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or
copper below the UCC12050 device on the outer copper layers.
24
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10.2 Layout Example
Figure 10-1. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For development support, refer to:
•
•
•
High-efficiency, low-emission, isolated DC/DC converter-based analog input module reference design
Isolated delta-sigma modulator based AC/DC voltage and current measurement module reference design
Isolated power architecture reference design for communication and analog input/output modules
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• UCC12050 Evaluation Module User Guide
• Isolation Glossary
• A Reinforced-isolated Analog Input Chain for Space-constrained Applications
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical and Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
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6-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC12050DVE
ACTIVE
SO-MOD
DVE
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
UCC12050
UCC12050DVER
ACTIVE
SO-MOD
DVE
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
UCC12050
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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