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Design
UCC2808A-1, UCC2808A-2, UCC3808A-1, UCC3808A-2
SLUS456F – APRIL 1999 – REVISED JULY 2018
UCCx808A Low-Power Current-Mode Push-Pull PWM
1 Features
•
1
•
•
•
•
•
•
•
•
The UCCx808A dual-output drive stages are
arranged in a push-pull configuration. Both outputs
switch at half the oscillator frequency using a toggle
flip-flop. The dead time between the two outputs is
typically 60 ns to 200 ns depending on the values of
the timing capacitor and resistors, thus limiting each
output stage duty cycle to less than 50%.
Dual-Output Drive Stages in Push-Pull
Configuration
Current-Sense Discharge Transistor to Improve
Dynamic Response
130-μA Typical Starting Current
1-mA Typical Run Current
Operation to 1 MHz
Internal Soft Start
On-Chip Error Amplifier With 2-MHz Gain
Bandwidth Product
On-Chip VDD Clamping
Output Drive Stages Capable of 500-mA PeakSource Current, 1-A Peak-Sink Current
The UCCx808A family offers a variety of package
options, temperature range options, and choice of
undervoltage lockout levels. The family has UVLO
thresholds and hysteresis options for off-line and
battery-powered systems.
The UCCx808A is an enhanced version of the
UCC3808 family. The significant difference is that the
A versions feature an internal discharge transistor
from the CS pin to ground, which is activated each
clock cycle during the oscillator dead time. The
feature discharges any filter capacitance on the CS
pin during each cycle and helps minimize filter
capacitor values and current sense delay.
2 Applications
•
•
•
•
High-Efficiency Switch-Mode Power Supplies
Telecom DC-to-DC Converters
Point-of-Load Power Modules
Low-Cost Push-Pull and Half-Bridge Applications
Device Information(1)
PART NUMBER
UCC2808A-1,
UCC2808A-2,
UCC3808A-2
3 Description
The UCCx808A devices are a family of BiCMOS
push-pull,
high-speed,
low-power,
pulse-width
modulators. The UCCx808A contains all of the control
and drive circuitry required for off-line or DC-to-DC
fixed frequency current-mode switching power
supplies with minimal external parts count.
UCC3808A-1
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
TSSOP (8)
3.00 mm × 4.40 mm
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
VOUT
UCCx808A
VIN
VDD
OUTA
RC
OUTB
COMP
FB
CS
GND
Isolated
Feedback
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC2808A-1, UCC2808A-2, UCC3808A-1, UCC3808A-2
SLUS456F – APRIL 1999 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagrams ....................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (December 2016) to Revision F
Page
•
Changed the Simplified Application........................................................................................................................................ 1
•
Changed references of N package to P package (PDIP) ...................................................................................................... 5
•
Changed the Electrostatic Discharge Caution statement .................................................................................................... 15
Changes from Revision D (August 2002) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Lead temperature, soldering (10 s): 300°C maximum .............................................................................................. 5
2
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SLUS456F – APRIL 1999 – REVISED JULY 2018
5 Pin Configuration and Functions
UCCx808A D or P Package
8-Pin SOIC or PDIP
Top View
UCC2808A-x, UCC3808A-2 PW Package
8-Pin TSSOP
Top View
COMP
1
8
VDD
FB
2
7
CS
3
RC
4
OUTA
1
8
OUTB
OUTA
VDD
2
7
GND
6
OUTB
COMP
3
6
RC
5
GND
FB
4
5
CS
Not to scale
Not to scale
Pin Functions
PIN
NAME
SOIC, PDIP
TSSOP
TYPE (1)
DESCRIPTION
COMP
1
3
O
COMP is the output of the error amplifier and the input of the PWM comparator. The
error amplifier in the UCCx808A is a true low-output impedance, 2-MHz operational
amplifier. As such, the COMP pin can both source and sink current. However, the
error amplifier is internally current limited, so that zero duty cycle can be externally
forced by pulling COMP to GND. The UCCx808A family features built-in full-cycle soft
start. Soft start is implemented as a clamp on the maximum COMP voltage.
CS
3
5
I
The input to the PWM, peak current, and overcurrent comparators. The overcurrent
comparator is only intended for fault sensing. Exceeding the overcurrent threshold
causes a soft-start cycle. An internal MOSFET discharges the current sense filter
capacitor to improve dynamic performance of the power converter.
FB
2
4
I
The inverting input to the error amplifier. For best stability, keep FB lead length as
short as possible and FB stray capacitance as small as possible.
GND
5
7
G
Reference ground and power ground for all functions. Because of high currents, and
high-frequency operation of the UCC3808A, a low impedance circuit board ground
plane is highly recommended.
O
Alternating high current output stages. Both stages are capable of driving the gate of a
power MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A
peak-sink current. The output stages switch at half the oscillator frequency, in a pushpull configuration. When the voltage on the RC pin is rising, one of the two outputs is
high, but during fall time, both outputs are off. This dead time between the two
outputs, along with a slower output rise time than fall time, insures that the two outputs
can not be on at the same time. This dead time is typically 60 ns to 200 ns and
depends upon the values of the timing capacitor and resistor. The high-current-output
drivers consist of MOSFET output devices, which switch from VDD to GND. Each
output stage also provides a very low impedance to overshoot and undershoot. This
means that in many cases, external-schottky-clamp diodes are not required.
O
Alternating high current output stages. Both stages are capable of driving the gate of a
power MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A
peak-sink current. The output stages switch at half the oscillator frequency, in a pushpull configuration. When the voltage on the RC pin is rising, one of the two outputs is
high, but during fall time, both outputs are off. This dead time between the two
outputs, along with a slower output rise time than fall time, insures that the two outputs
can not be on at the same time. This dead time is typically 60 ns to 200 ns and
depends upon the values of the timing capacitor and resistor. The high-current-output
drivers consist of MOSFET output devices, which switch from VDD to GND. Each
output stage also provides a very low impedance to overshoot and undershoot. This
means that in many cases, external-schottky-clamp diodes are not required.
OUTA
OUTB
(1)
7
6
1
8
P = Power, G = Ground, I = Input, O = Output
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Pin Functions (continued)
PIN
NAME
RC
VDD
4
SOIC, PDIP
4
8
TSSOP
6
2
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TYPE (1)
DESCRIPTION
O
The oscillator programming pin. The UCC3808A’s oscillator tracks VDD and GND
internally, so that variations in power supply rails minimally affect frequency stability.
Functional Block Diagrams shows the oscillator block diagram. Only two components
are required to program the oscillator: a resistor (tied to the VDD and RC), and a
capacitor (tied to the RC and GND). The approximate oscillator frequency is
determined by the simple formula in Equation 1.
The recommended range of timing resistors is between 10 kΩ and 200 kΩ and range
of timing capacitors is between 100 pF and 1000 pF. Timing resistors less than 10 kΩ
must be avoided. For best performance, keep the timing capacitor lead to GND as
short as possible, the timing resistor lead from VDD as short as possible, and the
leads between timing components and RC as short as possible. Separate ground and
VDD traces to the external timing network are encouraged.
P
The power input connection for this device. Although quiescent VDD current is very
low, total supply current is higher, depending on OUTA and OUTB current, and the
programmed oscillator frequency. Total VDD current is the sum of quiescent VDD
current and the average OUT current. Knowing the operating frequency and the
MOSFET gate charge (Qg), average OUT current can be calculated from Equation 2.
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to
the chip as possible along with an electrolytic capacitor. A 1-µF decoupling capacitor
is recommended.
Copyright © 1999–2018, Texas Instruments Incorporated
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SLUS456F – APRIL 1999 – REVISED JULY 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
15
V
Supply voltage (IDD ≤ 10 mA)
Supply current
20
mA
–0.5
A
1
A
VDD + 0.3
(not to exceed 6)
V
P package
1
W
D package
650
PW package
400
OUTA/OUTB source current (peak)
OUTA/OUTB sink current (peak)
Analog inputs (FB, CS)
–0.3
Power dissipation at TA = 25°C
mW
Junction temperature, TJ
–55
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Currents are positive into, negative out of the specified terminal. Consult the packaging section of the Power Supply Control Products
Data Book for thermal limitations and considerations of packages.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage
TJ
Junction temperature
MIN
MAX
UCCx808-1
13
14
UCCx808-2
5
14
UCC2808-x
–40
85
UCC3808-x
0
70
UNIT
V
°C
6.4 Thermal Information
UCC2808A-x
UCC3808A-2
UCCx808A
THERMAL METRIC (1)
D (SOIC)
P (PDIP)
PW (TSSOP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
105.4
57
151.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.9
49.6
36.5
°C/W
RθJB
Junction-to-board thermal resistance
46.5
34.3
81.5
°C/W
ψJT
Junction-to-top characterization parameter
8.7
19.5
1.7
°C/W
ψJB
Junction-to-board characterization parameter
45.9
34.2
79.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 1999–2018, Texas Instruments Incorporated
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6.5 Electrical Characteristics
TA = 0°C to 70°C for the UCC3808A-x and –40°C to +85°C for the UCC2808A-x, VDD = 10 V (1), 1-µF capacitor from VDD to
GND, R = 22 kΩ, C = 330 pF, and TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Oscillator frequency
175
Oscillator amplitude/VDD (2)
0.44
194
213
kHz
0.5
0.56
V/V
1.95
2
2.05
V
1
µA
OSCILLATOR
ERROR AMPLIFIER
Input voltage
COMP = 2 V
Input bias current
–1
Open loop voltage gain
60
80
dB
0.3
2.5
mA
mA
COMP sink current
FB = 2.2 V, COMP = 1 V
COMP source current
FB = 1.3 V, COMP = 3.5 V
–0.2
–0.5
Maximum duty cycle
Measured at OUTA or OUTB
48%
49%
Minimum duty cycle
COMP = 0 V
PWM
50%
0%
CURRENT SENSE
Gain (3)
Maximum input signal
COMP = 5 V (4)
CS to output delay
COMP = 3.5 V,
CS from 0 mV to 600 mV
CS source current
1.9
2.2
2.5
V/V
0.45
0.5
0.55
V
100
200
ns
–200
CS sink current
CS = 0.5 V, RC = 5.5 V
(5)
Over current threshold
COMP to CS offset
CS = 0 V
nA
5
10
0.7
0.75
0.8
mA
V
0.35
0.8
1.2
V
V
OUTPUT
OUT low level
I = 100 mA
0.5
1
OUT high level
I = –50 mA, VDD – OUT
0.5
1
V
Rise time
CL = 1 nF
25
60
ns
Fall time
CL = 1 nF
25
60
ns
11.5
12.5
13.5
UCCx808A-2
4.1
4.3
4.5
UCCx808A-1
7.6
8.3
9
UCCx808A-2
3.9
4.1
4.3
UCCx808A-1
3.5
4.2
5.1
UCCx808A-2
0.1
0.2
0.3
FB = 1.8 V, rise from 0.5 V to 4 V
3.5
20
Start-up current
VDD < start threshold
130
260
µA
Operating supply current
FB = 0 V, CS = 0 V (1) (6)
1
2
mA
VDD zener shunt voltage
IDD = 10 mA (7)
14
15
V
UNDERVOLTAGE LOCKOUT
UCCx808A-1 (1)
Start threshold
Minimum operating voltage after start
Hysteresis
V
V
V
SOFT START
COMP rise time
ms
OVERALL
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
13
For UCCx808A-1, set VDD above the start threshold before setting at 10 V.
Measured at RC. Signal amplitude tracks VDD.
Gain is defined by: A = ΔVCOMP / ΔVCS, 0 V ≤ VCS ≤ 0.4 V.
Parameter measured at trip point of latch with FB at 0 V.
The internal current sink on the CS pin is designed to discharge an external filter capacitor. It is not intended to be a DC sink path.
Does not include current in the external oscillator network.
Start threshold and Zener shunt threshold track one another.
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SLUS456F – APRIL 1999 – REVISED JULY 2018
6.6 Typical Characteristics
14
1000
C = 100 pF
12
C = 1000 pF
10
IDD
with 1 nF load
10
C = 330 pF
IDD -mA
C = 820 pF
8
6
4
C = 560 pF
IDD
without load
2
0
1
0
50
100
150
200
0
200
400
RT − Timing Resistor − kΩ
600
800
1000
1200
Oscillator Frequency − kHz
Figure 1. Oscillator Frequency
vs External RC Values
Figure 2. IDD vs Oscillator Frequency
1.2
90
180
80
160
70
140
Gain - dB
COMP - CS Offset - V
1.0
0.8
0.6
60
120
Phase
50
100
40
80
30
60
0.4
20
0.2
40
10
0
Gain
20
0
−55
−35
−15
5
25
45
65
85
105
125
Phase Margin - Degrees
Frequency - kHz
C = 220 pF
100
VDD = 10 V, t = 25°C
0
1
100
Temperature - °C
10000
1000000
Frequency − Hz
Figure 3. COMP to CS Offset vs Temperature
Figure 4. Error Amplifier Gain and Phase Response
vs Frequency
400
300
C = 1000 pF
350
VDD = 5 V
250
C = 560 pF
C = 820 pF
200
Dead Time - ns
Dead Time - ns
300
C = 330 pF
150
C = 220 pF
VDD = 7.5 V
250
200
VDD = 10 V
150
100
100
50
C = 100 pF
0
50
50
100
150
200
250
RT − Timing Resistor − k Ω
Figure 5. Output Dead Time vs External RC Values
Copyright © 1999–2018, Texas Instruments Incorporated
−100
−50
0
50
100
150
Temperature - °C
Figure 6. Dead Time vs Temperature
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Typical Characteristics (continued)
120
300
100
250
VDD = 5 V
Ohms
Ohms
VDD = 5 V
80
200
VDD = 7.5 V
150
60
VDD = 7.5 V
100
40
VDD = 10 V
VDD = 10 V
50
20
0
0
−100
−50
0
50
100
150
Temperature - °C
Figure 7. RC RDS(on) vs Temperature
8
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−100
−50
0
50
100
150
Temperature - °C
Figure 8. CS RDS(on) vs Temperature
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SLUS456F – APRIL 1999 – REVISED JULY 2018
7 Detailed Description
7.1 Overview
The UCCx808A-x device is a highly integrated, low-power current mode push-pull PWM controller. The controller
employs low starting current and an internal control algorithm that offers accurate output voltage regulation in the
presence of line and load variations. The UCCx808A-x family of parts has UVLO thresholds and hysteresis
options for off-line and battery-powered systems.
Table 1. Undervoltage Lockout Levels
PART NUMBER
TURNON
THRESHOLD
TURNOFF
THRESHOLD
UCCx808A-1
12.5
8.3
UCCx808A-1
4.3
4.1
7.2 Functional Block Diagrams
OVERCURRENT
COMPARATOR
FB
COMP
CS
2
1
3
22 k Ω
PEAK CURRENT
COMPARATOR
8
VDD
7
OUTA
6
OUTB
5
GND
14 V
0.75 V
0.5 V
2.0 V
2.2 V
VDD OK
OSCILLATOR
S
Q
PWM
LATCH
R
1.2R
VDD−1 V
Q
S
S
Q
Q
T
Q
R
R
PWM
COMPARATOR
VDD
0.5 V
R
SOFT START
VOLTAGE
REFERENCE
SLOPE = 1 V/ms
4
Note: Pinout shown is for SOIC and PDIP packages. TSSOP pinout is different.
RC
Copyright © 2016, Texas Instruments Incorporated
The oscillator generates a sawtooth waveform on RC. During the RC rise time, the output stages alternate on time,
but both stages are off during the RC fall time. The output stages switch a 1/2 the oscillator frequency, with ensured
duty cycle of < 50% for both outputs.
Figure 9. Block Diagram
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Functional Block Diagrams (continued)
RC
4
FREQUENCY =
VDD
2
S
R
1.41
RC
(APPROXIMATE
FREQUENCY)
Q
OSCILLATOR
OUTPUT
0.2 V
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Block Diagram of Oscillator
7.3 Feature Description
7.3.1 Pin Descriptions
7.3.1.1 COMP
The COMP pin is the output of the error amplifier and the input of the PWM comparator. The error amplifier in the
UCC3808 is a true low-output impedance, 2-MHz operational amplifier. As such, the COMP pin can both source
and sink current. However, the error amplifier is internally current limited, so that zero duty cycle can be
externally forced by pulling COMP to GND.
The UCC3808 family features built-in full cycle soft start. Soft start is implemented as a clamp on the maximum
COMP voltage.
7.3.1.2 CS
The input to the PWM, peak current, and overcurrent comparators. The overcurrent comparator is only intended
for fault sensing. Exceeding the overcurrent threshold causes a soft-start cycle.
7.3.1.3 FB
The inverting input to the error amplifier. For best stability, keep FB lead length as short as possible and FB stray
capacitance as small as possible.
7.3.1.4 GND
Reference ground and power ground for all functions. Because of high currents, and high-frequency operation of
the UCC3808, a low-impedance printed-circuit board ground plane is highly recommended.
7.3.1.5 OUTA and OUTB
Alternating high current output stages. Both stages are capable of driving the gate of a power MOSFET. Each
stage is capable of 500-mA peak source current, and 1-A peak sink current.
The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the
RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between
the two outputs, along with a slower output rise time than fall time, insures that the two outputs can not be on at
the same time. This dead time is typically 60 ns to 200 ns and depends upon the values of the timing capacitor
and resistor.
The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output
stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external
Schottky clamp diodes are not required.
10
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www.ti.com
SLUS456F – APRIL 1999 – REVISED JULY 2018
Feature Description (continued)
7.3.1.6 RC
The oscillator programming pin. The oscillator of the UCC3808-x tracks VDD and GND internally, so that
variations in power supply rails minimally affect frequency stability. Figure 10 shows the oscillator block diagram.
Only two components are required to program the oscillator: a resistor (tied to the VDD and RC), and a capacitor
(tied to the RC and GND). The approximate oscillator frequency is determined by Equation 1.
1.41
fOSCILLATOR =
RC
where
•
•
•
frequency is in Hz
resistance in Ω
capacitance in Farads
(1)
The recommended range of timing resistors is between 10 kΩ and 200 kΩ and range of timing capacitors is
between 100 pF and 1000 pF. Timing resistors less than 10 kΩ must be avoided.
For best performance, keep the timing capacitor lead to GND as short as possible, the timing resistor lead from
VDD as short as possible, and the leads between timing components and RC as short as possible. Separate
ground and VDD traces to the external timing network are encouraged.
7.3.1.7 VDD
The power input connection for this device. Although quiescent VDD current is very low, total supply current is
higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total VDD current is
the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the
MOSFET gate charge (Qg), average OUT current can be calculated with Equation 2.
IOUT = Qg × F
where
•
F is frequency
(2)
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. TI recommends a 1-µF decoupling capacitor.
7.4 Device Functional Modes
7.4.1 VCC
When VCC rises above 12.5 V (for the UCCx808A-1) or above 4.3 V (for the UCCx808-2) the device is enabled.
When any fault conditions are cleared, a soft-start condition is initiated and the gate driver outputs begin
switching.
When VCC drops below 8.3 V (for the UCCx808-1) or 4.1 V (for the UCCx808-2) the device enters the UVLO
protection mode and both gate drivers are actively pulled low.
7.4.2 Push-Pull or Half-Bridge Function
Because the device provides alternate 180° out-of-phase gate drive signals (OUTA and OUTB), it may be used
as a controller for the push-pull or half-bridge topologies. For the half-bridge topology the UCCx808A-x requires a
an external high side gate driver or pulse transformer on one or both of the OUTA and OUTB signals.
Copyright © 1999–2018, Texas Instruments Incorporated
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A 200-kHz push-pull application circuit with a full-wave rectifier is shown in Figure 11. The output, VO, provides
5 V at 50 W maximum and is electrically isolated from the input. Because the UCC3808A is a peak-current-mode
controller the 2N2907 emitter following amplifier (buffers the CT waveform) provides slope compensation which is
necessary for duty ratios greater than 50%. Capacitor decoupling is very important with a single ground IC
controller, and a 1 μF is suggested as close to the IC as possible. The controller supply is a series RC for startup, paralleled with a bias winding on the output inductor used in steady-state operation.
Isolation is provided by an optocoupler with regulation done on the secondary side using the TL431 adjustable
precision shunt regulator. Small signal compensation with tight voltage regulation is achieved using this part on
the secondary side. Many choices exist for the output inductor depending on cost, volume, and mechanical
strength. Several design options are iron powder, molypermalloy (MPP), or a ferrite core with an air gap as
shown here. The main power transformer has a Magnetics Inc. ER28 size core made of P material for efficient
operation at this frequency and temperature. The input voltage may range from 36 Vdc to 72 Vdc.
8.2 Typical Application
ER28
8:2
32CTQ030
NP2
NS1
NP1
NS2
VO
5 V 50 W
+
EF25 7µH
680 µF
0.01 µF
+
−
LOOP B
VIN
36 V TO 72 V
4700 µF
0.47 µF
1000 pF
−
BYV
28−200
62 Ω
62 Ω
BYV
28−200
1000 pF
200 Ω
LOOP A
COMP
51 kΩ
1/4 W
19.1 kΩ
IRF640
IRF640
4700 pF 20 kΩ
12
10 Ω
2.2 Ω
470 pF
DF02SGICT
2.2 Ω
1 mH
3
0.1 µF
10 µF
0.1 µF
1 TL431
2
19.1 kΩ
2 kΩ
0.2 Ω
20 kΩ
VDD
8
330 pF
OUTA OUTB GND
7
6
PRIMARY
GROUND
5
UCC3808AD−1
1
2
COMP FB
3
CS
4
240 Ω
RC
RC
4.99 kΩ
2.80 kΩ
86.6 kΩ
CURRENT
SENSE
4.99 kΩ
2K12907
4
H11A1
U3
3
20 kΩ
330 pF
432 Ω
0.1 µF
5
2
6
1
0.01 µF
1 kV
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Typical Application Diagram: 48-Vin, 5-V, 50-W Output
12
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SLUS456F – APRIL 1999 – REVISED JULY 2018
Typical Application (continued)
8.2.1 Design Requirements
Table 2 lists the design parameters for the UCC3808A-x.
Table 2. Design Parameters
PARAMETER
VALUE
Output voltage
5V
Rated output power
50 W
Input DC voltage range
36 V to 72 V
Switching frequency
210 kHz
8.2.2 Detailed Design Procedure
The output, VO, provides 5 V at 50 W maximum and is electrically isolated from the input. Because the
UCC3808A is a peak current mode controller, the 2N2907 emitter follower amplifier buffers the oscillator
waveform (RC pin) and provides slope compensation to the current sense (CS) input. This is necessary for duty
cycle ratios of greater than 50%.
Capacitor decoupling is provided on the VDD pin. TI recommends using a minimum decoupling capacitance of
10-µF electrolytic and 0.1-µF ceramic. The ceramic capacitor must be as close to the VDD pin as possible. The
UCC3808A is initially powered up from the 36-V to 72-V input supply . Once the power supply has started, the
bias supply is provided by an auxiliary winding on the main power transformer.
Isolation is provided by an optocoupler with regulation done on the secondary side using the TL431 precision
programmable reference. The internal error amplifier of the UCC3808A is set up as a unity gain amplifier and the
compensation network is provided on the secondary side.
Many choices exist for the output inductor depending on cost and size constraints. Design options are powdered
iron, molypermalloy or the ferrite core option used in this design. The power transformer is a low profile design,
EFD25 size, using the Magnetics Inc. P material. This material is a good choice for low power loss at high
switching frequency.
The switching frequency is set at 210 kHz with the RC network on the RC pin.
8.2.3 Application Curves
90
180
80
160
120
CT=1000pF
120
Gain dB
60
Phase
50
100
40
80
30
60
20
40
Dead Time – ns
140
70
Phase Margin - Degrees
100
CT=820pF
80
CT=560pF
60
40
CT=100pF
CT=220pF
CT=330pF
20
10
20
Gain
0
0
1
100
10000
1000000
Frequency – Hz
Figure 12. Error Amplifier Gain and Phase Response
vs Frequency
Copyright © 1999–2018, Texas Instruments Incorporated
0
0
20
40
60
80
100
RT – Timing Resistor – kΩ
Figure 13. Dead Time vs Timing Resistor
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SLUS456F – APRIL 1999 – REVISED JULY 2018
www.ti.com
9 Power Supply Recommendations
The VDD power terminal for the device requires the placement of electrolytic capacitor as energy storage
capacitor because of the 1-A drive capability of the UCCx808A-x controller. Also a low-ESR noise decoupling
capacitor is required and it must be placed as close as possible to the VDD and GND pins. Ceramic capacitors
with stable dielectric characteristics over temperature are recommended. X7R is a suitable dielectric material for
use here.
TI recommends a 10-µF, 25-V electrolytic capacitor part.
10 Layout
10.1 Layout Guidelines
1. Place the VDD capacitor as close as possible between the VDD pin and GND of the UCCx808A-x, tracked
directly to both pins.
2. A small, external filter capacitor is recommended on the CS pin. Track the filter capacitor as directly as
possible from the CS to GND pins.
3. The tracking and layout of the FB pin and connecting components is critical to minimizing noise pickup and
interference. Reduce the total surface area of traces on the FB net to a minimum.
4. The OUTA and OUTB pins have a high-current source and sink capability. An external gate resistor is
recommended to damp oscillations. A value of around a few Ohms is recommended. A pulldown resistor on
the gate to source is recommended to prevent the MOSFET gate from floating on if there is an open-circuit
fault in the gate drive path.
10.2 Layout Example
SOIC-8
PDIP-8
TOP VIEW
1 COMP
VDD 8
2 FB
OUTA 7
3 CS
OUTB 6
4 RC
GND 5
Figure 14. Recommended Layout
14
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UCC2808A-1, UCC2808A-2, UCC3808A-1, UCC3808A-2
www.ti.com
SLUS456F – APRIL 1999 – REVISED JULY 2018
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
Power Supply Control Products Data Book
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC2808A-1
Click here
Click here
Click here
Click here
Click here
UCC2808A-2
Click here
Click here
Click here
Click here
Click here
UCC3808A-1
Click here
Click here
Click here
Click here
Click here
UCC3808A-2
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLUS456F – APRIL 1999 – REVISED JULY 2018
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
UCC2808AD-1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808A-1
Samples
UCC2808AD-2
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808A-2
Samples
UCC2808AD-2G4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808A-2
Samples
UCC2808ADTR-1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808A-1
Samples
UCC2808ADTR-1G4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808A-1
Samples
UCC2808ADTR-2
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808A-2
Samples
UCC2808ADTR-2G4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808A-2
Samples
UCC2808APW-1
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
2808A1
Samples
UCC2808APW-1G4
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
2808A1
Samples
UCC2808APW-2
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
2808A2
Samples
UCC2808APWTR-2
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
2808A2
Samples
UCC3808AD-1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3808A-1
Samples
UCC3808AD-1G4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3808A-1
Samples
UCC3808AD-2
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3808A-2
Samples
UCC3808ADTR-1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3808A-1
Samples
UCC3808ADTR-1G4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3808A-1
Samples
UCC3808ADTR-2
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3808A-2
Samples
UCC3808APW-2
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
3808A2
Samples
UCC3808APWTR-2
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
3808A2
Samples
UCC3808APWTR-2G4
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
3808A2
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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