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UCC29950
SLUSC18A – SEPTEMBER 2014 – REVISED MARCH 2015
UCC29950 CCM PFC and LLC Combo Controller
1 Features
2 Applications
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High Efficiency PFC and Half-Bridge Resonant
LLC Combo Controller
Continuous Conduction Mode (CCM) Boost Power
Factor Correction
Supports Self-Bias or Auxiliary (external) Bias
Mode of Operation
PFC Loops Fully Internally Compensated
PFC Stage Design in 3 Easy Steps
(design voltage feedback, current feedback and
power stage)
Fixed 100-kHz PFC Frequency with Dithering for
Ease of EMI Compliance
True Input Power Limit, Independent of Line
Voltage
Fixed LLC Frequency Operating Range of 70 kHz
to 350 kHz
Dead-Time Varied Across Load Range for LLC
Half-Bridge Power Stage to Extend ZVS Range
Three-Level LLC Over-Current Protection
Hiccup Mode Operation for Continuous Overload
and Short-Circuit Power Protection
Low Standby Power Consumption Enabled by
Active Control of High-Voltage Start-Up MOSFET
and X-Cap Discharge Function
Built In Soft-Start and Converter Sequencing to
Simplify Design
AC Line Brownout Protection, with Fail Indicator
PFC Bus Over-Voltage and Under-Voltage
Protection
Over-Temperature Protection
External Gate Drivers for Scalability with Power
Level
SOIC-16 Package
•
•
•
•
Offline AC-to-DC Server Power Supplies (80
PLUS® Bronze/Silver/Gold)
Industrial DIN Rail and Open Frame Power
Supplies
Gaming and Printer Power
High-Density Adapters
Lighting Drivers
3 Description
The UCC29950 provides all the control functionality
for an AC-to-DC converter with a CCM boost Power
Factor Correction (PFC) stage followed by an LLC
converter stage. The controller is optimized to allow
ease of use.
Proprietary CCM PFC algorithms enable the system
to achieve high efficiency, smaller converter size with
high power factor. The integrated LLC controller
enables a high-efficiency DC-to-DC conversion stage
utilizing soft switching for low EMI noise. Integration
of PFC control and LLC control in a combo controller
allows the control algorithms to take advantage of
information from both stages.
The controller includes a control circuit for start-up
using a Depletion Mode MOSFET with internal device
power management that minimizes external
component requirements and helps lower system
implementation costs.
To further reduce the standby power an X-Cap
discharge circuit is integrated. The UCC29950
implements a complete suite of system protection
functions, including AC line brownout, PFC bus under
voltage PFC and LLC, over current and thermal
shutdown.
Device Information(1)
PART NUMBER
UCC29950
PACKAGE
BODY SIZE (NOM)
SOIC 16 Pin (D)
9.90 mm x 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
AC_DET
MD_SEL/PS_ON
1
6
15
7
UCC29950
4 SUFG
5 SUFS
VCC
GD2 2
GD1 14
FB 12
VCC 3
Vout
LLC_CS (mV)
PFC_CS
AGND
11
GND
9 AC2
8
VBULK
16
LLC_CS
13
PFC_GD
10 AC1
LLC stage Over-Current Protection Profile
TRANSFORMER
VBLK
CBLK
EMC Filter
VAC
900
600
400
300
0
0
10
Time (ms)
52
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC29950
SLUSC18A – SEPTEMBER 2014 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
1
1
1
2
3
6
Specifications......................................................... 6
5.1 Detailed Pin Descriptions ......................................... 4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
Absolute Maximum Ratings ...................................... 6
Storage Conditions.................................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Typical Characteristics ............................................ 11
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 29
8
Application and Implementation ........................ 36
8.1 Application Information............................................ 36
8.2 Typical Application ................................................. 36
8.3 Do's and Don'ts ...................................................... 57
9 Power Supply Recommendations...................... 58
10 Layout................................................................... 59
10.1 Layout Guidelines ................................................. 59
10.2 Layout Example .................................................... 61
11 Device and Documentation Support ................. 61
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
61
61
61
61
12 Mechanical, Packaging, and Orderable
Information ........................................................... 61
4 Revision History
Changes from Original (September 2014) to Revision A
•
2
Page
Changed marketing status from custom to catalog. ............................................................................................................... 1
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5 Pin Configuration and Functions
SOIC (D)
16 Pins
Top View
GND
1
16
PFC_GD
GD2
2
15
AC_DET
VCC
3
14
GD1
SUFG
4
13
PFC_CS
SUFS
5
12
FB
AGND
6
11
LLC_CS
MD_SEL/
PS_ON
7
10
AC1
VBULK
8
9
AC2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
1
-
Power ground. Connect all the gate driver pulsating current returns to this pin.
GD2
2
O
Gate drive output for LLC stage MOSFET. The typical peak current is 1-A source, 1.6-A sink
(CLOAD = 1 nF)
VCC
3
-
Bias supply input.
SUFG
4
O
Start-up MOSFET gate drive output. Leave open circuit if not used.
SUFS
5
I
Start-up MOSFET Source. Connect to VCC if not used.
AGND
6
-
Signal ground. Connect all device control signal returns to this ground.
MD_SEL/PS_
ON
7
I
Dual function pin:
1. Mode Select Function (MD_SEL): Select self bias or Aux bias mode of operation.
2. Power Supply On Function (PS_ON): Stop/start control of PFC and LLC stages, Aux
Bias mode only.
VBULK
8
I
Voltage sense input for PFC stage output.
AC2
9
I
AC line voltage detection. Connect 9.3 MΩ between AC line and this pin.
AC1
10
I
AC line voltage detection. Connect 9.3 MΩ between AC line and this pin.
LLC_CS
11
I
Current sense input for the LLC stage.
FB
12
I
Feedback signal input for LLC stage.
PFC_CS
13
I
Current sense input for the PFC stage.
GD1
14
O
Gate drive output for LLC stage MOSFET. The typical peak current is 1-A source, 1.6-A sink
(CLOAD = 1 nF).
AC_DET
15
O
AC line voltage fail signal output, for system use.
PFC_GD
16
O
The typical peak current is 0.6-A source, 1.3-A sink (CLOAD = 1 nF).
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5.1 Detailed Pin Descriptions
5.1.1 VCC
The VCC pin is the power supply input terminal to the device. This pin should be decoupled with a 10-μF ceramic
bypass capacitor in both Aux Bias and Self Bias Modes. An additional hold-up capacitor is needed at this pin if
operating in Self Bias Mode.
5.1.2 MD_SEL/PS_ON
MD_SEL/PS_ON pin. This pin can be used to make the UCC29950 operate in Self Bias or Auxiliary Bias Mode.
If MD_SEL/PS_ON pin is high during start up the controller enters Self Bias Mode. In this mode, the capacitor on
the device’s VCC rail is charged by an external depletion mode MOSFET connected at the SUFS and SUFG
pins. Once the VCC rail reaches an appropriate operating voltage, the FET is turned off and the VCC rail is then
supplied from an auxiliary winding on the LLC transformer. This avoids the standing or static losses incurred if a
drop resistor from rectified AC line were used to charge the VCC rail during startup.
If the MD_SEL/PS_ON pin is held low for at least 10 ms during start up the UCC29950 enters Aux Bias Mode.
Once this time has passed this pin may be used to turn on the PFC stage on its own or both the PFC and LLC
stages according to the values given in the MD_SEL/PS_ON part of the Electrical Characteristics.
5.1.3 SUFG, SUFS
The SUFG and SUFS are the control pins for an external start-up depletion mode FET. The use of a switched
device here eliminates the static power dissipation in a conventional resistive start-up approach where a drop
resistor from the rectified AC line to VCC is typically used. As a result standby power consumption is reduced.
Connect the FET gate to SUFG and its source to SUFS. The drain of the FET is connected to the rectified AC
voltage. SUFG and SUFS control the initial charging of the capacitor on the VCC rail during start-up in the SelfBias mode of operation. In this mode SUFG tracks SUFS as CVCC is charged and VCC rises. When VCC
reaches VCCSB(start) (typically 16.2 V) SUFG goes low. This turns the start-up FET off and the PFC and LLC gate
outputs start running. SUFG remains low unless VCC falls below VCCSB_UVLO(stop) (typically 7.9 V) or an X-Cap
discharge is required. If VCC falls below VCCSB_UVLO(stop) then SUFG goes high to turn the start-up FET on and
recharge CVCC back up to VCCSB_START.
SUFG and SUFS also provide an X-Cap discharge function in both Aux Bias and Self Bias Modes. This function
is described fully in Active X-Cap Discharge.
If the UCC29950 is used in Aux Bias Mode then VCC is supplied by an external source and the external
depletion mode FET is used only to provide the X-Cap discharge function. SUFG is at 0 V after a time
TMODE_SEL_READ has elapsed during power up after CVCC exceeds VCCSTART. SUFG goes high whenever an XCap discharge is required. If the start up FET is not used and X-Cap discharge is not desired then SUFS should
be connected to VCC and SUFG should be left open circuit.
5.1.4 GD1, GD2
GD1 and GD2 are the LLC gate drive outputs for the LLC half-bridge power MOSFETs. A gate drive transformer
or other suitable device is required to generate a floating drive for the high-side MOSFET. The first and last LLC
gate drive pulses are normally half width and appear on GD1 and GD2 respectively. If the LLC_OCP3 level is
exceeded then the final pulse is of normal width. The typical peak current is 1-A source, 1.6-A sink (1-nF load).
4
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Detailed Pin Descriptions (continued)
5.1.5 GND
GND is the power ground for the device. Connect all the gate-driver pulsating current returns to this pin.
5.1.6 AGND
AGND is the signal ground for device control signals. Connect all control signal returns to this pin.
5.1.7 LLC_CS
LLC_CS is the LLC stage current sense input. LLC_CS is used for LLC stage over-load protection. The load
current is reflected to the primary side of the transformer where it is sensed using a resistor. The UCC29950
senses the LLC stage input current level and enters the over-current protection Shut-Down Mode when the
current-sense signal exceeds the current and time thresholds described in LLC Three Level Over-Current
Protection . The controller tries to resume operation at 1-s intervals.
5.1.8 FB
FB is the LLC stage control-loop feedback input. Connect the opto-coupler emitter to this pin. The FB pin is the
input to the internal VCO. The VCO generates the switching frequency of the LLC converter. GD1 and GD2 stop
switching if this pin is driven above VFB_LLC(off) (typically 3.75 V) and resume operation when it falls below VFB(max)
(typically 3.0 V). If this pin is held below VFB(min) (typically 200 mV) the GD1 and GD2 outputs runs at their
minimum frequency.
5.1.9 PFC_GD
PFC_GD is the gate-driver output for a PFC MOSFET. Connect the PFC MOSFET gate through a resistor to
control its switching speed. Because of the limited driving capability an external gate driver might be needed to
support certain power MOSFET input capacitance conditions. The typical peak current is 0.6-A source, 1.3-A
sink (CLOAD = 1 nF).
5.1.10 PFC_CS
PFC_CS is the current sense input for the PFC stage. It is recommended to add a current-limiting resistor
between the current-sense resistor and current-sense pin, to prevent damage during inrush conditions. A 1-kΩ
resistor normally suffices. The UCC29950 implements a new hybrid average current-control method which
controls the average current but uses the peak PFC_CS signal to terminate each switching cycle (see Hybrid
PFC Control Loop). Correct PCB layout is important to ensure that the signal at this pin is an accurate
representation of the current being controlled.
5.1.11 VBULK
The VBULK pin is used for PFC output-voltage sensing. Connect the sensing resistors to this pin. The upper
resistor in the potential divider must be 30 MΩ and the lower resistor must be 73.3 kΩ. The high impedance
reduces the static power dissipation.
5.1.12 AC1, AC2
AC1 and AC2 are the AC line voltage sensing inputs. The UCC29950 uses differential sensing for more accurate
measurement of line voltage. These pins must be connected to the two line inputs via 9.3-MΩ resistors.
5.1.13 AC_DET
The AC_DET is a system-level signal which may be used for indication and system control. AC_DET goes high if
the instantaneous AC voltage remains below the brownout level for longer than 32 ms. An opto-coupler can be
used to send a signal to a system supervisor device so that appropriate action can be taken. In order to provide
hold-up time to the system, the power stages continue to operate for 100 ms after AC_DET goes high. This
behavior is shown in Figure 10, Figure 11 and Figure 12.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Supply Voltage
VCC
–0.3
20
V
Continuous Input
Voltage Range
LLC_CS
–0.3
4.5
V
FB, AC1, AC2, VBULK, MD_SEL/PS_ON
–0.3
VCC+0.3
V
0
4.5
V
AC_DET
SUFS
–0.3
20
V
SUFG
–0.3
SUFS+0.3
V
GD1, GD2, PFC_GD
–0.5
VCC+0.5
V
PFC_CS
–1.3
4.5
V
Continuous Input
Current Range
PFC_CS
±15
mA
TSOL
Lead temperature (10 s)
260
°C
125
°C
Operational Junction Temperature, TJ
(1)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Storage Conditions
Tstg
Storage temperature range
MIN
MAX
UNIT
–40
150
°C
6.3 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Supply voltage range
11
18
V
VFB
FB pin voltage range
0
VCC
V
VMD_SEL/PS_ON
MD_SEL/PS_ON pin voltage range
0
VCC
RL1/RL2
Line sensing resistors
9.3
V
MΩ
6.5 Thermal Information
UCC29950
THERMAL METRIC
(1)
SOIC (D)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
78.9
RθJC(top)
Junction-to-case (top) thermal resistance
40.3
RθJB
Junction-to-board thermal resistance
36.3
ψJT
Junction-to-top characterization parameter
8.9
ψJB
Junction-to-board characterization parameter
36.0
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.6 Electrical Characteristics
–40°C < TJ < 125°C (1), VCC = 12 V, all voltages are with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–1
–2
–4
UNIT
VCC Bias Supply (Self Bias Mode)
ISUFS
Charging current into VCC
SUFS = 7.5 V, VCC = 4 V
VCCSB(start)
In Self Bias mode, the controller will not start
PFC and LLC gate drive outputs until the start up
FET has charged the capacitance on the VCC
pin above this level
MD_SEL/PS_ON = VCC at
power-up (self bias mode)
15.0
16.2
17.4
In Self Bias mode, VCC must be greater than this
VCCSB_UVLO(stop) level to allow the controller to continue to output
VCC falling Self Bias Mode
the PFC and LLC gate drives.
7.3
7.9
8.5
mA
V
VCC Bias Supply (Aux Bias Mode)
VCCSTART (2)
VCCSTOP
(2)
VCCAB_UVLO(start
)
Controller logic starts at this VCC voltage
VCC rising
4.4
6
7.0
Controller logic stops at this VCC voltage
VCC falling
3.7
5.0
5.8
10.0
10.5
10.9
9.1
9.6
10.0
7.5
8.0
18.3
mA
1.6
2.1
V
In Aux Bias Mode, VCC must be greater than this VCC rising MD_SEL/PS_ON
level to allow the controller to start the PFC and
= 0 V at power-up (Aux Bias
LLC gate drive outputs.
Mode)
In Aux Bias Mode, VCC must be greater than this
VCCAB_UVLO(stop) level to allow the controller to continue to output
VCC falling Aux Bias Mode
the PFC and LLC gate drives.
V
VCC Supply Current
ICCENABLE
GD1, GD2 at LLCFMAX.
Device is Enabled and providing PFC & LLC gate PFC_GD at fPFC (100 kHz
drive outputs
nom). GD1, GD2 and
PFC_GD pins unloaded.
MD_SEL/PS_ON, Mode Select Function at Power Up
VMODE_SELSB
Minimum voltage on the MD_SEL/PS_ON pin
that will select Self Bias mode on power up (see
Device Functional Modes).
1.1
TMODE_SEL_READ
After VCC pin exceeds VCCSTART. This is the
minimum time that the MD_SEL/PS_ON pin must
remain below VMODE_SELSB to ensure that Aux
Bias Mode is selected (see Device Functional
Modes).
10
ms
MD_SEL/PS_ON, Power Supply On Function, Aux Bias Mode Only
VPS_ONPFC_RUN
Minimum voltage on the MD_SEL/PS_ON pin
that causes PFC stage to run (3)
20
25
33
%VCC
VPS_ONLLCPFC_R
Minimum voltage on the MD_SEL/PS_ON pin
that causes PFC and LLC stages to run (3)
66
75
85
%VCC
UN
AC_DET
VOH_TP_LZ
AC_DET output high
I(AC_DET) = –1 mA
2.5
3.1
4.1
V
VOL
AC_DET output low
I(AC_DET) = 1 mA
19
35
80
mV
IO(max_source)
AC_DET source current
VOUT > 2.4 V
–1.6
mA
IO(max_sink)
AC_DET sink current
VOUT< 0.5 V
6.0
mA
(1)
(2)
(3)
8
The device has been characterized over the entire temperature range during development. Individual devices may enter temperature
shutdown (TSD) at TJ lower than 125°C.
VCCSTARTis always greater than VCCSTOP.
Threshold voltage will track VCC and is therefore specified as a percentage of VCC.
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Electrical Characteristics (continued)
–40°C < TJ < 125°C(1), VCC = 12 V, all voltages are with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.06
1.10
1.14
V
0.907
0.940
0.973
V
VBULK, PFC OUTPUT VOLTAGE
VBULK(ovp)
PFC output overvoltage protection (auto
recovery)
VBULK(reg)
VBULK regulation set-point
VBULK(llc_start)
LLC operation start threshold
0.70
0.73
0.77
V
VBULK(llc_stop)
LLC operation stop threshold
0.45
0.49
0.53
V
AC1, AC2, AC LINE SENSING FOR PFC
RAC1
AC1 pin resistance to AGND
AC1 pin
45
60
71
RAC2
AC2 pin resistance to AGND
AC2 pin
45
60
71
IAC(det) (4) (5)
AC_DET is active HIGH when IAC is below this
level
Force current into AC1 or
AC2 pins. Unused pin input
at 0 V.
7.03
7.48
7.93
IAC(low_falling) (4) (5)
PFC stage stops 100 ms after IAC is at or below
this level
Force current into AC1 or
AC2 pins. Unused pin input
at 0 V.
7.03
7.48
7.93
IAC(low_rising) (4) (5)
PFC stage is allowed to start when IAC is at or
above this level
Force current into AC1 or
AC2 pins. Unused pin input
at 0 V.
8.04
8.55
9.1
IAC(high_falling) (4) (5 PFC stage restarts if IAC falls below this level. No
)
soft-start
Force current into AC1 or
AC2 pins. Unused pin input
at 0 V.
30.7
32.0
33.3
IAC(high_rising) (4) (5) PFC stage stops if IAC is at or above this level
Force current into AC1 or
AC2 pins. Unused pin input
at 0 V.
31.8
33.1
34.4
PFC and LLC stages stop if IAC is at or above
this level
Force current into AC1 or
AC2 pins. Unused pin input
at 0 V.
32.8
34.2
35.6
–200
–225
–250
IAC(halt) (4) (5)
kΩ
µARMS
PFC_CS, PFC CURRENT SENSE
VPFCCS(cav_max)
VPFCCS(max)
Maximum voltage at PFC_CS pin, (ignoring
signal ripple due to inductor ripple current) that
determines maximum power delivered. Used to
determine RCS_PFC. (see PFC Stage Current
Sensing Figure 13 and Figure 6)
Maximum voltage at PFC_CS pin
mV
VBULK pin = 800 mV,
|VAC1 – VAC2| = VAC_PEAK (6)
–570
–800
–950
PFC_GD, PFC GATE DRIVER
VHI(pfc_2mA)
PFC_GD high level
IO(PFC_GD) = –2 mA
11.5
11.8
12.0
VHI(pfc_75mA)
PFC_GD high level
IO(PFC_GD) = –75 mA
8.5
9.5
10.5
RPFC(gd_hi)
PFC_GD pull-up resistance
IO(PFC_GD) = –50 mA
14
25
RPFC(gd_lo)
PFC_GD pull-down resistance
IO(PFC_GD) = 75 mA
4.4
10
tR(pfc)
PFC_GD rise time
Capacitive load of 1.0 nF on
PFC_GD pin, 20% to 80%
30
45
tF(pfc)
PFC_GD fall time
Capacitive load of 1.0 nF on
PFC_GD pin, 20% to 80%
10
25
fPFC
Switching frequency
Includes dithering of ±2 kHz
at nominal 333-Hz rate.
98
109
(4)
(5)
(6)
V
Ω
ns
87
kHz
These are specified at 25°C. The relative levels for these specifications track each other. The equivalent line voltages are given in
Table 3, assuming a source impedance of 9.3 MΩ.
This is the current into the AC1 or AC2 pins.
Tested at peak of line voltage or 90° from zero crossing.
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Electrical Characteristics (continued)
–40°C < TJ < 125°C(1), VCC = 12 V, all voltages are with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.17
0.2
0.23
3
3.10
UNIT
FB, LLC Control Loop Feedback
VFB(min) (7)
Minimum voltage on FB pin where LLC frequency Below VFB_MIN, LLC
is modulated
frequency is LLCFmin
VFB(max) (7)
Maximum voltage on FB pin where LLC
frequency is modulated
Between VFB_MAX, and
VFB_LLC_OFF LLC frequency is
LLCFmax
2.90
VFB(llc_off) (7)
Voltage on FB pin above which LLC gate drive
terminated
Once VFB exceeds
VFB_LLC_OFF, VFB must fall
below VFB_MAX to resume
switching
3.62
3.75
3.88
LLCFMIN (7)
Minimum LLC switching frequency
63.7
70
74.8
Maximum LLC switching frequency
321
350
378
LLCT(dead) (8)
Time for which GD1 and GD2 are both low during LLC dead-time at minimum
LLC operation at LLCFMIN
switching frequency.
224
300
388
ns
RFB
Internal resistance from FB pin to AGND
45
60
71
kΩ
0.87
0.9
0.94
0.27
0.30
0.33
LLCFMAX
(7)
V
kHz
LLC_CS, LLC Current Sense
VCS(ocp3) (9)
LLC Overcurrent threshold level three
VCS(llc_max)
Voltage at LLC_CS pin at 100% of full load
If this level is exceeded the
PFC and LLC stages will stop
for tLONG(fault). Restart with a
normal soft-start sequence
V
FAULT Section
tLONG(fault)
Recovery time after long fault
0.9
1.0
1.5
s
tSHORT(fault)
Recovery time after short fault
90
100
150
ms
GD1, GD2, LLC GATE Drive Output
VGD(hi_2mA)
GD1, GD2 output high level
IO(GDx) = –2 mA
11.5
11.8
12
VGD(hi_75mA)
GD1, GD2 output high level
IO(GDx) = –75 mA
9.3
10.1
10.9
RGD(hi)
GD1, GD2 gate driver pull-up resistance
IO(GDx) = –50 mA
5.8
10.5
RGD(lo)
GD1, GD2 gate driver pull-down resistance
IO(GDx) = 75 mA
1.6
5
tr(llcgd)
LLC gate driver rise time
Capacitive load of 1 nF on
GD1, GD2 pins
12
30
tf(llcgd)
LLC gate driver fall time
capacitive load of 1 nF on
GD1, GD2 pins (20% to 80%)
11
25
V
Ω
ns
Thermal Shutdown
TSD
Thermal shutdown temperature
TST
Start / restart temperature
(7)
(8)
(9)
10
125
113
°C
Refer to Figure 1.
Refer to Figure 2.
Refer to Table 4 for other LLC Stage Over-Current Protection Levels.
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400
900
350
800
300
LLC Dead Time (ns)
Switching Frequency (kHz)
6.7 Typical Characteristics
250
200
150
100
700
600
500
400
300
50
0
200
0
0.5
1
1.5
2
2.5
Feedback Voltage (V)
3
3.5
4
0
1
Figure 1. LLC Switching Frequency vs VFB
3
400
14
350
12
300
10
8
D001
250
200
6
150
4
100
50
2
0
10
20
30
40
50
60
Time (ms)
70
80
90
0
100
10
20
30
D001
Figure 3. LLC Period vs Time During Soft-Start
40
50
60
Time (ms)
70
80
90
100
D001
Figure 4. LLC Frequency vs Time During Soft-Start
0
1.005
VPFCCS(cav)
VPFCCS(cav_max)
VPFCCS(cav)
-0.03
1
-0.06
-0.09
0.995
Voltage (V)
Normalized Switching Frequency
4
Figure 2. LLC Dead Time vs VFB
16
Frequency (kHz)
LLC Period (µs)
2
Feedback Voltage (V)
D001
0.99
0.985
0.98
-0.12
-0.15
-0.18
-0.21
-0.24
-0.27
0.975
-0.3
0.97
-50
-0.33
-25
0
25
50
Temperature (C°)
75
100
125
0
D001
Figure 5. Switching Frequency vs Temperature
(for PFC and LLC). Normalized to 1 at 20°C
2
4
6
8
10
12
Time (ms)
14
16
18
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D001
Figure 6. PFC_CS Signal (diagrammatic)
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57.3
-1.6
57
-1.7
56.7
-1.8
SUFS to VCC Current (mA)
RAC1, RAC2 Resistance (k:)
Typical Characteristics (continued)
56.4
56.1
55.8
55.5
55.2
54.9
-2
-2.1
-2.2
-2.3
-2.4
54.6
-2.5
54.3
-40
-2.6
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
-20
D001
Figure 7. RAC1, RAC2 Resistance vs Temperature
12
-1.9
0
20
40
60
80
Temperature (°C)
100
120
140
D001
Figure 8. SUFS to VCC Current vs Temperature
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7 Detailed Description
7.1 Overview
The UCC29950 combines all the functions necessary to control a Boost PFC and LLC power system. It is
packaged in an SOIC-16 package. The SUFG and SUFS pins allow the system designer to use an external
depletion mode MOSFET to provide start up power instead of using a dissipative resistor. The use of highimpedance voltage sensing networks further reduces standby power. The combo device uses information from
both PFC and LLC stages to optimize the system efficiency, transient response and standby power. The
controller can be operated with bias current supplied from a small external PSU (Aux Bias) or from a winding on
the LLC transformer (Self Bias). In Aux Bias Mode, the MD_SEL/PS_ON pin allows the user to turn on the PFC
stage alone or both PFC and LLC stages.
The UCC29950 has many protection features, these include:
• Bias Rail Under-Voltage Lockout
• Active X-Cap Discharge
• Line Under-Voltage Detection
• Line Over-Voltage Detection
• Line Brownout Detection
• Three Level Output Overcurrent Profile on LLC Stage
• PFC Stage Constant Input Power Limit
• PFC Stage Input Current Limit
• PFC Stage Second Current Limit
• PFC Stage Output Overvoltage Protection
• VBLK Sensing Network Fault Detection
• VBLK Over-Voltage Protection
• PFC and LLC Stage Soft-Start
• PFC Stage Frequency Dithering
• Thermal Shutdown
The UCC29950 implements an advanced control algorithm to control the PFC stage input current. This
proprietary hybrid method combines both average and peak-mode control methods.
• Accurate control of the average current drawn from the line gives good THD.
• Peak inductor current information is used to terminate each PFC switching cycle.
• The algorithm is insensitive to variations in the peak-to-average current ratio.
The input current is accurately controlled so that it follows the correct sinusoidal shape and also gives inherent
cycle-by-cycle protection against excess MOSFET current. A further advantage is that the control loop is
insensitive to PFC inductor and bulk capacitor variations. The UCC29950 takes full advantage of this fact to
implement internal compensation of the PFC stage. This simplifies the system designer’s task and reduces the
external component count. A sophisticated soft-start algorithm is used to achieve a constant soft-start ramp time
over a wide range of bulk capacitor values and initial conditions.
An LLC stage is typically used to convert the PFC stage output to an isolated final voltage for system use. The
UCC29950 provides all the primary-side functions needed to control such a second stage. The input to the FB
pin is an isolated control signal from the output. This signal is fed into a voltage-to-frequency converter (VCO).
The VCO inserts an appropriate dead time and the resulting signals are routed through some on-chip drivers
connected to the GD1 and GD2 outputs. The dead time is shortest at low LLC frequencies and is increased
automatically as frequency is increased. A three level Over-Current Protection (OCP) function stops the GD1 and
GD2 signals if the current signal at the LLC_CS pin goes outside of a defined current vs time profile.
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7.2 Functional Block Diagram
SUFG
Over
Temperature
Protection
Fault Timer
and Control
4
Brownout
15
AC_DET
10
AC1
9
AC2
8
VBULK
13
PFC_CS
X-cap Discharge
5
VCC_UVLO
SUFS
Current
Limit
VCC
3
| VAC1 ± VAC2 |
AC Line
Process
VREF
+
Voltage
Loop
UVLO_REF
Soft Start
MD_SEL/
PS_ON
7
CONTROL
IAV_DEM
Current Loop
PFC_GD
16
+
PWM
OCP_REF
PFC Stop
GD1 14
PFC_OVP
VCC_UVLO
Brownout
Three Level OCP
VCO
GD2
PFC_OCP
2
11
LLC_CS
12
FB
Dead Time Profile
Soft Start
LLC_UV
14
1
6
GND
AGND
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7.3 Feature Description
Table 1. UCC29950 Features and Benefits
Feature
Benefit
Self-Bias Mode allowing off-line operation
Eliminate cost of Auxiliary Flyback Bias supply in system
Control output for external high-voltage, depletion mode start-up
MOSFET
Eliminates drop resistor from rectified AC line, reduces stand-by
power
Integrated X-Cap discharge function using external start-up
MOSFET
Eliminates bleed resistor across differential EMI filter capacitor,
reduces stand-by power
PFC stage design in 3 easy steps - (i) design voltage feedback
network, (ii) choose current sense feedback resistor, (iii) design
power stage
Greatly simplifies design effort
Advanced control algorithm for PFC Stage
Good iTHD and insensitivity to inductor and bulk capacitor variations,
Cycle by cycle PFC overcurrent protection
Internal compensation of PFC Stage Voltage and Current feedback
loops
Reduces Component count, eliminates 2 design steps (voltage and
current loop compensation)
Differential AC Line sensing with fixed 9.3M-ohm resistors
Accurate measurement of line conditions under no-load or start-up
conditions for improved performance and protection - Eliminates 1
design step (AC line sensing)
PFC frequency dithering
Simplifies EMI filtering and eases EMI compliance
True input power limit, independent of line voltage
Limit set by choice of RCS(pfc) allowing designer greater flexibility
compared to fixed limits that depending on AC line voltage
Zero Voltage Switching (ZVS) over a wide range of operating
conditions
Reduced switching losses in the LLC converter power devices
Three Level over current protection for LLC and Hiccup mode of
operation
Allows the power stage to ride through a short-term transient
overload but reacts quickly to protect the power stage from heavy
overload or output short-circuit events.
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7.3.1 Sense Networks
The UCC29950 uses fixed scaling factors to measure the signals at its pins. The circuit position of the voltage
sensing resistors is shown in Figure 9. The current sensing resistors are shown in Figure 13.
The resistors in the VBLK sensing network, RTOP and RBOT in Figure 9 have been chosen to minimize the power
dissipation and ensure correct operation over the expected tolerance bands. The impedance in this network may
be reduced by choosing lower value resistors provided that the potential division ratio is unchanged or kept within
the limits given below.
The nominal ratio is 30 MΩ/73.33 kΩ = 409.28. This has been chosen to give a nominal VBULK regulation setpoint
of 385 V. This voltage is the ideal operating point for the PFC. It prevents direct conduction into the bulk
capacitor at high line and prevents false OVP tripping due to load transients - especially under high load
conditions where the voltage ripple on the bulk capacitor is maximum. It is possible to change the nominal
setpoint within the limits below.
If the ratio is increased above the nominal value then there is a risk of triggering a sense network fault condition
at startup - as described in the next section. The maximum ratio is not an absolutely fixed value but is likely to be
about 425 with a corresponding VBULK regulation setpoint of 400 V. The minimum ratio is governed by the desire
to avoid direct conduction into the bulk capacitor when operating at high line. VBULK must be greater than 374 V
to avoid this condition on a 264 VRMS line. The corresponding minimum ratio is about 395.
Table 2. Sensing Resistor Values
RESISTOR
DESCRIPTION
MIN
TYP
MAX
UNIT
RL1 and RL2
1% tolerance parts are recommended. To meet
voltage ratings, it may be necessary to split the
resistance across more than one part.
9.21
RTOP
1% tolerance parts are recommended. To meet
voltage ratings, it may be necessary to split the
resistance across more than one part.
29.7
30.0
30.3
RBOT
1% tolerance parts are recommended. A parallel
combination of a 75-kΩ and a 3.3-MΩ resistor
gives a nominal 73.33 kΩ
72.50
73.33
74.07
RCS(pfc)
Value depends on system power level and is
given by Equation 59
33
RCS(llc)
Value depends on system power level and is
given by Equation 36
400
9.30
9.40
MΩ
kΩ
mΩ
EMC Filter
VBLK
VAC
RTOP
CBLK
RBOT
RL2
RL1
VBULK
8
10 AC1
9 AC2
UCC29950
Figure 9. Voltage Sensing Network
16
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7.3.2 Sense Network Fault Detection
In a boost converter, there is a direct conduction path from AC line to the bulk capacitor which ensures that it will
be charged to peak of line even if the PFC stage controller is inactive. At start-up the UCC29950 measures AC
line voltage and the voltage on the PFC bulk energy storage capacitor. If the UCC29950 measures VBLK to be
lower than VAC it enters a latched fault condition. This feature prevents the PFC stage from running if the upper
resistor in the voltage sensing network has gone open circuit. If the lower resistor has gone open circuit, then the
UCC29950 detects this as an over-voltage event on the output and PFC switching will not start.
7.3.3 PFC Stage Soft-Start
The UCC29950 soft-start will typically charge the PFC boost capacitor within 50 ms to 100 ms of starting.
7.3.4 AC Line Voltage Sensing
The UCC29950 uses differential AC line sensing through its AC1 and AC2 pins. Differential sensing provides
more accurate measurements than single ended sensing, especially at startup and under light load conditions. It
also allows faster detection of AC line disconnection or failure.
Normal single ended sensing assumes that the diodes connected to the negative going AC line are forward
biased and that a single measurement of the positive going AC line is a true representation of the input voltage.
This is normally true but if there is no current being drawn, as is the case under no-load or start up conditions,
then it is possible that all the diodes in the bridge are reverse biased. If this happens then a single ended
measurement will overestimate the true AC line voltage. The differential AC line sensing used in the UCC29950
avoids these errors.
The external resistor value impedance for AC1 and AC2 is required to be 9.3 MΩ. This reduces the static power
dissipation and provides the correct divider ratio in conjunction with the GAIN and OFFSET factors of the device,
(see Equation 1).
These factors are set at the time the UCC29950 is tested. They are used to compensate for device to device
variations in RAC1 and RAC2.
8#% = #%1 F #%2 F 1((5'6 × )#+0
(1)
AC1 and AC2 must be connected to the AC line side of the bridge rectifier through 9.3-MΩ resistors. The high
impedance sensing network is effectively a current source which is why the levels in the electrical characteristics
table are given in terms of currents rather than voltages. The equivalent voltages are given in Table 3.
The 9.3-MΩ resistors must be able to support the full voltage at peak of AC line and are conveniently made from
three 3.09-MΩ resistors in series. It is recommended to minimize the length of track between the ACx pins and
the lowest resistor in the chain.
Table 3. PFC AC Line Voltage Action Levels (1)
VOLTAGE
PARAMETER
MIN
TYP
MAX
VAC(det)
AC_DET will be active HIGH when VAC
is below this level
IAC(det)
65.5
70
74.5
VAC(low_falling)
PFC stage stops 100 ms after VAC is at
or below this level
IAC(low_falling)
65.5
70
74.5
VAC(low_rising)
PFC stage is allowed to start when VAC
is at or above this level
IAC(low_rising)
75
80
85.2
VAC(high_falling)
PFC stage restarts if VAC falls below this IAC(high_falling)
level
287
300
313
VAC(high_rising)
PFC stage stops if VAC is at or above
this level
IAC(high_rising)
297
310
323
VAC(halt)
PFC and LLC stages stop if VAC is at or
above this level
IAC(halt)
306
320
333
(1)
UNIT
VRMS
Based on parameter values in Electrical Characteristics table and calculated assuming 9.3 MΩ resistors in AC1 and AC2 lines. The
relative levels of these action levels track each other.
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7.3.5 VBLK Sensing
VBLK is sensed through a potential divider with a resistance of 30 MΩ between the VBULK pin and VBLK. The
bottom resistor in the potential divider is 73.3 kΩ. The 30 MΩ resistor has to support the full VBLK voltage and it is
normal to split this resistance into three separate parts of 10 MΩ each. As noted in Sense Network Fault
Detection the UCC29950 will not start the power stages if it detects that VBLK is less than peak of VAC. Because
of the high impedance nature of the sensing network it is recommended to minimize the length of track between
the VBULK pin and the lowest resistor in the sensing chain.
7.3.6 AC Input UVLO and Brownout Protection
The UCC29950 provides full brownout protection and will not react to single-cycle AC line dropouts. While the
PFC stage is running the controller checks each AC line half-cycle. A valid AC line input is detected if the peak
voltage during an AC line half-cycle is greater than the brownout level (equivalent to 70 VRMS). The AC_DET
output goes high if no valid AC line input is detected for a period greater than 32 ms and both the PFC and LLC
stages stop operating 100 ms later.
NOTE
The LLC stage always stops immediately if VBULK falls below VBULK(llc_stop).
VAC_DET
VAC
AC_DET
t30 mst
PFC_GD
GD1/GD2
Time
Figure 10. AC Line Dropout
VAC_DET
VAC
AC_DET
32 ms (typ)
100 ms
PFC_GD
GD1/GD2
Time
Figure 11. AC Line Disconnect
VAC_DET
VAC
AC_DET
32 ms (typ)
100 ms
PFC_GD
GD1/GD2
Time
Figure 12. AC Line Brownout
18
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7.3.7 Dither
The PFC stage switching frequency is stepped between three discrete frequencies at a rate of 333 Hz. The
frequencies are spaced at nominal 2-kHz intervals. The dither rate is selected to avoid harmonics of the major
AC line frequencies. Dither is effective in reducing the average EMI level and also reduces the quasi-peak levels
but to a lesser extent.
7.3.8 Active X-Cap Discharge
If the Active X-Cap discharge function is to be used, the drain of the start-up FET must be connected to the AC
side of the bridge rectifier, as shown in Figure 20. The X-Cap is discharged by bringing SUFG low to turn the
start-up FET on. The discharge path is then through the startup FET, via the SUFS pin and into CVCC.
NOTE
A Zener diode should be used to clamp VCC and prevent multiple X-Cap discharge
events from over charging the capacitor. This Zener diode should be 18V rated device in
Self-bias applications. A lower voltage Zener could be used in Aux bias applications,
providing that the Zener voltage is greater than the normal operating VCC rail voltage.
When the AC line is removed the UCC29950 detects that the zero voltage crossings on VAC have ceased. If the
PFC stage is running at that time then the X-Cap is discharged through the switching action of the PFC stage
and no further action is needed. If the PFC stage is not running at the time of disconnection, perhaps because
MD_SEL/PS_ON is held low or VBULK is > VBULK(reg) , then SUFG is set high if VCX-Cap (the voltage on the XCap) is greater than 42 V and the X-Cap is discharged. If VCX-Cap is < 42 V then it is regarded as being at a safe
level, discharge is not needed and SUFG is not set high. The X-Cap is always discharged within the 1 s allowed
by the safety standards but there may be up to 300 ms delay or latency in SUFG operation if the controller is
operating in burst mode, for example at light loads. The UCC29950 makes the decision to set SUFG high based
on the voltage on the X-Cap at the end of this latency period.
7.3.9 LLC Stage Soft Start
The LLC stage soft-start ramps the LLC gate drive frequency from min period (1/LLCF(max) ) to max period
(1/LLCF(min) ) over a 100-ms interval. The ramp is terminated when the voltage at the FB pin is such that it would
command a higher frequency than the ramp. The first pulse from the GD1 output is half width.
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7.3.10 PFC Stage Current Sensing
The UCC29950 controls the average current in the PFC inductor. This means that the current sense signal at the
PFC_CS pin must represent the inductor current during the full PFC switching cycle. That is when the MOSFET
is ON and also when the MOSFET is OFF. This is achieved by putting the current sensing resistor, RCS(pfc), in the
position shown in Figure 13 and Figure 34.
NOTE
The current sense signal, VCS_PFC, is negative going, so the signal goes more negative as
the inductor current increases.
The current sensing resistor is on the input current return path and inrush currents flow through it. These may
generate large voltage drops on the current sense resistor. These voltages may be higher than the negative
voltage rating on the PFC_CS pin. A resistor, recommended value = 1 kΩ, between the current sensing resistor
and the PFC_CS pin is used to avoid over stressing the device. Signal diodes may be necessary to provide
additional clamping. A small filter capacitor may be useful to further reduce the noise level at this pin but be
careful that this part does not significantly attenuate the ripple component of the current sense signal. These
components are shown in Figure 13.
The current drawn from the AC line is limited so that the peak voltage on the PFC_CS pin, ignoring PFC stage
switching ripple, does not exceed –225 mV, VTH(PFCCS(cav_max)), as shown in Figure 6.
There is a second current limit point at VPFCCS(max) and the peak voltage at the PFC_CS pin should not be
allowed to exceed this limit (–570 mV). The operation of this second current limit is explained later. The PFC
current sense resistor (RCS(pfc)) value needed can be calculated using Equation 59.
EMC Filter
VBLK
VAC
CBLK
RCS(pfc)
RCS(llc)
C1
RF(pfc)
RF(llc)
CF(pfc)
13
11
PFC_CS
LLC_CS
AGND
CF(llc)
AGND
Figure 13. Current Sensing Connections
20
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7.3.11 Input Power Limit
The UCC29950 has a true input power limit which limits the PFC stage power at a level which is independent of
the AC line voltage. This is more useful than a simple fixed input current limit where the power would be limited
at different levels depending on the AC line voltage. The power limit is set by the choice of RCS(pfc) according to
Equation 59.
7.3.12 PFC Stage Soft Start
When the power system is first connected, the bulk capacitor charges to the peak value of the AC line voltage.
The PFC stage soft-start process first calculates the current needed to charge the bulk capacitor from this initial
stage to the regulation setpoint (VBULK at VBULK(reg)) in a nominal 50 ms. This is an approximate calculation
based on a bulk capacitance of 0.8-µF per watt and varies if a larger or smaller capacitor is used. The PFC stage
is then started using this current limit value.
7.3.13 Hybrid PFC Control Loop
The UCC29950 controls a continuous-conduction mode PFC stage by using a novel method combining average
current-mode control with peak-current sensing. Among other advantages, this method eliminates the peak-mode
line current distortions due to a varying peak-to-average current ratio. The average current is used to control the
average value of the PFC inductor current and the peak current is used to terminate each PWM cycle and
provide high bandwidth, cycle-by-cycle current control or limiting. Good power factor is achieved by forcing the
average input current to follow a demand signal that is derived from the AC line voltage.
Traditional current-mode control systems require resistor and capacitor compensation components to shape the
system response. It is difficult to integrate these components into a semiconductor chip and external parts must
be used. The UCC29950 avoids the need for external compensation networks by implementing the average
portion of the control loop digitally. The entire outer-voltage control loop is digital and the required slow response
is easily achieved without the need for external parts. This mixed signal approach uses digital methods for lowfrequency compensation and analog op-amps and comparators for the actual PWM duty-cycle generation.
The input AC line voltage is sensed differentially through the AC1 and AC2 pins, as shown in Figure 14.
Differential sensing allows more accurate measurement of the AC line voltage over the entire input power range,
including no load, than single ended sensing. The output of the voltage loop is multiplied by the instantaneous
line voltage, |VAC1 - VAC2|, to give an average current demand signal, IAV(dem), for the current loop. The IAV(dem),
the voltage loop and |VAC1 - VAC2| signals are all implemented digitally. The voltage loop provides correct
compensation over the expected range of bulk capacitor values, based on a capacitance to power ratio between
0.5 μF W-1 and 2.4 μF W-1. This eliminates the need for external compensation components and simplifies the
design task.
The current-demand signal normally has a rectified sinusoidal shape. The current-loop output is used to program
a duty cycle which is then sent to the PFC_GD pin through a driver. The minimum duty cycle is 0% at which
point the PFG_GD output is kept low for the entire switching cycle. The maximum duty cycle for the PFC_GD
output is at least 92%.
NOTE
The maximum duty cycle is imposed by the PWM block independently of the input from
the current loop and does not depend on inputs from the current loop or elsewhere.
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10
AC1
AC2
VBULK
| VAC1 ± VAC2 |
9
IAV(dem)
Current
Loop
16
PFC_GD
Voltage
Loop
8
PFC
Stop
VREF
PFC_CS
PWM
13
Figure 14. PFC Control Loop
The inner current loop uses a hybrid mixed signal control method as shown in Figure 15. The IAV(dem) signal
(digital average current demand) is converted to an analog form and summed with the sensed current signal ICS
by the unity gain inverting amplifier, A1. The current sensed is the total inductor current which means that the
sensing resistor must be placed in the negative return as shown in Figure 13. The IAV(dem) signal is positive going,
greater IAV(dem) values commands larger currents. The signal at the PFC_CS pin is negative going so that larger
currents give a more negative signal level. The action of the control loop is to keep the inverting and noninverting inputs to A1 at the same level (450 mV). The output of the A1 amplifier contains both average and
peak-inductor current information. The average level at the A1 amplifier output is extracted by the ADC and
digital filter shown in the block called A2 in Figure 15. This average level is then subtracted from the fixed PWM
ramp coming from the waveform generator. The result is converted into an analog signal by the DAC and sent to
the inverting input of the fast analog PWM Comparator. The comparator ramp has an offset which is a function of
the digital-filter output. This offset value moves up and down in response to changes at the A1 output. The
comparator ramp at the inverting input is negative going and that at the non-inverting input is positive going. This
increases the noise immunity of the comparator making an incorrect, early termination of the cycle is less likely.
22
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If the IAV(dem) signal increases, for example in response to an AC line voltage or load change then the average
output of the A1 amplifier initially decreases by the same amount. The PWM duty cycle, and inductor current, will
then increase because as VA1(out) moves negative, it takes longer for the two signals at the comparator inputs to
intersect and terminate the cycle. The digital-filter output also increases in response to the change in VA1(out)
according to its frequency response characteristic and the average value of the comparator ramp moves
negative. This tends to reduce the PWM duty cycle. Eventually, as the PFC inductor current increases the VA1(out)
signal returns to its equilibrium point at 450 mV. The digital filter dynamically adjusts its output up or down so as
to keep the average value of the comparator ramp at the level where VA1(out) is kept at 450 mV. The overall effect
is that a unipolar sinusoidal demand signal is translated into a unipolar sinusoidal PFC inductor current.
Digital
Waveform
Generator
PWM Ramp
+
DAC
-
A2
Digital Filter
IAVG(dem)
(Analog)
IAV(dem)
DAC
ADC
Comparator
Ramp
B
PFC_CS
13
VA1(out)
ICS
+
A1
A
450 mV
Unity Gain Inverting
Analog Amplifier
+
PWM
Comparator
+
850 mV
OCP
Comparator
Figure 15. UCC29950 Hybrid Current-Mode Control
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7.3.14 PFC Stage Second Current Limit
An individual PFC switching cycle is normally terminated by the PWM Comparator. If for some reason the PWM
Comparator fails or has stopped operating then there is a second comparator monitoring the output of the A1
amplifier (OCP Comparator in Figure 15). The OCP comparator turns the PFC MOSFET off and provides an
additional protection function for the devices in the power train.
If the output of A1 reaches 850 mV then the OCP comparator trips. Two actions follow:
1. The existing PWM cycle is terminated immediately.
2. Both the PFC and LLC stages shut down for 1 s followed by a re-start.
7.3.15 PFC Inductor and Bulk Capacitor Recommendations
The CCM Boost converter current-mode control loop is insensitive to PFC inductor value and can operate over a
wide range of inductance values. The inductor value in a given application is a trade off between ripple current,
physical size, losses, cost and several other parameters. For example, in Detailed Design Procedure for the PFC
stage a value of 600 µH for a 300-W application is chosen.
The hybrid control loop has been designed to be stable for any bulk capacitance between 0.5 µF W-1 and 2.4 µF
W-1. For a 300-W application, this would allow the use of a bulk capacitance between 150 µF and 720 µF. These
limits on PFC inductance and bulk capacitance are conservative.
7.3.16 PFC Stage Over Voltage Protection
In normal operation the PFC stage control loop in the UCC29950 regulates the PFC stage output voltage (VBLK)
such that the voltage at the VBULK pin is held at VBULK(reg). If the recommended sensing network is used then
this corresponds to 385 V on the bulk capacitor. If the voltage at the VBULK pin exceeds VBULK(ovp) the PFC
stage is stopped immediately. It restarts once VBULK falls back to the VBULK(reg) level. The OVP level
corresponds to 450 V at the PFC bulk capacitor. This protects the PFC stage against over stresses due to rapid
increases in VBLK, occurring if an AC line surge event were to happen. The LLC stage continues to operate in
order to load and discharge the bulk capacitor. The OVP response is immediate, of the order of 100 µs, and is
more rapid than the response of the normal PFC voltage control loop.
VBULK(ovp)
VBULK(reg)
PFC_GD
GD1/GD2
Time
Figure 16. VBULK Over-Voltage Protection
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7.3.17 LLC Stage Control
The UCC29950 has three pins dedicated to the control of an LLC power stage, the two gate drives GD1 and
GD2, and the feedback pin, FB. If the controller is operating in Aux Bias Mode then the MD_SEL/PS_ON pin
may also be used to turn the LLC stage on or off. The UCC29950 includes an on chip Voltage to Frequency
Converter (VCO) which converts the voltage on the FB pin into a square wave at the desired frequency
according to the graph in Figure 1. The basic response time of the voltage to frequency conversion process is
typically less than 40 µs. This means that the overall response of the LLC power system is dominated by the
other components in the loop, for example, the opto-coupler and error amplifier on the output , rather than by the
UCC29950. Inverted and non-inverted versions of the square wave are produced and a dead time is added. The
dead time added is a function of the frequency being generated according to the graph in Figure 2. The signal is
then passed to the on-chip drivers connected at the GD1 and GD2 pins. The duty cycles of the GD1 and GD2
signals are highly symmetrical, typically they match to better than 0.1%.
The first and last LLC gate drive pulses are normally half width and appear on GD1 and GD2 respectively. The
half width pulses reduce any DC flux in the transformer at start up or shutdown. If the LLC_OCP3 level is
exceeded then the final pulse is of normal width.
GD1
GD2
Time
Figure 17. LLC GD1 and GD2 Start and Stop
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7.3.18 Driver Output Stages and Characteristic
The output stage pull-up features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The
function of the N-Channel MOSFET is to provide an increased sourcing current enabling fast turn-on, as it
delivers the highest peak-source current during the Miller plateau region of the power-switch turn-on transition,
when the power switch drain or collector voltage experiences high dV/dt. The N-Channel device can pull the
driver output to within one threshold voltage drop of the V+ rail. The P-Channel device can pull the driver output
all the way to V+.
The effective resistance of the UCC29950 pull-up stage during the turn-on instant is therefore lowest during the
time when the highest current is needed. The pull-down structure in UCC29950 is composed of an N-Channel
MOSFET which can pull the output all the way to GND.
The structure in Figure 18 is used in the output circuit of the low power driver used to output the AC_DET signal.
It has the same pull up characteristics, but at an impedance level more suitable for driving a signal level load
such as an optocoupler LED.
V+
ROH
Output
ROL
Input
Figure 18. Driver Output Stage (simplified)
7.3.19 LLC Stage Dead Time Profile
The UCC29950 programs a dead time into the LLC gate drive outputs (GD1 and GD2) which follows the profile
shown in Figure 2. The dead time is longest at high frequencies because the currents in the resonant tank circuit
are less and so the stray capacitances at the switched node take longer to swing from one rail to the other. At
low frequencies the opposite is true, the currents in the resonant tank are greater and the switched node swings
more quickly.
7.3.20 LLC Stage Current Sensing
The UCC29950 uses primary-side current sensing to monitor the output current. This has the advantage that
current limiting can be implemented without having to bring a current limit signal across the primary-to-secondary
isolation barrier. Also, assuming that the output voltage of the LLC stage is lower than the input, the currents in
the primary circuit are lower than those in the secondary. This allows a larger value of sensing resistor to be
used without incurring excessive power dissipation. One side effect of sensing on the transformer primary is that
the sensed current includes start up charging currents onto the LLC stage output capacitance. The three level
OCP feature allows this charging current to flow without tripping a fault. Even if the current sensing were done on
the secondary side and outboard of the LLC stage output capacitance there may still be additional, off-board
capacitance whose charging current does flow in the sensing resistor.
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7.3.21 LLC Three Level Over-Current Protection
The UCC29950 uses the LLC stage input current to represent the output current. The value of the LLC current
sense resistor that should be used is given by Equation 36.
Three levels of overcurrent protection as shown in Figure 19, are provided to allow the UCC29950 to react in a
flexible manner to an over current event. VCS(ocp1) and VCS(ocp2) faults are triggered after a short delay. VCS(ocp3)
level faults are acted on immediately.
Table 4. LLC Stage Over-Current Protection Levels
OCP PARAMETER
VCS(ocp1)
DESCRIPTION
VALUE
First overload detection level. If this threshold is exceeded for tOCP1 then both 133% of VCS(llc_max).
the PFC and LLC stages will shut-down. Restart with a normal soft-start
Typically 400 mV
sequence after tLONG(fault) (1 s typ).
tOCP1
VCS(ocp2)
52 ms
Second overload detection level. If this threshold is exceeded for tOCP2 then
both the PFC and LLC stages will shut-down. Restart with a normal soft start
sequence after tLONG(fault) (1 s typ).
tOCP2
200% of VCS(llc_max).
Typically 600 mV
10 ms
VCS(ocp3)
Third overload detection level. If this threshold is exceeded for tOCP3 then
both the PFC and LLC stages will shut-down. Restart with a normal soft start
sequence after tLONG(fault) (1 s typ).
300% of VCS(llc_max).
Typically 900 mV
tOCP3
This is the time the UCC29950 takes to react to a level three overload
voltage at the LLC_CS pin. Board level filtering can reduce the signal rise
time at the pin and significantly increase the overall reaction time.
VAC(high_rising)
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7.4 Device Functional Modes
7.4.1 Mode Selection
The UCC29950 may be operated in one of two modes. In Aux Bias Mode VCC is supplied from an external
source. A small, separate fly-back supply is normally used for this purpose. Aux Bias Mode allows the user to
turn both the LLC and PFC stages off or to run only the PFC stage or to run both PFC and LLC stages together
and to run the system at no load if desired. In Self Bias Mode the VCC rail is powered from a small auxiliary
winding on the LLC transformer and ON/OFF control of the PFC and LLC stages is not possible in Self Bias
Mode.
7.4.2 Start-Up in Aux Bias Mode
A small external PSU is used to supply VCC in Aux Bias Mode. A 12-V 50-mA supply is normally sufficient but
this does depend on system level factors such as the gate-driver circuitry used, the load presented by the
switching MOSFETs and other factors.
MD_SEL/PS_ON
LLC_CS
AC_DET
11
AGND
8
GND
9 AC2
16
PFC_GD
10 AC1
PFC_CS
13
VBULK
CX-cap
VAC
1
6
15
7
UCC29950
4 SUFG
5 SUFS
GD1 14
GD2 2
FB 12
VCC
VCC 3
CVCC
External
Control
Signal
Figure 20. External Control Signal
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Device Functional Modes (continued)
Aux Bias Mode is selected if the MD_SEL/PS_ON pin is kept lower than VMODE(selsb) for a time greater than
TMODE(sel_read) after VCC passes the VCCSTART threshold. After this time has passed, the MD_SEL/PS_ON pin
may be used to turn on the PFC stage alone by setting this pin to a voltage between the VPS_ONPFC_RUN and
VPS_ONLLCPFC_RUN levels. The PFC and LLC stages may both be turned on by setting the MD_SEL/PS_ON pin to
a voltage greater than VPS_ONLLCPFC_RUN. Refer to the Electrical Characteristics table for the related tolerances on
these thresholds.
The MD_SEL/PS_ON pin may be driven from an active source such as a comparator or digital output (with
appropriate level shifting, provided by an optocoupler for example). A simple RC network may also be used if an
active source is not available. Connect a capacitor from MD_SEL/PS_ON to AGND and a resistor from
MD_SEL/PS_ON to VCC. The RC time constant should be chosen so that the voltage at the MD_SEL/PS_ON
pin is less than VMODE_SELSB 10 ms after VCC increases past VCC(start). Normally an RC time constant of 100ms
will be satisfactory. The slow rise of the MD_SEL/PS_ON signal between the VPS_ONPFC_RUN and
VPS_ONLLCPFC_RUN levels increases overall start-up time by a few 100 ms.
The normal sequence in a system is that VAC is applied, MD_SEL/PS_ON is held low, VCC comes up and
MD_SEL/PS_ON is then used to turn the PFC/LLC stages on as shown in Figure 21.
This sequence applies whether or not the X-Cap discharge function is being used.
Typical start-up times in Aux Bias Mode are in the range 150 ms to 250 ms after MD_SEL/PS_ON is brought
high.
VBULK_LLC_START
VC_Bulk
VAC
VCC
tTMODE_SEL_READ
MD_SEL/
PS_ON
VPS_ONLLCPFC_RUN
VPS_ONPFC_RUN
TPFC_PS_ON_DELAY
PFC_GD
tLLC_Soft_Start_Delayt
GD1/GD2
Time
Figure 21. Typical Aux Bias Turn-On Sequence
(both PFC and LLC stages are turned on simultaneously by pulling MD_SEL/PS_ON above
VPS_ONLLCPFC_RUN )
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Device Functional Modes (continued)
7.4.3 Start-Up Operation in Self-Bias Mode
In Self Bias Mode, the MD_SEL/PS_ON pin should be tied to VCC as shown. The start-up FET is a normally on
depletion mode device, a BSS126 for example. CVCC is charged via the start-up FET and the internal currentlimiting block. Initial charging of CVCC happens automatically even though VCC is below VCCSTART. When VCC
reaches VCCSTART the SUFG pin goes low, which turns the start-up FET off. If the MD_SEL/PS_ON pin is tied to
VCC, the UCC29950 enters Self Bias Mode. SUFG goes high again to turn the start-up FET on again and allow
CVCC to charge further. When CVCC has been charged to VCCSB(start) (typically 16.2 V) the start-up FET is turned
off and providing that the current into the AC1 and AC2 pins is greater than IAC(low_rising) and that the sensed VBLK
voltage is greater than peak of AC line the PFC stage is started. As noted earlier, an 18-V zener diode should be
used to clamp the voltage on CVCC. The switching operation of the PFC and LLC stage is maintained as long as
CVCC is above VCCSB(stop). Equation 2 allows the user to select the value of CVCC.
AC_DET
MD_SEL/PS_ON
11
AGND
8
GND
9 AC2
Start Up
FET
16
LLC_CS
10 AC1
PFC_CS
13
VBULK
CX-Cap
PFC_GD
VAC
1
6
15
7
UCC29950
4 SUFG
5 SUFS
Bias Winding on
LLC transformer
GD2 2
GD1 14
FB 12
VCC 3
CVCC
Figure 22. Self Bias Mode
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Device Functional Modes (continued)
The start-up time in Self Bias Mode depends strongly on the current available for charging and on the
capacitance on the VCC rail and. A first pass estimate of start-up time can be made using:
P5$(OP=NP ) N
%8%% × VCC5$ (OP=NP
+57(5
)
+ 200 ms
(2)
For typical values, assuming CVCC is 200 µF, tSTART is therefore 1.8 s.
VBULK(LLC(start))
VC(bulk)
VAC
VCCSB(start)
VCC
VCCSB(UVLO(stop))
VCCSTART
SUFG
TMODE_SEL_READ
PFC_GD
GD1/GD2
Time
Figure 23. Typical Self Bias Turn-On Sequence
7.4.4 Bias Rail UVLO
The UCC29950 continuously monitors the voltage at its VCC pin. It stops both the PFC and LLC stages if VCC
falls below VCCAB(uvlo_stop) or VCCSB(uvlo_stop), depending on whether it is operating in Aux Bias or Self Bias
Modes respectively. In Aux Bias Mode, the device simply waits for VCC to recover to a voltage greater than
VCCAB(uvlo_stop). At which point it restarts. If it is operating in Self Bias Mode it sets SUFG HI to turn the start-up
FET on. The current through the start-up FET then charges the capacitance on the VCC rail up to VCCSB(start) at
which point the system tries to restart as described earlier.
7.4.5 LLC Stage MOSFET Drive
UCC29950 includes two high-power drivers that are capable of directly driving both MOSFETs in the half bridge
LLC circuit through a suitable gate drive transformer as shown in Figure 24. Alternatively an external driver
device, with its own high-side channel, can be used to interface between UCC29950 and half bridge MOSFETs
as shown in Figure 25.
If a gate drive transformer is used then GD1 should be used to drive the high-side MOSFET and GD2 used to
drive the low-side MOSFET. If a gate driver device is used then GD1 should be used to drive the low-side
MOSFET and GD2 used to drive the high-side MOSFET. TI recommends the UCC22714 as a suitable gate
driver device. The first and last LLC gate drive pulses are normally half width and appear on GD1 and GD2
respectively, see Figure 17.
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Device Functional Modes (continued)
VIN
Q1
D1
0.5 CR
NP:NS:NS
+
CO
RL
VSQ
GD1
LR
Q2
LM
VOUT
GD2
D2
0.5 CR
RCS_LLC
VCS_LLC
Figure 24. LLC MOSFET Gate Drive Using a Gate Drive Transformer (simplified)
DB
VCC
VIN
VCC HB
12V
(typ)
GD2
HI
CB
HO
Q1
D1
0.5 CR
NP:NS:NS
+
HS
CO
RL
VSQ
LR
GD1
LI
LO
LM
VOUT
Q2
D2
COM
GND
0.5 CR
RCS_LLC
VCS_LLC
Figure 25. LLC MOSFET Gate Drive Using a Driver Device (simplified)
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Device Functional Modes (continued)
7.4.6 Gate Drive Transformer
Gate driver transformers are robust and less susceptible to noise than gate drive devices but will also be larger
than a solution using a gate driver device.
The GD1 and GD2 outputs from the UCC29950 are symmetrical, with 180˚ phase shift and a duty cycle less than
50%. If the gate drive transformer is driven as shown in Figure 24, then the waveform at its primary has no DC
component. The gate-drive transformer must be able to support the maximum V sec product based on the GD1
and GD2 signal at LLC FMIN. In steady state conditions, the duty cycles of GD1 and GD2 outputs are extremely
well matched, typically within 0.1% of each other. When using a gate-drive transformer, the GD1 signal should be
used to driver the high-side MOSFET and the GD2 signal used to drive the low-side MOSFET, as shown in
Figure 24. The initial half-width pulse on GD1 and final half-width pulse on GD2 ensures that there is no DC flux
imbalance on either the gate-drive transformer or in the main transformer see Figure 17.
The gate-drive transformer used to directly drive the LLC power MOSFETs should have a low common-mode
capacitance. The common-mode current that flows from the upper-gate winding, back through the UCC29950
drivers, during bridge-switching transitions must return to the power circuit via the UCC29950 GND pin. Voltage
disturbance on the GND pins during LLC bridge transitions may lead to audible interaction between the PFC and
LLC power stages.
Placing a screen between the controller winding and gate-drive windings is one way to reduce the commonmode capacitance of the transformer. This screen should be connected to the source of the lower half-bridge
MOSFET (Q2).
The gate-drive transformer should drive both the low-side and high-side MOSFETs as shown in Figure 24. This
ensures that propagation delays through the transformer are matched and the symmetry of the dead time is
maintained.
7.4.7 Gate Drive Device
A gate-driver device solution is less bulky than a gate-drive transformer and may be easier to design and layout.
The capacitance from output to input is very low which means that interference from common-mode currents will
not normally occur. In both Aux Bias and Self Bias Modes, the HO and LO outputs must make a clean transition
between their active state (where they obey the HI and LI inputs) and their UVLO state (where they are latched
low). Additionally, if operating in Aux Bias Mode it is very important to make sure that the UVLO level of the gatedriver device is less than that of the UCC29950 (VCCAB_UVLO(stop)). This ensures that the GD1 and GD2 signals
are always passed on to the switching MOSFETs and that the UCC29950 maintains control of the LLC power
train. It also ensures, if there is a UVLO condition on the bias rail, that the UCC29950 can enter and exit the
UVLO condition correctly with a proper soft start during the recovery phase. In Self Bias Mode, it is not
necessary that the driver UVLO is lower than that of the UCC29950, if the MOSFET gate drives stop for any
reason then the bias always collapse to the UCC29950 VCCSB_UVLO(stop) level, followed by a full restart as
described in LLC Stage Soft Start.
High-side driver devices use a bootstrap capacitor, CB in Figure 25, to supply the current to charge the gate of
the high side MOSFET. This capacitor must first be charged to the driver high-side UVLO voltage before any HO
pulses are delivered to the high-side MOSFET gate. CB is charged during the first few LO pulses. Once the
voltage across CB reaches the high side driver UVLO level there is normally a short delay, 20 µs, before HO
pulses appear. The current in the circuit during the first few switching cycles, when both high-side and low-side
MOSFETs are being driven, will be higher than normal. The circuit designer must ensure that the LLC powercircuit components are rated for these stresses.
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Device Functional Modes (continued)
7.4.8 Comparison
Users who employ a gate-drive transformer benefit from special features in UCC29950 to ensure a much
smoother start-up transition of the LLC converter. This allows magnetics with a lower peak-current rating to be
used safely. It is important to use a gate-drive transformer with a low common-mode capacitance.
If an external high-side driver is used then the smooth start-up feature is effectively disabled and the designer
must ensure that the LLC magnetics are rated to cope with the resulting increased peak current during start-up.
Figure 26 compares the LLC resonant current waveform observed during the start-up transient. Both traces are
triggered on GD1 output at the same point. The lower trace is observed when directly driving the LLC bridge
MOSFETs via a gate drive transformer. The upper trace is observed when driving the LLC bridge MOSFETs via
an external gate device driver. Vertical scale is 2 A/div. Horizontal scale is 10 µs/div.
Figure 26. Typical LLC Transformer Primary Current During Startup
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8 Application and Implementation
8.1 Application Information
The UCC29950 device is a highly-integrated combo controller. It is designed for applications requiring a CCM
boost PFC input stage followed by an LLC output / isolation stage. The PFC loop is internally compensated and
requires no external loop-compensation components. EMI filtering is simplified because the PFC stage operates
at a fixed frequency with dither. A three level output overload protection current/time profile is included.
8.2 Typical Application
S2
TP15
PSON
A typical application for this device would be in a 300-W, universal input isolated PSU with a 24-V (12.5-A)
output.
AGND
1
PGND
0
R48
C39
0.1μF
R55
AGND
D19
1000pF
C41
LLC_RCS
D18
470
R53
R52
470
PFCCS
R51
3.09Meg
3.09Meg
3.09Meg
R50
2.21k
TP16
AGND
470pF
470pF
AGND
AGND
C38
R49
10.0Meg
R43
R42
BULK
10.0Meg
AC1
R44
10.0Meg
R45
75.0k
R46
3.3Meg
C36
470pF
C37
3.09Meg
3.09Meg
3.09Meg
R38
R40
R39
D16
AC2
AGND
C40
0.1μF
R56
3.32k
TP17
FB
UCC29950D
AGND
GND
FB
LLC_CS
PFC_CS
11
13
12
6
TP14
AGND
TP10
PFCGD
GD2
16
2
GD2
PFC_GD
AC1
AC2
VBULK
8
10
9
PSON
Q4
0
R37
0
R36
0
D15
AC1
AGND
R54
100k
R47
100k
VCC
D17
Green
R41
10.0k
GD1
TP12
TP13
14
GD1
MD_SEL/PS_ON
SUFS
5
7
15
4
SUFG
AGND
AC_DET
PGND
U6
3
VCC
C35
10μF
C33
0.1μF
C34
10μF
TP9
4
1
VCC
6
3
375Vdc
S1
4
1
R35
6
3
Figure 27. Controller Application
36
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J1
GD1
GD2
TP21
NEUTRAL
LINE
VCC
R57
1.00
C27
0.1μF
C25
1μF
V1
VCC
C45
100pF
51.1
R11
250V 8A
PGND
C44
100pF
51.1
R13
TP4
3
2
1
C26
220μF
TP5
8
9
10
14
2
1
4
7
C16
1μF
18V
D11
D20
UCC27714D
NC
NC
NC
NC
LI
HI
NC/EN
VDD
U2
2.2
R58
AC2
C1
0.47μF
D6
PFCCS
LO
HS
HO
HB
PGND
3
5
6
11
12
13
TP28
-
R15
1.10M
R14
10.0M
VSS
COM
C2
0.47μF
5 ohm
t°
RT1
~
D2
TP3
+
C48
0.01μF
C12
0.1μF
R4
0.1
~
90VAC to 264VAC
L1
2.2mH
R5
0.1
C47
10μF
6
1
3
2
22
NC
IN
EN
DELAY
R18
10.0k
GND EP
OUT
PG
FB
U7
R12
10.0k
R60
R59
100k
PGND
C9
1μF
1.0
7
5
8
LLC_RCS
AGND
D10
C43
10μF
Q3
AOW25S65
C13
0.012μF
H2 HEATSINK Q1, Q2
PGND
J4
C42
0.1μF
VCC
1
2
3
PGND
1
D12
J5
3
1
6
5
2
D13
1
2
3
HS1
D3
C3D04060A
TP8
T1
FB
19
20
15
16
18
17
14
13
C10
3
1
3
1
AGND
R34
NF
TP22
TP20
2
2
H3 HEATSINK D4, D6
3
4
1
2
3
ACPL-217-56AE
U4
2
1
2
1
NF
S3
C22
1000μF
SEC_0V
C21
1000μF
R21
NF
R20
NF
C32
0.1μF
C20
330μF
R30
0
C31
NF
BZX384-C12,115
12V
D14
C24
1000μF
LLC_RCS
C23
1000μF
1.20
R9
1.20
R8
1.20
R7
47μF
C7
PFC BULK RTN
+PFC BULK
J2 NOMINAL VBULK: 390VDC
BULK
TP33
1
2
3
385V to 450VDC
TP23
ACPL-217-56AE
R28
NF
VCC
3
4
U3
R23
1.20k
VCC
TP32
C5
0.1μF
TP31
HS3
SEC_0V
C4
0.1μF
STPS40L45CT
D8
D7
SEC_0V
C6
270μF
HIGH VOLTAGE
1000pF
PGND
H1 HEATSINK D2, D3, Q1
Q1
TP2
C19
D4
TP18
L3
R62
10.0k
TP26
L2
D1
0.016μF
C15
0.047μF
C11
C14
0.012μF
C8
0.1μF
R2
3.3 R3
0.016μF
HS2
3
2
1
1
2
3
TPS7A1601DGNT
NF
OUTL
OUTH
VDD
UCC27511DBVR
GND
IN-
IN+
U1
PFCGD
Q2
AOW25S65
Net-Tie
4
5
6
R1
10.0
NT1
BULK
TP24
TP25
AGND
R17
NF
D9
22
C3
0.33μF
R6
0.1
R10
NF
D5
AC1
90VAC to 264VAC
4
HIGH VOLTAGE
9
2
3
F1
1
4
3
6
TP1
1
Product Folder Links: UCC29950
C29
NF
U5
TL431AIDBZR
NF
C30
TP7
TP6
0.047μF
R29
R25
10.0k
R22
5.10k
R16
NF
2
Copyright © 2014–2015, Texas Instruments Incorporated
3
R32
NF
R26
36k
R24
49.9
C17
330μF
+VOUT
R31
0
R27
NF
10K
R33
C28
NF
SEC_0V
TP27
C18
1μF
TP19
1
2
3
4
VOUT RTN
+VOUT
TP29
TP30
J3
+VOUT
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UCC29950
Typical Application (continued)
Figure 28. Power Stage Application
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Typical Application (continued)
8.2.1 Design Requirements
The typical application should meet the following requirements:
Table 5. Typical Application Requirements
PARAMETER
REQUIREMENT
VAC
Input voltage
fLINE
Line frequency
VBLK
Nominal PFC stage output voltage
385 V
VBLK(ripple)
Max VBLK ripple (2 x Line Frequency)
30 VPP
VBLK(max)
Maximum PFC stage output voltage, VBLK + ½ VBLK(ripple)
400 V
VBLK(min)
Minimum PFC stage output voltage, VBLK – ½ VBLK(ripple)
370 V
VBLK(hu)
Minimum PFC stage output voltage at end of hold-up time
300 V
VOUT
Output voltage
VOUT(min)
Min output voltage
21.6 V (VOUT – 10%)
VOUT(max)
Max output voltage
26.4 V (VOUT +10%)
IOUT
Full load output current
12.5 A
VOUT(pk_pk)
Output voltage ripple
300 mV
POUT
Output power
300 W
η
Efficiency
PF
Power factor
0.99
tH
Hold-up time
20 ms
fPFC
PFC stage switching frequency
98 kHz
38
85 VAC to 264 VAC
47 Hz to 63 Hz
24 VDC
90 %
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8.2.2 Detailed Design Procedure
8.2.2.1 LLC Stage
Start the design by deciding on the component values in the LLC power train and then move to the PFC stage.
The LLC stage design procedure outlined here follows the one given in the TI publication “Designing an LLC
Resonant Half-Bridge Power Converter” which is available at http://www.ti.com/lit/ml/slup263/slup263.pdf. The
document contains a full explanation of the origin of each of the equations used. The equations given below are
based on the First Harmonic Approximation (FHA) method commonly used to analyze the LLC topology. This
method gives a good starting point for any design, but a final design requires an iterative approach combining the
FHA results, circuit simulation and hardware testing. An alternative design approach is given in TI Application
Note, LLC Design for UCC29950, Texas Instruments Literature Number SLUA733.
One of the reasons that the LLC topology is so popular is that it can achieve Zero Voltage Switching (ZVS) over
a wide range of operating conditions. ZVS is important because it reduces switching losses in the power devices.
The schematic for a basic LLC is shown in Figure 29.
Q1
+
±
CR
VIN
LR
NP:NS:NS
D1
+
VSQ
CO
RL
VOUT
Q2
LM
-
RCS(llc)
D2
VCS(llc)
Figure 29. Basic LLC Schematic
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In this system the input VIN is the output of the PFC stage. VIN is a DC voltage with some AC ripple at twice the
line frequency. The two switches Q1 and Q2 are driven in anti-phase to generate a high-frequency square wave
input signal VSQ at the input to the resonant network formed by CR, LR and LM. RCS(llc) is a current sensing
resistor. Current flows in RCS(llc) only during the on time of Q1 in this single ended version of the LLC topology.
This has two effects.
1. There is a significant voltage ripple on the current sense signal as Q1 and Q2 are switched.
2. Fault currents in Q2 are measured indirectly by their effect on currents in Q1.
The modified LLC topology shown in Figure 33 eliminates these disadvantages.
The resistor RL loads this circuit through the transformer turns ratio and the peak gain is therefore a function of
load, as shown in Figure 30. At no load, RL is very high and its influence may be neglected and circuit has a
resonance at:
BL =
1
2è¥(.4 + ./ )%4
(3)
At the other extreme, RL is zero and it effectively shorts the transformer magnetizing inductance LM. The
resonant frequency under this condition is:
1
B0 =
2è¥.4 %4
(4)
This means that as the load changes from no load to short circuit the peak-gain frequency (fC0) moves between
these two values so that:
BL Q B%0 Q B0
(5)
Output voltage regulation is achieved by changing the switching frequency of the LLC stage. If VIN increases the
LLC stage gain must reduce in order to keep VOUT unchanged. The gain is reduced by increasing the switching
frequency as can be seen in Figure 30. If VIN reduces, then the gain must be increased and this is done by
reducing the switching frequency. The frequency must remain above the resonant frequency fC0 to maintain zero
voltage switching and to avoid control law reversal. This is especially important in a short circuit condition where
the control loop would try to reduce the switching frequency and where simultaneously fC0 has increased to its
maximum at f0. Short circuit and overload protection are provided in the UCC29950 and are discussed in LLC
Stage Over-Current Protection, Current Sense Resistor below.
40
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8.2.2.2 LLC Switching Frequency
Selecting the nominal full-load switching frequency is relatively straightforward. Most EMI standards for
conducted emissions have a lower limit at 150 kHz. If the fundamental switching frequency is lower than this then
it does not appear in the EMI test scans which makes EMI filtering easier. Otherwise, if it is too low then the
magnetic components are larger than necessary and the efficiency benefits of ZVS are reduced. A switching
frequency of 120 kHz is a good compromise and is the one used in this design.
8.2.2.3 LLC Transformer Turns Ratio
The transformer turns ratio is given by the equation:
0=
8+0 /2
385 8/2
=
= 8.02 8
8176
24 8
(6)
VIN is the voltage on the bulk capacitor. This is regulated at 385 VDC if the resistor values suggested in Table 2
are used for the potential divider at the VBULK pin and ignoring diode forward voltage drops VOUT is 24 V.
8.2.2.4 LLC Stage Equivalent Load Resistance
This is the effective load resistance reflected through the transformer turns ratio. Re is determined at the full load
point.
4' =
8 02
64
24 8
4. = 8 ×
×
= 99.6 À
2
9.87 12.5 #
è
(7)
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8.2.2.5 LLC Gain Range
These parameters set the gain range required of the LLC stage. It is assumed a 0.5-V drop in the rectifier diodes
(Vf) and a further 0.5-V drop due to other losses (VLOSS).
8176 (IEJ )
(21.6 8 + 0.5 8)
=8×
= 0.88
8+0(I=T )
(400 8)W
W
2
2
8176 + VB + V.155
(24 8 + 0.5 8 + 0.5 8)
=0
=8×
= 1.33
8BLK(hu)
(300 8)W
W
2
2
/)(IEJ ) = 0
/)(I=T )
(8)
(9)
2
Q=0.00143
Q=0.29
Q=0.44
Q=0.48
1.9
1.8
1.7
1.6
1.5
Gain (Mg)
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0
0.5
1
1.5
2
2.5
Normalized Frequency (F N)
3
3.5
D001
Figure 30. LLC Stage Gain Curve
42
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8.2.2.6 Select LN and QE
From Figure 31 and Figure 32 select suitable LN and QE values to meet the MG_MIN and MG_MAX values from
Equation 8 and Equation 9.
LN is the primary inductance ratio and is given by:
.0 =
./
= 5.0
.4
(10)
QE is the quality factor of the resonant network.
3' =
¥.4 ¤%4
= 0.4
4'
(11)
Set LN = 5.0 and QE = 0.40 for this application. The LLC peak gain curves below show a maximum which is
greater than the maximum calculated by Equation 9.
3.6
7
Ln, 1.5
Ln, 2.0
Ln, 2.5
Ln, 3.0
Ln, 3.5
Ln, 4.0
Attainable Peak Gain, (M G(pk))
6
5.5
Ln, 5.0
Ln, 6.0
Ln, 7.0
Ln, 8.0
Ln, 9.0
3.3
3
Attainable Peak Gain, (M G(pk))
6.5
5
4.5
4
3.5
3
2.5
2.7
2.4
2.1
1.8
1.5
2
1.2
1.5
1
0.9
0
0.2
0.4
0.6
0.8
Quality Factor, (Q E)
1
1.2
1.4
0
D001
Figure 31. LLC Peak Gain Curves
0.2
0.4
0.6
0.8
Quality Factor, (Q E)
1
1.2
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D001
Figure 32. LLC Peak Gain Curves
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8.2.2.7 LLC No-Load Gain
The gain required at no load is:
/)(») =
.0
5.0
=
= 0.83
.0 + 1
5.0 + 1
(12)
Figure 30 shows that the design can achieve a minimum gain of 0.8 at the maximum frequency of the UCC29950
(350 kHz or 2.9 times the normalized f0 of 120 kHz).). If the gain is too high then the UCC29950 enters a burst
mode of operation to keep the output voltage under control.
8.2.2.8 Parameters of the LLC Resonant Circuit
The value of the resonant capacitor is given by the equation:
1
%4 =
2 è B59 4' 3'
=
1
= 33 J( 32 J(
2 è × 120 G*V × 99.6 À × 0.4
(13)
The resonant inductor is given by the equation:
.4 =
1
1
=
= 55 ä*
2
(2 è B59 ) %4
(2 è 120 G*V)2 × 32 J(
(14)
Rearranging Equation 10 gives a value for LM, the transformer magnetizing inductance:
./ = .0 .4 = 5.0 × 55 ä* = 275 ä*
(15)
44
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8.2.2.9 Verify the LLC Resonant Circuit Design
The series resonant frequency is given by Equation 4.
1
B0 =
1
=
2è¥.4 %4
2è¥55 ä* × 32 J(
= 120 G*V
(16)
The inductance ratio is given by:
.0 =
./
275 ä*
=
= 5.0
.4
55 ä*
(17)
The quality factor at full load is given by:
3' =
¥.4 ¤%4 ¥55 ä*¤32 J(
=
= 0.42
4'
99.6 À
(18)
This differs from the initial value of 0.45 because a rounded value for CR is used here and in the calculation of
LR.
The difference is not significant.
Figure 30 has been normalized to the series resonant frequency which is 120 kHz in this example.
At the minimum gain condition with minimum output voltage and maximum input voltage (MG(min)) the frequency
is 1.6 times f0 or fSW(max) = 192 kHz.
At the maximum gain condition with maximum output voltage and minimum input voltage (MG(max)) the frequency
is 0.6 times f0 or fSW(min) = 72 kHz.
8.2.2.10 LLC Primary-Side Currents
The primary-side RMS load current is given by:
è
+1' =
×
2¾2
1
è
1
× +1 =
× × 110% × 12.5 # = 1.91 #
0
8
2¾2
(19)
The RMS magnetizing current at minimum switching frequency is:
+/ =
8 × 24
2¾2 08176
2¾2
=
= 1.4 #
è ñ./
è 2è × 72 G*V × 275 ä*
(20)
The total current in the resonant circuit is then given by:
2
2
+4 = +92 = +%4 = §+/
+ +1'
= ¥(1.91 #)2 + (1.4 #)2 = 2.4 #
(21)
This current also flows in the transformer primary winding (IWP) and the resonant capacitor (ICR).
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8.2.2.11 LLC Secondary-Side Currents
The total secondary-side RMS current is the current referred from the primary side (IOE) to the secondary side.
+1'(5) = 0 +1' = 8 × 1.91 # = 15.3 #
(22)
The design uses a centre tapped secondary so that this current is shared equally between the two windings. The
current in each winding is then:
+95 =
¾2 +1'(5)
¾2 × 15.3 #
=
= 10.8 #
2
2
(23)
And the half-wave average current in the secondary windings is:
+5#8 =
¾2 +1'(5)
¾2 × 15.3 #
=
= 6.89 #
è
è
(24)
8.2.2.12 LLC Transformer
The transformer can be built or purchased according to these specifications:
• Turns Ratio (N): 8
• Primary Magnetizing Inductance: LM = 275 µH
• Primary Terminal Voltage: 450 VAC
• Primary Winding Rated Current: IWP = 2.4 A
• Secondary Terminal Voltage: 56 VAC
• Secondary Winding Rated Current: IWS = 10.8 A
• No Load Operating Frequency: fSW(max) = 192 kHz
• Full Load Operating Frequency: fSW(min) = 72 kHz
• Reinforced Insulation Barrier from Primary-to-Secondary to IEC60950
The minimum operating frequency during normal operation is that calculated above but during shutdown the LLC
can operate at at LLCFMIN .The magnetic components in the resonant circuit, the transformer and resonant
inductor, should be rated to operate at this lower frequency.
46
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8.2.2.13
SLUSC18A – SEPTEMBER 2014 – REVISED MARCH 2015
LLC Resonant Inductor
The AC voltage across the resonant inductor is given by its impedance times the current:
8.4 = ñ.4 +4 = 2è × 72 G*V × 55 µH × 2.4 A = 59.6 V 60 V
(25)
As
•
•
•
•
with the transformer, the resonant inductor can be built or specified according to these specifications:
Inductance: LR = 55 µH
Rated Current: IR = 2.4 A
Terminal AC Voltage: VLR = 60 V
Frequency Range: 72 kHz to 192 kHz.
The minimum operating frequency during normal operation is that calculated above but during shutdown the LLC
can operate at at LLCFMIN.The magnetic components in the resonant circuit, the transformer and resonant
inductor, should be rated to operate at this lower frequency.
8.2.2.14
Combining the LLC Resonant Inductor and Transformer
All physical transformers have a certain amount of leakage inductance. This inductance appears in series with
the magnetizing inductance. It degrades the performance of most topologies so designers usually try to minimize
it. In the LLC topology however, the leakage inductance appears in the same position as the Resonant Inductor
LR in Figure 29. This means that it is possible to design the transformer so that its leakage inductance replaces
the separate resonant inductor.
The Advantages:
• Fewer Magnetic Components
• Simpler PCB
• Lower Cost
The disadvantage to the transformer must be designed to have a relatively large and well controlled amount of
leakage inductance. The resonant inductance in the design above is about 20% of the total LR + LM. This is a
high ratio and careful control of the winding geometry and layering is needed to keep the leakage inductance
within acceptable limits.
The design procedure given above is valid irrespective of whether a design uses a separate resonant inductor
and transformer or uses a single high-leakage transformer.
8.2.2.15
LLC Resonant Capacitor
This capacitor carries the full-primary current at a high frequency. A low dissipation factor part is needed to
prevent overheating in the part.
The AC voltage across the resonant capacitor is given by its impedance times the current.
8%4 =
+%4
2.4 A
=
= 166 8
2è × 72 G*V × 32 J(
ñ%4
(26)
8+0(I=T ) 2
400 8 2
2
8%4(NIO ) = ¨l
p + 8%4
= ¨l
p + 166 8 2 = 260 8
2
2
(27)
And the corresponding peak voltage:
8%4(LA=G ) =
8+0(I=T )
400 8
+ ¾28%4 =
+ ¾2 × 260 8 = 434 8
2
2
(28)
The part selected must meet these specifications:
• Rated Current: ICR = 2.4 A
• AC Voltage: VCR(peak) = 434 V
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8.2.2.16 LLC Stage with Split Resonant Capacitor
It is possible to split the resonant capacitor in Figure 29 into two separate parts as shown below. The two circuits
are topologically equivalent but there are some differences in circuit stresses. The calculation of the resonant
circuit components is the same and the values of LR, LM and CR are unchanged. The two resonant capacitors are
each half the value of CR.
The major advantages are:
• The current stresses in the capacitors are halved because the resonant current is shared between the two
parts.
• The currents during the conduction times of both Q1 and Q2 flow in the current sensing resistor.
The main disadvantage is two parts are needed.
D1
0.5 CR
Q1
NP:NS:NS
+
CO
+
±
RL
VSQ
VIN
LR
LM
VOUT
D2
Q2
0.5 CR
RCS(llc)
VCS(llc)
Figure 33. Basic LLC Schematic with Split Resonant Capacitor
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8.2.2.17 LLC Primary-Side MOSFETs
VIN appears across the MOSFET which is not conducting. The voltage rating must then be:
831(LA=G ) = 832(LA=G ) = 8+0 = 400 8 500 8
(29)
This is a minimum rating and a 650-V rated part would be a better choice to allow margin for line-surge tests.
In the steady state, each MOSFET carries half of the resonant current. Start-up currents can be significantly
higher so we set the RMS current rating to 110 % of the resonant current.
+31(NIO ) = +32(NIO ) = 110% +4 = 1.1 × 2.4# = 2.65 #
(30)
8.2.2.18 LLC Output Rectifier Diodes
The voltage rating for the output diodes is given by:
8&$ =
8+0(I=T ) 400 8
=
= 50 8 62 8
0
8
(31)
The current rating for the output diodes is given by:
+5#8 =
¾2 +1'(5) ¾2 × 15.3 #
=
= 6.9 #
è
è
(32)
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8.2.2.19 LLC Stage Output Capacitors
The LLC converter topology does not require an output filter although a small second stage filter inductor may be
useful in reducing peak-to-peak output noise.
Assuming that the output capacitors carry the rectifier’s full wave output current then the capacitor ripple current
rating is:
è
+4'%6 = +59 =
2¾2
è
+176 =
× 12.5 # = 13.9 #
2¾2
(33)
The capacitor’s RMS current rating at 120 kHz is:
è
è2
+%(KQP ) = ¨(
+176 )2 F +176 2 = ¨ F 1 × +176 = 0.483 × 12.5 # = 6.04 #
8
2¾2
(34)
Solid Aluminum capacitors with conductive polymer technology have high ripple-current ratings and are a good
choice here. The ripple-current rating for a single capacitor may not be sufficient so multiple capacitors are often
connected in parallel.
The ripple voltage at the output of the LLC stage is a function of the amount of AC current that flows in the
capacitors. To estimate this voltage, we assume that all the current, including the DC current in the load, flows in
the filter capacitors.
'54/#: =
VOUT(pkFpk)
+4'%6(LG )
=
300 I8
= è
= 15.3 IÀ
è
+176
2 × 12.5 #
4
4
VOUT(pkFpk)
2
(35)
The capacitor specifications are:
• Voltage Rating: 30 V
• Ripple Current Rating: 6.04 A at 120 kHz
• ESR: < 15 mΩ
8.2.2.20 LLC Stage Over-Current Protection, Current Sense Resistor
This resistor shown in Figure 29 and Figure 33 senses the LLC stage input current. This current contains a
significant component at the switching frequency in additional to a DC component. Only the DC component is
proportional to the load current. This means that the signal should be filtered before it is applied to the LLC_CS
pin of the UCC29950. The degree of filtering is a compromise between response time and accuracy. A
recommended schematic is shown in Figure 13. An RC filter with a pole at about 1 kHz is used to filter the signal.
An additional capacitor, C1, across the current sense resistor provides a higher frequency pole at approximately
10 kHz.
The LLC current sensing resistor is selected so that the LLC_CS signal is at 90% of the OCP1 level (400 mV x
0.9 = 360 mV) when the converter is operating at full load and nominal input and output conditions. The resistor
value is then given by:
4%5(HH? ) =
8%5(HH? _BH ) 8$.- (IEJ )
0.36 8 × 370 8
=
= 403 IÀ 400 IÀ
1
110%
× 300 9
2176
ß
(36)
Where VBLK(min) is the voltage at the bottom of the line ripple on CBLK.
Assuming there is no ripple current in the current sensing resistor, the full load power dissipated in this resistor is
given by:
24%5 (..% ) =
2
8%5(HH?
_BH)
4%5(HH? )
=
0.36 8 2
= 324 I9
400 IÀ
(37)
The resistor should be able to dissipate the power due to an overload which is just lower than the OCP_1
threshold.
24% (HH? _I=T ) =
50
2
8%5(1%21)
4%5(..%)
=
0.4 82
= 400 I9
400 IÀ
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8.2.2.21 Detailed Design Procedure for the PFC stage
The boost topology operated in Continuous Conduction Mode (CCM) is a popular choice for a Power Factor
Correction (PFC) stage because it has lower component stresses than other topologies. This becomes more
important at higher power levels.
The schematic for a basic PFC is shown in Figure 34. The basic schematics for the three boost PFC circuits,
Discontinuous Conduction Mode (DCM), Transition Mode (TM) and CCM, are the same. The differences relate to
whether or not the inductor current is allowed to go to zero for part of the PWM cycle (DCM) and whether the
PFC frequency is held constant or used as a control variable (TM)
LPFC
VAC
EMC Filter
D1
VBLK
CBLK
BR1
Q1
CIN
RCS(pfc)
RTOP
30 M
VBULK
RBOT
73.3 k
VCS(pfc)
Figure 34. Basic PFC Schematic
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8.2.2.22 PFC Stage Output Current Calculation
The first step is to determine the maximum load current on the PFC stage, allowing for an overload to 110 % of
maximum load power.
+176 (LB? ) =
110% 2176
1.1 × 300 9
=
= 0.9 #
8$.- (IEJ )
370 8
(39)
8.2.2.23 Line Current Calculation
Next determine the maximum RMS input-line current, allowing for an overload to 110% of maximum load power.
+.+0'(4/5 :I=T ;) =
110% 2176
1.1 × 300 9
=
= 4.31 #
0.9 × 85 8
ß 8#%(IEJ )
(40)
The peak line current is:
+.+0'(2'#-:I=T ;) = ¾2 +.+0'(4/5:I=T ;) = ¾2 × 4.07 # = 6.1 #
(41)
The average line current is given by:
+.+0'(#8) :I=T ;) =
2 +.+0'(2'#- :I=T ;)
2 × 6.1 #
=
= 3.88 #
è
è
(42)
8.2.2.24 Bridge Rectifier
A typical bridge rectifier has a forward voltage drop VF_BR of 0.95 V. The power loss in the bridge rectifier can be
calculated from:
2$4 = 2 8(($4) +.+0'(#8) :I=T ;) = 2 × 0.95 8 × 3.88 # = 7.37 9
(43)
The bridge rectifier must be rated to carry the full-line current (ILINE(avg_max)). The voltage rating of the bridge
should be at least 600 V. The bridge rectifier also carries the full inrush current as the bulk capacitor (CBLK)
charges when the line is connected. The amplitude and duration of this current is difficult to determine in
advance because it depends on many unknown parameters.
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8.2.2.25 PFC Boost Inductor
The boost inductor is usually chosen so that the peak-to-peak amplitude of the switching frequency ripple
current, IHFR(pfc), is between 20% and 40% of the average current at peak of line. This design example uses
IHFR_PFC = 30%. Numerically this is, (from Equation 41)
+*(4(LB? ) = 0.30 +.+0' (2'#- :I=T ;) = 0.30 × 6.1 # = 1.83 #
(44)
The minimum boost inductor value is calculated from a worst case duty cycle of 50%.
.2(% R
8$.- &:1 F &; 385 8 × 0.5 × :1 F 0.5;
=
= 536 µ* 550 µ*
B2(% +*(42(%
98 G*V × 1.83 #
(45)
The boost inductor must be able to support a maximum current of:
+.(LA=G ) = +.+0'(LA=G (I=T )) +
+*(4(LB? )
1.83 #
= 6.1 # +
= 7.0#
2
2
(46)
The boost inductor specifications are:
• LPFC = 550 µH
• Current = 7 A
8.2.2.26 PFC Input Capacitor
The purpose of the input capacitor is to provide a local, low-impedance source for the high-frequency ripple
currents which flow in the PFC inductor. The allowed voltage ripple on CIN is ΔVIN.
V+0 = 5% ¾2 8#%(IEJ ) = 5% × ¾2 × 85 8 = 6.0 8
(47)
%+0
+*(4(LB? )
1.83 #
=
=
= 390 J( 470 J(
8 B2(% V+0
8 × 98 G*V × 6.0 8
(48)
An X2 film capacitor is normally chosen for this application.
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8.2.2.27 PFC Stage MOSFET
The main specifications for the PFC stage MOSFET are:
• BVDSS, Drain Source Breakdown Voltage, ≥ 650 V
• RDS(on), On State Drain Source Resistance, 460 mΩ (125 °C)
• COSS, Output Capacitance, 87 pF
• tr, device rise time, 30 ns
• tf device fall time, 34 ns
The losses in the device are calculated below. These calculations are approximations because the losses are
dependent on parameters which are not well controlled. For example the RDS(on) of a MOSFET can vary by a
factor of 2 from 25°C to 125°C. Therefore several iterations may be needed to choose an optimum device for an
application different to the one discussed.
The conduction losses are estimated by:
2176(I=T )
16¾28#%(IEJ ) 2
¨2 F
231(?KJ@ ) = (
) 4&5(KJ )
3è8$.¾28#%(IEJ )
(49)
Numerically:
300 9
16¾2 × 85 8 2
¨2 F
231(?KJ@ ) = (
) × 0.46 À = 4.21 9
3è × 385 8
¾2 × 85 8
(50)
The switching losses in the MOSFET are estimated by:
231(OS) =
1
2
B (8 +
kP + PB o + %155 8$.)
2 2(% $.- .+0'(4/5(I=T )) N
(51)
Numerically:
231(OS ) =
1
2
× 98 G*V × :385 8 × 4.31 # × :30 JO + 34 JO; + 87 L( × 385 82 ; = 5.84 9
231 = 231(?KJ@ ) + 231(OS) = 4.21 9 + 5.84 9 = 10.05 9
(52)
(53)
8.2.2.28 PFC Boost Diode
Reverse recovery losses can be significant in a CCM boost converter so a silicon carbide diode is chosen here
because it has no reverse recovery charge, QRR, and therefore zero reverse recovery losses. The disadvantage
is that the cost is higher than that of Silicon ultra fast diodes. The losses are estimated as follows:
2&1 = 8B +176 = 1.5 8 × 0.9 # = 1.35 9
(54)
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8.2.2.29 Bulk Capacitor
The value of the bulk capacitor is determined by three factors.
1. To ensure loop stability, the capacitance must be between 0.5 μF W-1 and 2.4 μF W-1 (see PFC Inductor and
Bulk Capacitor Recommendations). For this 300-W application a bulk capacitance in the range 150 μF to 720
μF is allowed.
2. It must be large enough to provide the required hold-up time.
3. It must be large enough to keep the ripple at twice line frequency within the required limits.
The UCC29950 continues to run the LLC stage until the voltage at the VBULK pin has fallen below VBULK(llc_stop)
(0.49 V). This corresponds to a VBLK of 200 V if the specified values for RBOT and RTOP are used. From
Equation 55 it can be see that the LLC stage will not have enough gain to maintain VOUT with such a low input
voltage. The minimum voltage at which the LLC stage regulates is determined from Equation 55 which is a
rearrangement of Equation 10. MG(max) is found from Figure 31 which gives a maximum gain of the LLC stage of
1.33.
8+0(IEJ ) = 0
2 8176
2 × 24 8
=8 ×
= 288 8 300 8
/)(I=T )
1.33
(55)
The value of the capacitor is then given by:
%$.- R
2 2176 P*
2 × 300 9 × 20 IO
=
= 255 µ( 270 µ(
2
2
3702 F 3002
8$.-(IEJ
F
8
$.-*7
)
(56)
-1
270 µF for 300 W is equal to 0.9 µF W which lies within the allowed range for loop stability.
The peak-to-peak ripple voltage at twice line frequency on CBLK is calculated as follows:
8$.-(NELLHA ) =
+176 (LB? )
0.9 #
=
= 11.3 8
è 2 B.+0'(IEJ ) %$.- è × 2 × 47 *V × 270 µ(
(57)
The result of this calculation, 11.3 V, is significantly better than the specification, 30 V. This is because the size
of the bulk capacitor is determined by the hold-up time rather than by the peak-to-peak line ripple specification.
The ripple current flowing in the bulk capacitor depends on the duty cycle which varies over the line cycle and
also as a function of the RMS value of the line voltage. This makes a precise calculation difficult however
Equation 58 gives a good approximation.
&
0.5
+%$.- _4 = +176 (LB? ) ¨
N 0.9 # × ¨
N 0.9 #
1F&
1 F 0.5
(58)
8.2.2.30 PFC Stage Current Sense Resistor
The current sense resistor is selected so that:
4%5(LB? ) = VPFCCS (cav _max ) 8#%(min )
ß
¾2 125% 2176
(59)
Numerically this is:
4%5(LB? ) = 225 mV × 85 V
90%
¾2 125% 2176
= 33 IÀ
(60)
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8.2.3 Application Curves
0.3
20
0.25
Gain
Phase
0.2
0
50
0.15
0.1
Phase (°)
Gain (dB)
THD
100
90 V
115 V
230 VTHD (%)
-20
0
0.05
0
-40
0
50
100
150
200
Input Power (W)
250
300
1
2
D001
Figure 35. Typical THD vs. Input Power
20
3
4 5 6 7 8 10
20
Frequency (Hz)
-50
30 40 50 70 100
D002
D008
D001
Figure 36. PFC Loop Gain/Phase at 300 W, 115 V
100
Gain
Phase
50
Phase (°)
Gain (dB)
0
-20
0
-40
1
2
3
4 5 6 7 8 10
20
Frequency (Hz)
-50
30 40 50 70 100
D002
D008
D001
Figure 38.
Figure 37. PFC Loop Gain/Phase at 300 W, 230 V
Figure 39. Line Current 115 V
56
Figure 40. Line Current 230 V
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Figure 41. LLC Stage Switching
(C1: VSQ, C2: GD1, C3: GD2 See Figure 33)
Figure 42. PFC Stage Switching (C1: VDS, C2: PFC_GD See
Figure 34)
8.3 Do's and Don'ts
Don’t probe the SUFG pin unless absolutely necessary. A normal X10 Oscilloscope probe can significantly load
the very high output impedance of this pin .
Pay careful attention to grounding and to the routing of the sensing signals at PFC_CS, LLC_CS, VBULK, AC1
and AC2 pins.
The UCC29950 uses low value PFC current sense resistors, 38 mΩ in the example above. Careful attention to
layout is needed to avoid significant errors in the PFC current and power limit points. Use Kelvin connections to
the resistors.
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9 Power Supply Recommendations
The UCC29950 should be operated from a VCC rail which is within the limits given in the VCC Bias Supply
section of the Electrical Characteristics table. To avoid the possibility that the device might stop switching, VCC
must not be allowed to fall into the UVLO range. In order to minimize power dissipation in the device, VCC
should not be unnecessarily high. Keeping VCC at 12 V is a good compromise between these competing
constraints. The gate drive outputs from the UCC29950 deliver large current pulses into their loads. This
indicates the need for a low ESR decoupling capacitor to be connected as directly as possible between the VCC
and PGND terminals. Ceramic capacitors with a stable dielectric characteristic over temperature, such as X7R,
are recommended. Avoid capacitors which have a large drop in capacitance with applied DC voltage bias and
use a part that has a low voltage co-efficient of capacitance. The recommended decoupling capacitance is 10
µF, X7R, with at least a 25-V rating.
Operation in Self Bias Mode requires an additional, larger, energy storage capacitor. The value required depends
on the details of the application but typically this part is between 100 µF and 300 µF. This energy storage
capacitor does not require low ESR and it does not need to be placed close to the UCC29950. A 25-V rated
aluminum electrolytic capacitor is a good choice.
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10 Layout
10.1 Layout Guidelines
In order to increase the reliability and robustness of the design, it is recommended that the following layout
guidelines be met.
10.1.1 GND Pin
• This pin is the power ground connection and should be used as the return connection for the driver pins
PFC_GD, GD1 and GD2.
• GND and AGND must be connected at a star point close to the pins on the controller
• If possible use a ground plane to minimize noise pickup.
10.1.2 GD1, GD2 Pins
• The GD1 and GD2 gate drive pins can be used to directly drive the primary winding of a gate-drive
transformer or a high voltage gate driver device. The tracks connected to these pins carry high dv/dt signals.
Minimize noise pickup by routing them as far away as possible from tracks connected to the device inputs,
AC1, AC2, VBULK, FB, PFC_CS and LLC_CS.
10.1.3 VCC Pin
• The VCC pin must be decoupled to GND and AGND by two 10-µF 1206 ceramic capacitors placed close to
the pins. In addition it is recommended that an additional 0.1-µF ceramic capacitor 0603 be placed in parallel
between the VCC and AGND pin.
10.1.4 SUFG Pin
• The SUFG is a high-impedance pin and can only be connected to the gate of the external depletion mode
MOSFET when the external high-voltage start-up feature is required. If the application does not require the
external high-voltage start-up circuit then the SUFG pin should be left open circuit.
10.1.5 SUFS Pin
• The SUFS connects to the source of an external depletion mode MOSFET, if this feature in not required,
SUFS should be connected to the VCC rail.
10.1.6 AGND Pin
• As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the
integrity of the ground return. Place all decoupling and filter capacitors as close as possible to the device pins
with short traces. The AGND pin is used as the return connection for the low-power signaling and sensitive
signal traces, AC1, AC2, VBULK, FB, MD_SEL/PS_ON and AC DET. It is also used as local decoupling
return for PFC_CS and LLC_CS. It is connected to the GND pin at a star point close to the device.
10.1.7 MD_SEL/PS_ON Pin
• This pin is not especially sensitive but minimize coupling to tracks carrying high dv/dt signals.
10.1.8 VBULK Pin
• The VBULK sense chain is connected to the high-voltage rail on the PFC stage. Typically the top resistive
element of the sense chain is split into two or three separate resistors to reduce the voltage stress on each
device and permit the use of standard low-cost resistors, such as 1206 sized SMT devices, in the sense
chain. Sufficient PCB spacing must be given between the high-voltage connections to the low voltage and
GND nets. The VBULK is a high-impedance connection and should be shielded by a ground plane from any
high-voltage switching nets. The copper area connecting the VBULK pin to the lower resistor/filter capacitor
and the last resistor in the high-side divider chain should be kept to a minimum to reduce parasitic
capacitance to any nearby switching nets. The bottom resistor in the divider network and filter capacitor must
be placed close to the VBULK pin.
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Layout Guidelines (continued)
10.1.9 AC1, AC2 Pins
• The AC1 and AC2 are connected to the AC input lines by resistive divider chains. These divider chains are
normally formed using several discrete resistors in series. The AC1 and AC2 are high-impedance pins and
care must be taken to route the resistor divider components away from high voltage switching nets. Ideally
the connections should be shielded by ground planes. Sufficient PCB spacing must be given between the
high-voltage connections and any low-voltage nets. A filter capacitor, 470 pF, must be placed in close
proximity to the pins on the controller to decouple any high-frequency noise picked up on the AC1 and AC2
sense-chain connections.
10.1.10 LLC_CS
• The LLC_CS pin should be decoupled by an external RC filter placed close to the pin. Suitable values are a
2.2-kΩ resistor and 0.1-µF ceramic capacitor.
10.1.11 FB
• The FB signal is a low-power, high-impedance signal from the LLC regulation circuit. The PCB tracks from the
opto-coupler should be tracked to minimize the loop area by running the VÌ feed track and FB signal from the
opto-coupler in parallel. It is also recommended to provide screening for these traces with ground plane(s).
10.1.12 PFC_CS
• The PFC_CS requires an external resistor, recommended value of 1 kΩ, between the current sensing resistor
and the PFC_CS pin to avoid overstressing the device during inrush. A small filter capacitor (1 nF) may be
useful to further reduce the noise level at this pin. These components should be placed close to PFC_CS pin.
• The PFC_CS resistor is a low resistance part. Be careful that the connections to this resistor connect directly
to the part terminals to avoid adding extra parasitic resistance. Be especially careful of the connection to the
ground side of this resistor.
10.1.13 AC_DET
• The AC_DET is a signal output. This is a low-voltage signal trace and must be kept clear of any high-voltage
switching nodes.
10.1.14 PFC_GD
• The track connected to the PFC_GD pin carries high dv/dt signal. Minimize noise pickup by routing the trace
to this pin as far away as possible from tracks connected to the device inputs – AC1, AC2, VBULK, FB,
PFC_CS and LLC_CS
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10.2 Layout Example
PFC_CS
LLC_CS
Star
Point
VBLK
GND
PFC_GD
GD2
AC_DET
VCC
GD1
SUFG
PFC_CS
SUFS
FB
AGND
LLC_CS
MD_SEL/
PS_ON
AC1
VBULK
AC2
PFC_CS
LLC_CS
Figure 43.
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
1. Combining Peak Current Mode Control with Average Current Mode Control Using Digitally Assisted Analog;
Seamus O’Driscoll, Texas Instruments and David A. Grant, Texas Instruments; 2014 IEEE Applied Power
Electronics Conference and Exposition (APEC 2014), PP76
2. TI Application Note LLC Design for UCC29950 Texas Instruments Literature Number SLUA733
11.2 Trademarks
is a registered trademark of ~ECOVA, INC..
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC29950D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC29950
UCC29950DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC29950
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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