UCD90124ARGCR

Product Folder Order Now Support & Community Tools & Software Technical Documents UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 UCD90124A 12-Rail Power Supply Sequencer and Monitor with ACPI Support and Fan Control" 1 Features 3 Description • The UCD90124A is a 12-rail PMBus/I2C addressable power-supply sequencer and monitor. The device integrates a 12-bit ADC for monitoring up to 12 power-supply voltage inputs. Twenty-six GPIO pins can be used for power supply enables, power-on reset signals, external interrupts, cascading, or other system functions. Twelve of these pins offer PWM functionality. Using these pins, the UCD90124A offers support for fan control, margining, and generalpurpose PWM functions. 1 • • • • • • • • Monitor and sequence 12 voltage rails – All rails sampled every 400 μs – 12-bit ADC with 2.5-V, 0.5% internal VREF – Sequence based on time, rail and pin dependencies – Four programmable undervoltage and overvoltage thresholds per monitor Nonvolatile error and peak-value logging per monitor (up to 12 fault detail entries) Closed-loop margining for 10 Rails – Margin output adjusts rail voltage to match user-defined margin thresholds Programmable watchdog timer and system reset Flexible digital I/O configuration Pin-selected rail states Multiphase PWM clock generator – Clock frequencies from 15.259 kHz to 125 MHz – Capability to configure independent clock outputs for synchronizing switch-mode power supplies JTAG and I2C/SMBus/PMBus™ interfaces Fan control and monitoring system functions. – Supports four fans with five user-defined speed-vs-temperature setpoints – Supports two-, three-, and four-wire fans Specific power states can be achieved using the PinSelected Rail States feature. This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used for hardware devices. The TI Fusion Digital Power™ designer software is provided for device configuration. This PC-based graphical user interface (GUI) offers an intuitive interface for configuring, storing, and monitoring all system operating parameters. Device Information(1) PART NUMBER PACKAGE UCD90124A BODY SIZE (NOM) VQFN (64) 9.00 mm × 9.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic 12V 12V OUT 3.3V_UCD V33A V33D Industrial ATE Telecommunications and networking equipment Servers and storage systems Any system requiring sequencing and monitoring of multiple power rails TEMP12V 5.1V 12V OUT • • • • TEMP IC INA196 V33FB 2 Applications I12V GPIO VIN VMON VMON 1.8V OUT VMON 0.8V OUT VMON I0.8V VMON TEMP0.8V VMON I12V VMON TEMP12V VMON 3.3V OUT VOUT /EN GPIO 3.3V OUT DC-DC 1 VFB VIN /EN GPIO VOUT 1.8V OUT LDO1 TEMP IC VIN UCD90124A WDI from main processor GPIO WDO GPIO POWER_GOOD GPIO TEMP0.8V 0.8V OUT VOUT /EN GPIO DC-DC 2 VFB INA196 PWM WARN_OC_0.8V_ OR_12V GPIO SYSTEM RESET GPIO OTHER SEQUENCER DONE (CASCADE INPUT) 2MHz I0.8V Vmarg Closed Loop Margining 4- wire Fan 12 V GPIO 12V I2C/ PMBUS JTAG PWM GPIO 25 kHz Fan PWM Fan Tach PWM TACH GND DC Fan 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Pin Configuration and Functions ......................... 3 Specifications......................................................... 7 Absolute Maximum Ratings.................................. 7 ESD Ratings ........................................................... 7 Recommended Operating Conditions ................. 7 Thermal Information.............................................. 7 Electrical Characteristics ..................................... 9 I2C/SMBus/PMBus Timing Requirements ........ 10 12.1 Typical Characteristics .......................................... 11 13 Detailed Description ........................................... 12 13.1 Overview ............................................................... 12 13.2 Functional Block Diagram ..................................... 18 13.3 Feature Description............................................... 18 13.4 Device Functional Modes...................................... 18 13.5 Programming......................................................... 42 14 Application and Implementation........................ 47 14.1 Application Information.......................................... 47 14.2 Typical Application ............................................... 47 15 Power Supply Recommendations ..................... 50 16 Layout................................................................... 50 16.1 Layout Guidelines ................................................. 50 16.2 Layout Example .................................................... 50 17 Device and Documentation Support ................. 52 17.1 17.2 17.3 17.4 17.5 17.6 Device Support...................................................... Documentation Support ........................................ Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 52 52 52 52 52 52 18 Mechanical, Packaging, and Orderable Information ........................................................... 52 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (January 2012) to Revision A Page • Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1 • Added fan control to the feature list ...................................................................................................................................... 1 • Changed 0 V to 0.2 V for MON10 through MON13................................................................................................................ 5 • Changed Tinternal to Tempinternal in the Electrical Characteristics ............................................................................................ 9 • Added footnote Characterized by design and not production tested. .................................................................................... 9 • Added footnote The maximum high/low temperature values are not production tested. ...................................................... 9 • Changed Timing requirements table (tf) from: See (Note Rise Time) To: See (Note Fall Time) ......................................... 10 • Changed Timing requirements table (tf) from: See (Note Fall Time) To: See (Note Rise Time) ........................................ 10 • Added GPIO 1/2/3/4/13/16/17/18 pins shall not be configured to enable the low latency feature. Otherwise the functions of associated logical controlled GPOs may malfunction. For example, GPIO13 is the fifth one among those 8 pins. If configured as the fifth GPI, the low latency feature is enabled, otherwise it is disabled....................................... 48 2 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 5 Pin Configuration and Functions AVSS3 MON9 MON8 PMBUS_ADDR0 PMBUS_ADDR1 MON7 V33FB NC4 MON13 NC3 MON12 NC2 MON11 NC1 MON10 AVSS1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RGC Package with Thermal Pad 64-Pin VQFN Top View RESET 9 40 TRST TRCK 10 39 TMS/GPIO22 GPIO1 11 38 TDI/ GPIO21 GPIO2 12 37 TDO/GPIO20 GPIO3 13 36 TCK/GPIO19 GPIO4 14 35 GPIO18 PMBUS_CLK 15 34 GPIO17 PMBUS_DATA 16 33 GPIO16 32 PWM4/GPI4 PWM2/GPI2 41 31 8 PWM1/GPI1 DVSS1 30 PWM3/GPI3 GPIO15 42 29 7 GPIO14 V33DIO1 28 DVSS3 PMBUS_CNTRL 43 27 6 PMBUS_ALERT MON6 26 V33DIO2 DVSS2 44 25 5 GPIO13 MON5 24 V33D FPWM8/GPIO12 45 23 4 FPWM7/GPIO11 MON4 22 V33A FPWM6/GPIO10 46 21 3 FPWM5/GPIO9 MON3 20 BPCAP FWPM4/GPIO8 47 19 2 FPWM3/GPIO7 MON2 18 AVSS2 FPWM2/GPIO6 48 17 1 FPWM1/GPIO5 MON1 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 3 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com V33B BPCAP V33A V33D V33DIO1 V33DIO2 7 44 45 46 47 58 1 MON1 2 MON2 TCK/GPIO19 36 3 MON3 TDO/GPIO20 37 TRCK 10 4 MON4 TDI/GPIO21 38 5 MON5 TMS/GPIO22 39 6 MON6 TRST 40 59 MON7 62 MON8 GPIO1 11 63 MON9 GPIO2 12 50 MON10 GPIO3 13 52 MON11 GPIO4 14 54 MON12 GPIO13 25 56 MON13 GPIO14 29 GPIO15 30 GPIO16 33 15 PMBUS_CLK GPIO17 34 16 PMBUS_DATA GPIO18 35 27 PMBUS_ALERT 28 PMBUS_CNTRL FPWM1/GPIO5 17 61 PMBUS_ADDR0 FPWM2/GPIO6 18 60 PMBUS_ADDR1 FPWM3/GPIO7 19 FPWM4/GPIO8 20 31 PWM1/GPI1 FPWM5/GPIO9 32 PWM2/GPI2 FPWM6/GPIO10 22 42 PWM3/GPI3 FPWM7/GPIO11 23 41 PWM4/GPI4 FPWM8/GPIO12 24 51 NC1 53 NC2 55 NC3 57 NC4 9 AVSS3 AVSS1 AVSS2 DVSS3 DVSS2 DVSS1 RESET 21 64 49 48 43 26 8 4 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Table 1. Pin Functions (1) PIN NAME PIN NO. I/O TYPE DESCRIPTION ANALOG MONITOR INPUTS MON1 1 I Analog input (0 V–2.5 V) MON2 2 I Analog input (0 V–2.5 V) MON3 3 I Analog input (0 V–2.5 V) MON4 4 I Analog input (0 V–2.5 V) MON5 5 I Analog input (0 V–2.5 V) MON6 6 I Analog input (0 V–2.5 V) MON7 59 I Analog input (0 V–2.5 V) MON8 62 I Analog input (0 V–2.5 V) MON9 63 I Analog input (0 V–2.5 V) MON10 50 I Analog input (0.2 V–2.5 V) MON11 52 I Analog input (0.2 V–2.5 V) MON12 54 I Analog input (0.2 V–2.5 V) MON13 56 I Analog input (0.2 V–2.5 V) GPIO1 11 I/O General-purpose discrete I/O GPIO2 12 I/O General-purpose discrete I/O GPIO3 13 I/O General-purpose discrete I/O GPIO4 14 I/O General-purpose discrete I/O GPIO13 25 I/O General-purpose discrete I/O GPIO14 29 I/O General-purpose discrete I/O GPIO15 30 I/O General-purpose discrete I/O GPIO16 33 I/O General-purpose discrete I/O GPIO17 34 I/O General-purpose discrete I/O GPIO18 35 I/O General-purpose discrete I/O FPWM1/GPIO5 17 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO FPWM2/GPIO6 18 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO FPWM3/GPIO7 19 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO FPWM4/GPIO8 20 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO FPWM5/GPIO9 21 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO FPWM6/GPIO10 22 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO FPWM7/GPIO11 23 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO FPWM8/GPIO12 24 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO PWM1/GPI1 31 I/PWM Fixed 10-kHz PWM output or GPI PWM2/GPI2 32 I/PWM Fixed 1-kHz PWM output or GPI PWM3/GPI3 42 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI PWM4/GPI4 41 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI GPIO PWM OUTPUTS PMBus COMM INTERFACE PMBUS_CLK 15 I/O PMBus clock (must have pullup to 3.3 V) PMBUS_DATA 16 I/O PMBus data (must have pullup to 3.3 V) PMBALERT# 27 O PMBus alert, active-low, open-drain output (must have pullup to 3.3 V) PMBUS_CNTRL 28 I PMBus control PMBUS_ADDR0 61 I PMBus analog address input. Least-significant address bit PMBUS_ADDR1 60 I PMBus analog address input. Most-significant address bit JTAG (1) The maximum number of configurable rails is 16. The maximum number of configurable GPIs is 8. The maximum number of configurable Boolean Logic GPOs is 16. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 5 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com Table 1. Pin Functions(1) (continued) PIN NAME PIN NO. I/O TYPE TRCK 10 O Test return clock TCK/GPIO19 36 I/O Test clock or GPIO TDO/GPIO20 37 I/O Test data out or GPIO TDI/GPIO21 38 I/O Test data in (tie to Vdd with 10-kΩ resistor) or GPIO TMS/GPIO22 39 I/O Test mode select (tie to Vdd with 10-kΩ resistor) or GPIO TRST 40 I 6 DESCRIPTION Test reset – tie to ground with 10-kΩ resistor Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Table 1. Pin Functions(1) (continued) PIN NAME PIN NO. I/O TYPE DESCRIPTION INPUT POWER AND GROUNDS RESET 9 Active-low device reset input. Hold low for at least 2 μs to reset the device. V33FB 58 3.3-V linear regulator feedback connection. Leave unconnected. V33A 46 Analog 3.3-V supply. Refer to the layout guidelines section. V33D 45 Digital core 3.3-V supply. Refer to the layout guidelines section. V33DIO1 7 Digital I/O 3.3-V supply. Refer to the layout guidelines section. V33DIO2 44 Digital I/O 3.3-V supply. Refer to the layout guidelines section. BPCap 47 1.8-V bypass capacitor – tie 0.1-μF capacitor to analog ground. AVSS1 49 Analog ground AVSS2 48 Analog ground AVSS3 64 Analog ground DVSS1 8 Digital ground DVSS2 26 Digital ground DVSS3 43 Digital ground QFP ground pad NA Thermal pad – tie to ground plane. 6 Specifications 7 Absolute Maximum Ratings (1) MIN MAX UNIT Voltage applied at V33D to DVSS –0.3 3.8 V Voltage applied at V33A to AVSS –0.3 3.8 V –0.3 (V33A + 0.3) V –40 150 °C Voltage applied to any other pin (2) Storage temperature (Tstg) (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability All voltages referenced to VSS 8 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2500 Charged device model (CDM), per JEDEC specification JESD22C101 (2) V ±750 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 9 Recommended Operating Conditions Supply voltage during operation (V33D, V33DIO, V33A) Operating free-air temperature range, TA MIN NOM MAX 3 3.3 3.6 V 110 °C 125 °C –40 Junction temperature, TJ UNIT 10 Thermal Information UCD90160 THERMAL METRIC (1) RGC [VQFN] UNIT 64 PINS RθJA (1) Junction-to-ambient thermal resistance 26.4 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 7 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com Thermal Information (continued) UCD90160 THERMAL METRIC (1) RGC [VQFN] UNIT 64 PINS RθJC(top) Junction-to-case(top) thermal resistance 21.2 °C/W RθJB Junction-to-board thermal resistance 1.7 °C/W ψJT Junction-to-top characterization parameter 0.7 °C/W ψJB Junction-to-board characterization parameter 8.8 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance 1.7 °C/W 8 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 11 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Supply Current IV33A VV33A = 3.3 V 8 mA IV33DIO VV33DIO = 3.3 V 2 mA VV33D = 3.3 V 40 mA VV33D = 3.3 V, storing configuration parameters in flash memory 50 mA IV33D Supply current (1) IV33D Analog Inputs (MON1–MON16) MON1–MON13 VMON Input voltage range INL ADC integral nonlinearity DNL ADC differential nonlinearity Ilkg Input leakage current 3 V applied to pin IOFFSET Input offset current 1-kΩ source impedance RIN Input impedance CIN Input capacitance tCONVERT ADC sample period 16 voltages sampled, 3.89 μsec/sample VREF ADC 2.5 V, internal reference accuracy 0°C to 125°C MON14–MON16 0 2.5 0.2 2.5 –4 4 LSB 2 LSB -2 MON1–MON13, ground reference MON14–MON16, ground reference –5 V 100 nA 5 μA 3 MΩ 10 pF 8 0.5 V MΩ 1.5 400 μsec –0.5% 0.5% –40°C to 125°C –1% 1% 9 11 2.26 Analog Input (PMBUS_ADDRx) IBIAS Bias current for PMBus Addr pins VADDR_OPEN Voltage – open pin PMBUS_ADDR0, PMBUS_ADDR1 open VADDR_SHORT Voltage – shorted pin PMBUS_ADDR0, PMBUS_ADDR1 short to ground Tempinternal Internal temperature sense accuracy (2) Over range from –40°C to 125°C -10 (3) μA V ±5 0.124 V 10 °C Dgnd + 0.25 V Digital Inputs and Outputs VOL Low-level output voltage IOL = 6 mA (4), V33DIO = 3 V (5) VOH High-level output voltage IOH = –6 mA VIH High-level input voltage V33DIO = 3 V VIL Low-level input voltage V33DIO = 3.5 V , V33DIO = 3 V V33DIO – 0.6 V 2.1 3.6 V 1.4 V Margining Outputs TPWM_FREQ MARGINING-PWM frequency DUTYPWM MARGINING-PWM duty cycle range FPWM1-8 PWM3-4 15.260 125000 0.001 7800 0% 100% kHz System Performance VDDSlew Minimum VDD slew rate VDD slew rate between 2.3 V and 2.9 V VRESET Supply voltage at which device comes out of reset For power-on reset (POR) tRESET Low-pulse duration needed at RESET pin To reset device during normal operation f(PCLK) Internal oscillator frequency TA = 125°C, TA = 25°C (1) (2) (3) (4) (5) 0.25 V/ms 2.4 2 240 V μS 250 260 MHz Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins. Characterized by design and not production tested. The maximum high/low temperature values are not production tested. The maximum total current, IOL max, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. The maximum total current, IOH max, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 9 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tretention Retention of configuration parameters TJ = 25°C 100 Years Write_Cycles Number of nonvolatile erase/write cycles TJ = 25°C 20 K cycles I2C/SMBus/PMBus Timing Requirements 12 Timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBus TA = –40°C to 85°C, 3 V < VDD < 3.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted) MAX UNIT FSMB SMBus/PMBus operating frequency PARAMETER Slave mode, SMBC 50% duty cycle TEST CONDITIONS 10 400 kHz FI2C I2C operating frequency Slave mode, SCL 50% duty cycle 10 400 kHz t(BUF) Bus free time between start and stop 1.3 μs t(HD:STA) Hold time after (repeated) start 0.6 μs t(SU:STA) Repeated-start setup time 0.6 μs t(SU:STO) Stop setup time 0.6 μs t(HD:DAT) Data hold time 0 ns t(SU:DAT) Data setup time 100 ns Receive mode (1) t(TIMEOUT) Error signal/detect t(LOW) Clock low period t(HIGH) Clock high period See (2) t(LOW:SEXT) Cumulative clock low slave extend time See (3) tf Clock/data fall time See (4) tr Clock/data rise time See (5) Cb Total capacitance of one bus line (1) (2) (3) (4) (5) See MIN TYP 35 1.3 ms μs 0.6 μs 25 ms 20 + 0.1 Cb 300 ns 20 + 0.1 Cb 300 ns 400 pF The device times out when any clock low exceeds t(TIMEOUT). t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0). t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. Fall time tf = 0.9 VDD to (VILMAX – 0.15) Rise time tr = (VILMAX – 0.15) to (VIHMIN + 0.15) Figure 1. I2C/SMBus Timing Diagram 10 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Start Stop TLOW:SEXT TLOW:MEXT TLOW:MEXT TLOW:MEXT PMB_Clk Clk ACK Clk ACK PMB_Data Figure 2. Bus Timing in Extended Mode 2.500 1.3 2.498 1.0 2.496 0.8 2.494 0.5 DNL High 0.3 DNL Low DNL (LSB) ADC Reference Voltage (V) 12.1 Typical Characteristics 2.492 2.490 0.0 2.488 ±0.3 2.486 ±0.5 2.484 ±0.8 2.482 ±50 ±30 ±10 10 30 50 70 90 110 Temperature (Cƒ) ±1.0 130 ±50 ±30 10 ±10 30 50 70 90 110 Temperature (ƒC) C001 Figure 3. ADC Reference Voltage vs Temperature 130 C002 Figure 4. ADC Differential Nonlinearity vs Temperature 2.5 2.0 INL (LSB) 1.5 1.0 INL High 0.5 INL Low 0.0 ±0.5 ±1.0 ±1.5 ±50 ±30 ±10 10 30 50 70 Temperature (ƒC) 90 110 130 C003 Figure 5. ADC Integral Nonlinearity vs Temperature Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 11 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com 13 Detailed Description 13.1 Overview Modern electronic systems often use numerous microcontrollers, DSPs, FPGAs, and ASICs. Each device can have multiple supply voltages to power the core processor, analog-to-digital converter or I/O. These devices are typically sensitive to the order and timing of how the voltages are sequenced on and off. The UCD90124A can sequence supply voltages to prevent malfunctions, intermittent operation, or device damage caused by improper power up or power down. Appropriate handling of under- and overvoltage faults can extend system life and improve long term reliability. The UCD90124A stores power supply faults to on-chip nonvolatile flash memory for aid in system failure analysis. Tach monitor inputs, PWM outputs and temperature measurements can be combined with a choice between two built-in fan-control algorithms to provide a stand-alone fan controller for independent operation of up to four fans. System reliability can be improved through four-corner testing during system verification. During four-corner testing, the system is operated at the minimum and maximum expected ambient temperature and with each power supply set to the minimum and maximum output voltage, commonly referred to as margining. The UCD90124A can be used to implement accurate closed-loop margining of up to 10 power supplies. The UCD90124A 12-rail sequencer can be used in a PMBus- or pin-based control environment. The TI Fusion GUI provides a powerful but simple interface for configuring sequencing solutions for systems with between one and 12 power supplies using 12 analog voltage-monitor inputs, four GPIs and 22 highly configurable GPIOs. A rail includes voltage, a power-supply enable and a margining output. At least one must be included in a rail definition. Once the user has defined how the power-supply rails should operate in a particular system, analog input pins and GPIOs can be selected to monitor and enable each supply (Figure 6). 12 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Overview (continued) Figure 6. Fusion GUI Pin-Assignment Tab After the pins have been configured, other key monitoring and sequencing criteria are selected for each rail from the Vout Config tab (Figure 7): • Nominal operating voltage (Vout) • Undervoltage (UV) and overvoltage (OV) warning and fault limits • Margin-low and margin-high values • Power-good on and power-good off limits • PMBus or pin-based sequencing control (On/Off Config) • Rails and GPIs for Sequence On dependencies • Rails and GPIs for Sequence Off dependencies Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 13 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com Overview (continued) • • • Turn-on and turn-off delay timing Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled or disabled Other rails to turn off in case of a fault on a rail (fault-shutdown slaves) Figure 7. Fusion GUI VOUT-Config Tab The Synchronize margins/limits/PG to Vout check box is an easy way to change the nominal operating voltage of a rail and also update all of the other limits associated with that rail according to the percentages shown to the right of each entry. The plot in the upper left section of Figure 7 shows a simulation of the overall sequence-on and sequence-off configuration, including the nominal voltage, the turnon and turnoff delay times, the power-good on and powergood off voltages and any timing dependencies between the rails. After a rail voltage has reached its POWER_GOOD_ON voltage and is considered to be in regulation, it is compared against two UV and two OV thresholds in order to determine if a warning or fault limit has been exceeded. If a fault is detected, the UCD90124A responds based on a variety of flexible, user-configured options. Faults can cause rails to restart, shut down immediately, sequence off using turnoff delay times or shut down a group of rails and sequence them back on. Different types of faults can result in different responses. 14 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Overview (continued) Fault responses, along with a number of other parameters including user-specific manufacturing information and external scaling and offset values, are selected in the different tabs within the Configure function of the Fusion GUI. Once the configuration satisfies the user requirements, it can be written to device SRAM if Fusion GUI is connected to a UCD90124A using an I2C/PMBus. SRAM contents can then be stored to data flash memory so that the configuration remains in the device after a reset or power cycle. The Fusion GUI Monitor page has a number of options, including a device dashboard and a system dashboard, for viewing and controlling device and system status. Figure 8. Fusion GUI Monitor Page The UCD90124A also has status registers for each rail and the capability to log faults to flash memory for use in system troubleshooting. This is helpful in the event of a power-supply or system failure. The status registers (Figure 9) and the fault log (Figure 10) are available in the Fusion GUI. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference (SLVU352) and the PMBus Specification for detailed descriptions of each status register and supported PMBus commands. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 15 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com Overview (continued) Figure 9. Fusion GUI Rail-Status Register 16 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Overview (continued) Figure 10. Fusion GUI Flash-Error Log (Logged Faults) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 17 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com 13.2 Functional Block Diagram Comparators JTAG Or GPIO I2C/PMBus General Purpose I/O (GPIO) Rail Enables (16 max) 6 Digital Outputs (16 max) Monitor Inputs Digital Inputs (8 max) 16 12-bit 200ksps, ADC (0.5% Int. Ref) 22 SEQUENCING ENGINE Multi-phase PWM (8 max) FLASH Memory User Data, Fault and Peak Logging BOOLEAN Logic Builder Margining Outputs (10 max) 64-pin QFN 13.3 Feature Description 13.3.1 TI Fusion GUI The Texas Instruments Fusion Digital Power Designer is provided for device configuration. This PC-based graphical user interface (GUI) offers an intuitive I2C/PMBus interface to the device. It allows the design engineer to configure the system operating parameters for the application without directly using PMBus commands, store the configuration to on-chip nonvolatile memory, and observe system status (voltage, etc). Fusion Digital Power Designer is referenced throughout the data sheet as Fusion GUI and many sections include screenshots. The Fusion GUI can be downloaded from www.ti.com. 13.3.2 PMBUS Interface The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus interface that is built on the I2C physical specification. The UCD90124A supports revision 1.1 of the PMBus standard. Wherever possible, standard PMBus commands are used to support the function of the device. For unique features of the UCD90124A, MFR_SPECIFIC commands are defined to configure or activate those features. These commands are defined in the UCD90xxx Sequencer and System Health Controller PMBUS Command Reference (SLVU352). The most current UCD90xxx PMBus Command Reference can be found within the TI Fusion Digital Power Designer software through the Help Menu (Help, Documentation & Help Center, Sequencers tab, Documentation section). This document makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power System Management Protocol Specification Part II – Command Language, Revision 1.1, dated 5 February 2007. The specification is published by the Power Management Bus Implementers Forum and is available from www.pmbus.org. The UCD90124A is PMBus compliant, in accordance with the Compliance section of the PMBus specification. The firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT function. The hardware can support either 100-kHz or 400-kHz PMBus operation. 13.4 Device Functional Modes 13.4.1 Power-Supply Sequencing The UCD90124A can control the turn-on and turn-off sequencing of up to 12 voltage rails by using a GPIO to set a power-supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a sequence-on event by asserting the PMBUS_CNTRL pin or by sending the OPERATION command over the I2C serial bus. In pin-based designs, the PMBUS_CNTRL pin can also be used to sequence-on and sequence-off. 18 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Device Functional Modes (continued) The auto-enable setting ignores the OPERATION command and the PMBUS_CNTRL pin. Sequence-on is started at power up after any dependencies and time delays are met for each rail. A rail is considered to be on or within regulation when the measured voltage for that rail crosses the power-good on (POWER_GOOD_ON (6)) limit. The rail is still in regulation until the voltage drops below power-good off (POWER_GOOD_OFF). In the case that there isn't voltage monitoring set for a given rail, that rail is considered ON if it is commanded on (either by OPERATION command, PMBUS CNTRL pin, or auto-enable) and (TON_DELAY + TON_MAX_FAULT_LIMIT) time passes. Also, a rail is considered OFF if that rail is commanded OFF and (TOFF_DELAY + TOFF_MAX_WARN_LIMIT) time passes 13.4.1.1 Turn-on Sequencing The following sequence-on options are supported for each rail: • Monitor only – do not sequence-on • Fixed delay time (TON_DELAY) after an OPERATION command to turn on • Fixed delay time after assertion of the PMBUS_CNTRL pin • Fixed time after one or a group of parent rails achieves regulation (POWER_GOOD_ON) • Fixed time after a designated GPI has reached a user-specified state • Any combination of the previous options The maximum TON_DELAY time is 3276 ms. 13.4.1.2 Turn-off Sequencing The following sequence-off options are supported for each rail: • Monitor only – do not sequence-off • Fixed delay time (TOFF_DELAY) after an OPERATION command to turn off • Fixed delay time after deassertion of the PMBUS_CNTRL pin • Fixed time after one or a group of parent rails drop below regulation (POWER_GOOD_OFF) • Fixed delay time in response to an undervoltage, overvoltage, or max turn-on fault on the rail • Fixed delay time in response to a fault on a different rail when set as a fault shutdown slave to the faulted rail • Fixed delay time in response to a GPI reaching a user-specified state • Any combination of the previous options The maximum TOFF_DELAY time is 3276 ms. PMBUS_CNTRL PIN RAIL 1 EN TON_DELAY[1] TOFF_DELAY[1] POWER_GOOD_ON[1] POWER_GOOD_OFF[1] RAIL 1 VOLTAGE RAIL 2 EN Ÿ Rail 1 and Rail 2 are both sequenced “ON” and “OFF” by the PMBUS_CNTRL pin only Ÿ Rail 2 has Rail 1 as an “ON” dependency Ÿ Rail 1 has Rail 2 as an “OFF” dependency TON_DELAY[2] TOFF_DELAY[2] RAIL 2 VOLTAGE TON_MAX_FAULT_LIMIT[2] TOFF_MAX_WARN_LIMIT[2] Figure 11. Sequence-on and Sequence-off Timing (6) In this document, configuration parameters such as Power Good On are referred to using Fusion GUI names. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference name is shown in parentheses (POWER_GOOD_ON) the first time the parameter appears. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 19 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com Device Functional Modes (continued) 13.4.1.3 Sequencing Configuration Options In addition to the turn-on and turn-off sequencing options, the time between when a rail is enabled and when the monitored rail voltage must reach its power-good-on setting can be configured using max turn-on (TON_MAX_FAULT_LIMIT). Max turn-on can be set in 1-ms increments. A value of 0 ms means that there is no limit and the device can try to turn on the output voltage indefinitely. Rails can be configured to turn off immediately or to sequence-off according to rail and GPI dependencies, and user-defined delay times. A sequenced shutdown is configured by selecting the appropriate rail and GPI dependencies, and turn-off delay (TOFF_DELAY) times for each rail. The turn-off delay times begin when the PMBUS_CNTRL pin is deasserted, when the PMBus OPERATION command is used to give a soft-stop command, or when a fault occurs on a rail that has other rails set as fault-shutdown slaves. Shutdowns on one rail can initiate shutdowns of other rails or controllers. In systems with multiple UCD90124As, it is possible for each controller to be both a master and a slave to another controller. 13.4.2 Pin Selected Rail States This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used for operating system directed power management in servers and PCs. In up to 8 system states, the power system designer can define which rails are on and which rails are off. If a new state is presented on the input pins, and a rail is required to change state, it will do so with regard to its sequence-on or sequence-off dependencies. The OPERATION command is modified when this function causes a rail to change its state. This means that the ON_OFF_CONFIG for a given rail must be set to use the OPERATION command for this function to have any effect on the rail state. The first 3 pins configured with the GPI_CONFIG command are used to select 1 of 8 system states. Whenever the device is reset, these pins are sampled and the system state, if enabled, will be used to update each rail state. When selecting a new system state, changes to the status of the GPIs must not take longer than 1 microsecond. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for complete configuration settings of PIN_SELECTED_RAIL_STATES. Table 2. GPI Selection of System States GPI 2 State GPI 1 State GPI 0 State System State NOT Asserted NOT Asserted NOT Asserted 0 NOT Asserted NOT Asserted Asserted 1 NOT Asserted Asserted NOT Asserted 2 NOT Asserted Asserted Asserted 3 Asserted NOT Asserted NOT Asserted 4 Asserted NOT Asserted Asserted 5 Asserted Asserted NOT Asserted 6 Asserted Asserted Asserted 7 13.4.3 Monitoring The UCD90124A has 13 monitor input pins (MONx) that are multiplexed into a 2.5V referenced 12-bit ADC. The monitor pins can be configured so that they can measure voltage signals to report voltage, current and temperature type measurements. A single rail can include all three measurement types, each monitored on separate MON pins. If a rail has both voltage and current assigned to it, then the user can calculate power for the rail. Digital filtering applied to each MON input depends on the type of signal. Voltage inputs have no filtering. Current and temperature inputs have a low-pass filter. Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of 610 μV is fixed by the 2.5-V reference and the 12-bit ADC. 20 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Table 3. Voltage Range and Resolution VOLTAGE RANGE (Volts) RESOLUTION (millivolts) 0 to 127.99609 3.90625 0 to 63.99805 1.95313 0 to 31.99902 0.97656 0 to 15.99951 0.48824 0 to 7.99976 0.24414 0 to 3.99988 0.12207 0 to 1.99994 0.06104 0 to 0.99997 0.03052 13.4.4 Voltage Monitoring Up to 12 rail voltages can be monitored using the analog input pins. The input voltage range is 0 V–2.5 V for MON pins 1-6, 59, 62 and 63. Pins 50, 52, 54 and 56 can measure down to 0.2 V. Any voltage between 0 V and 0.2 V on these pins is read as 0.2 V. External resistors can be used to attenuate voltages higher than 2.5 V. The ADC operates continuously, requiring 3.89 μs to convert a single analog input. Each rail is sampled by the sequencing and monitoring algorithm every 400 μs. The maximum source impedance of any sampled voltage should be less than 4 kΩ. The source impedance limit is particularly important when a resistor-divider network is used to lower the voltage applied to the analog input pins. MON1 - MON6 can be configured using digital hardware comparators, which can be used to achieve faster fault responses. Each hardware comparator has four thresholds (two UV (Fault and Warning) and two OV (Fault and Warning)). The hardware comparators respond to UV or OV conditions in about 80 μs (faster than 400 µs for the ADC inputs) and can be used to disable rails or assert GPOs. The only fault response available for the hardware comparators is to shut down immediately. An internal 2.5-V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and 125°C and a tolerance of ±1% between –40°C and 125°C. An external voltage divider is required for monitoring voltages higher than 2.5 V. The nominal rail voltage and the external scale factor can be entered into the Fusion GUI and are used to report the actual voltage being monitored instead of the ADC input voltage. The nominal voltage is used to set the range and precision of the reported voltage according to Table 3. MON1 – MON6 MON1 MON2 . . . . MON13 Analog Inputs (14) M U X 12-bit SAR ADC 200ksps MON1 – MON13 Internal Temp Sense Fast Digital Comparators Glitch Filter Internal 2.5Vref 0.5% Figure 12. Voltage Monitoring Block Diagram Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of 610 μV is fixed by the 2.5-V reference and the 12-bit ADC. 13.4.5 Current Monitoring Current can be monitored using the analog inputs. External circuitry, see Figure 13, must be used in order to convert the current to a voltage within the range of the UCD90124A MONx input being used. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 21 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com If a monitor input is configured as a current, the measurements are smoothed by a sliding-average digital filter. The current for 1 rail is measured every 200μs. If the device is programmed to support 10 rails (independent of current not being monitored at all rails), then each rail's current will get measured every 2ms. The current calculation is done with a sliding average using the last 4 measurements. The filter reduces the probability of false fault detections, and introduces a small delay to the current reading. If a rail is defined with a voltage monitor and a current monitor, then monitoring for undercurrent warnings begins once the rail voltage reaches POWER_GOOD_ON. If the rail does not have a voltage monitor, then current monitoring begins after TON_DELAY. The device supports multiple PMBus commands related to current, including READ_IOUT, which reads external currents from the MON pins; IOUT_OC_FAULT_LIMIT, which sets the overcurrent fault limit; IOUT_OC_WARN_LIMIT, which sets the overcurrent warning limit; and IOUT_UC_FAULT_LIMIT, which sets the undercurrent fault limit. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference contains a detailed description of how current fault responses are implemented using PMBus commands. IOUT_CAL_GAIN is a PMBus command that allows the scale factor of an external current sensor and any amplifiers or attenuators between the current sensor and the MON pin to be entered by the user in milliohms. IOUT_CAL_OFFSET is the current that results in 0 V at the MON pin. The combination of these PMBus commands allows current to be reported in amperes. The example below using the INA196 would require programming IOUT_CAL_GAIN to Rsense(mΩ)×20. UCD90124A MONx VOUT Vin+ AVSS1 Rsense GND Vin3.3V Current Path INA196 V+ Gain = 20V/V Figure 13. Current Monitoring Circuit Example Using the INA196 13.4.6 Remote Temperature Monitoring and Internal Temperature Sensor The UCD90124A has support for internal and remote temperature sensing. The internal temperature sensor requires no calibration and can report the device temperature via the PMBus interface. The remote temperature sensor can report the remote temperature by using a configurable gain and offset for the type of sensor that is used in the application such as a linear temperature sensor (LTS) connected to the analog inputs. External circuitry must be used in order to convert the temperature to a voltage within the range of the UCD90124A MONx input being used. If an input is configured as a temperature, the measurements are smoothed by a sliding average digital filter. The temperature for 1 rail is measured every 100ms. If the device is programmed to support 10 rails (independent of temperature not being monitored at all rails), then each rail's temperature will get measured every 1s. The temperature calculation is done with a sliding average using the last 16 measurements. The filter reduces the probability of false fault detections, and introduces a small delay to the temperature reading. The internal device temperature is measured using a silicon diode sensor with an accuracy of ±5°C and is also monitored using the ADC. Temperature monitoring begins immediately after reset and initialization. 22 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 The device supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1, which reads the internal temperature; READ_TEMPERATURE_2, which reads external temperatures; and OT_FAULT_LIMIT and OT_WARN_LIMIT, which set the overtemperature fault and warning limit. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference contains a detailed description of how temperature-fault responses are implemented using PMBus commands. TEMPERATURE_CAL_GAIN is a PMBus command that allows the scale factor of an external temperature sensor (Figure 14) and any amplifiers or attenuators between the temperature sensor and the MON pin to be entered by the user in °C/V. TEMPERATURE_CAL_OFFSET is the temperature that results in 0 V at the MON pin. The combination of these PMBus commands allows temperature to be reported in degrees Celsius. TMP20 UCD90124A MONx VOUT AVSS1 GND 3.3V V+ Vout = -11.67mV/°C x T + 1.8583 at -40°C < T < 85°C Figure 14. Remote Temperature Monitoring Circuit Example Using the TMP20 13.4.7 Temperature By Host Input If the host system has the option of not using the temperature-sensing capability of the UCD90124A, it can still provide the desired temperature to the UCD90124A through PMBus. The host may have temperature measurements available through I2C or SPI interfaced temperature sensors. The UCD90124A would use the temperature given by the host in place of an external temperature measurement for a given rail. The temperature provided by the host would still be used for detecting overtemperature warnings or faults, logging peak temperatures, input to Boolean logic-builder functions, and feedback for the fan-control algorithms. To write a temperature associated with a rail, the PMBus command used is the READ_TEMPERATURE_2 command. If the host writes that command, the value written will be used as the temperature until another value is written. This is true whether a monitor pin was assigned to the temperature or not. When there is a monitor pin associated with the temperature, once READ_TEMPERATURE_2 is written, the monitor pin is not used again until the part is reset. When there is not a monitor pin associated with the temperature, the internal temperature sensor is used for the temperature until the READ_TEMPERATURE_2 command is written. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 23 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com UCD90124A Faults and Warnings REMOTE TEMP SENSOR I2C I2C or SPI HOST Logged Peak Temperatures READ_TEMPERATURE_2 Boolean Logic Figure 15. Host Writing Temperature to UCD90124A 13.4.8 Fault Responses and Alert Processing The UCD90124A monitors whether the rail stays within a window of normal operation. There are two programmable warning levels (under and over) and two programmable fault levels (under and over). When any monitored voltage goes outside of the warning or fault window, the PMBALERT# pin is asserted immediately, and the appropriate bits are set in the PMBus status registers (Figure 9). Detailed descriptions of the status registers are provided in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference and the PMBus Specification. A programmable glitch filter can be enabled or disabled for each MON input. A glitch filter for an input defined as a voltage can be set between 0 and 102 ms with 400-μs resolution. Fault-response decisions are based on results from the 12-bit ADC. The device cycles through the ADC results and compares them against the programmed limits. The time to respond to an individual event is determined by when the event occurs within the ADC conversion cycle and the selected fault response. PMBUS_CNTRL PIN RAIL 1 EN TON_DELAY[1] TOFF_DELAY[1] TIME BETWEEN RESTARTS TIME BETWEEN RESTARTS MAX_GLITCH_TIME + TOFF_DELAY[1] MAX_GLITCH_TIME + TOFF_DELAY[1] TIME BETWEEN RESTARTS VOUT_OV_FAULT _LIMIT VOUT_UV_FAULT _LIMIT RAIL 1 VOLTAGE RAIL 2 EN POWER_GOOD_ON[1] MAX_GLITCH_TIME MAX_GLITCH_TIME TOFF_DELAY[1] MAX_GLITCH_TIME TON_DELAY[2] TOFF_DELAY[2] RAIL 2 VOLTAGE Rail 1 and Rail 2 are both sequenced “ON” and “OFF” by the PMBUS_CNTRL pin only Rail 2 has Rail 1 as an “ON” dependency Rail 1 has Rail 2 as a Fault Shutdown Slave Rail 1 is set to use the glitch filter for UV or OV events Rail 1 is set to RESTART 3 times after a UV or OV event Rail 1 is set to shutdown with delay for a OV event Figure 16. Sequencing and Fault-Response Timing 24 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 PMBUS_CNTRL PIN TON_DELAY[1] RAIL 1 EN Rail 1 and Rail 2 are both sequenced “ON” and “OFF” by the PMBUS_CNTRL pin only Time Between Restarts Rail 2 has Rail 1 as an “ON” dependency Rail 1 is set to shutdown immediately and RESTART 1 time in case of a Time On Max fault POWER_GOOD_ON[1] POWER_GOOD_ON[1] RAIL 1 VOLTAGE TON_MAX_FAULT_LIMIT[1] TON_DELAY[2] TON_MAX_FAULT_LIMIT[1] RAIL 2 EN RAIL 2 VOLTAGE Figure 17. Maximum Turn-on Fault The configurable fault limits are: TON_MAX_FAULT – Flagged if a rail that is enabled does not reach the POWER_GOOD_ON limit within the configured time VOUT_UV_WARN – Flagged if a voltage rail drops below the specified UV warning limit after reaching the POWER_GOOD_ON setting VOUT_UV_FAULT – Flagged if a rail drops below the specified UV fault limit after reaching the POWER_GOOD_ON setting VOUT_OV_WARN – Flagged if a rail exceeds the specified OV warning limit at any time during startup or operation VOUT_OV_FAULT – Flagged if a rail exceeds the specified OV fault limit at any time during startup or operation MAX_TOFF_WARN – Flagged if a rail that is commanded to shut down does not reach 12.5% of the nominal rail voltage within the configured time Faults are more serious than warnings. The PMBALERT# pin is always asserted immediately if a warning or fault occurs. If a warning occurs, the following takes place: Warning Actions — Immediately assert the PMBALERT# pin — Status bit is flagged — Assert a GPIO pin (optional) — Warnings are not logged to flash A number of fault response options can be chosen from: Fault Responses — Continue Without Interruption: Flag the fault and take no action — Shut Down Immediately: Shut down the faulted rail immediately and restart according to the rail configuration Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 25 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com — Shut Down using TOFF_DELAY: If a fault occurs on a rail, exhaust whatever retries are configured. If the rail does not come back, schedule the shutdown of this rail and all faultshutdown slaves. All selected rails, including the faulty rail, are sequenced off according to their sequence-off dependencies and T_OFF_DELAY times. If Do Not Restart is selected, then sequence off all selected rails when the fault is detected. Restart — Do Not Restart: Do not attempt to restart a faulted rail after it has been shut down. — Restart Up To N Times: Attempt to restart a faulted rail up to 14 times after it has been shut down. The time between restarts is measured between when the rail enable pin is deasserted (after any glitch filtering and turn-off delay times, if configured to observe them) and then reasserted. It can be set between 0 and 1275 ms in 5-ms increments. — Restart Continuously: Same as Restart Up To N Times except that the device continues to restart until the fault goes away, it is commanded off by the specified combination of PMBus OPERATION command and PMBUS_CNTRL pin status, the device is reset, or power is removed from the device. — Shut Down Rails and Sequence On (Re-sequence): Shut down selected rails immediately or after continue-operation time is reached and then sequence-on those rails using sequence-on dependencies and T_ON_DELAY times. 13.4.9 Shut Down All Rails and Sequence on (Resequence) In response to a fault, or a RESEQUENCE command, the UCD90124A can be configured to turn off a set of rails and then sequence them back on. To sequence all rails in the system, then all rails must be selected as faultshutdown slaves of the faulted rail. The rails designated as fault-shutdown slaves will do soft shutdowns regardless of whether the faulted rail is set to stop immediately or stop with delay. Shut-down-all-rails and sequence-on are not performed until retries are exhausted for a given fault. While waiting for the rails to turn off, an error is reported if any of the rails reaches its TOFF_MAX_WARN_LIMIT. There is a configurable option to continue with the resequencing operation if this occurs. After the faulted rail and fault-shutdown slaves sequence-off, the UCD90124A waits for a programmable delay time between 0 and 1275 ms in increments of 5 ms and then sequences-on the faulted rail and fault-shutdown slaves according to the start-up sequence configuration. This is repeated until the faulted rail and fault-shutdown slaves successfully achieve regulation or for a user-selected 1, 2, 3, or 4 times. If the resequence operation is successful, the resequence counter is reset if all of the rails that were resequenced maintain normal operation for one second. Once shut-down-all-rails and sequence-on begin, any faults on the fault-shutdown slave rails are ignored. If there are two or more simultaneous faults with different fault-shutdown slaves, the more conservative action is taken. For example, if a set of rails is already on its second resequence and the device is configured to resequence three times, and another set of rails enters the resequence state, that second set of rails is only resequenced once. Another example – if one set of rails is waiting for all of its rails to shut down so that it can resequence, and another set of rails enters the resequence state, the device now waits for all rails from both sets to shut down before resequencing. 13.4.10 GPIOs The UCD90124A has 22 GPIO pins that can function as either inputs or outputs. Each GPIO has configurable output mode options including open-drain or push-pull outputs that can be actively driven to 3.3 V or ground. There are an additional four pins that can be used as either inputs or PWM outputs but not as GPOs. Table 4 lists possible uses for the GPIO pins and the maximum number of each type for each use. GPIO pins can be dependents in sequencing and alarm processing. They can also be used for system-level functions such as external interrupts, power-goods, resets, or for the cascading of multiple devices. GPOs can be sequenced up or down by configuring a rail without a MON pin but with a GPIO set as an enable. 26 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Table 4. GPIO Pin Configuration Options PIN NAME PIN RAIL EN (12 MAX) GPI (8 MAX) GPO (12 MAX) PWM OUT (12 MAX) MARGIN PWM (10 MAX) FPWM1/GPIO5 17 X X X X X FPWM2/GPIO6 18 X X X X X FPWM3/GPIO7 19 X X X X X FPWM4/GPIO8 20 X X X X X FPWM5/GPIO9 21 X X X X X FPWM6/GPIO10 22 X X X X X FPWM7/GPIO11 23 X X X X X FPWM8/GPIO12 24 X X X X X GPI1/PWM1 31 X X GPI2/PWM2 32 X X GPI3/PWM3 42 X X X GPI4/PWM4 41 X X X GPIO1 11 X X X GPIO2 12 X X X GPIO3 13 X X X GPIO4 14 X X X GPIO13 25 X X X GPIO14 29 X X X GPIO15 30 X X X GPIO16 33 X X X GPIO17 34 X X X GPIO18 35 X X X TCK/GPIO19 36 X X X TDO/GPIO20 37 X X X TDI/GPIO21 38 X X X TMS/GPIO22 39 X X X 13.4.11 GPO Control The GPIOs when configured as outputs can be controlled by PMBus commands or through logic defined in internal Boolean function blocks. Controlling GPOs by PMBus commands (GPIO_SELECT and GPIO_CONFIG) can be used to have control over LEDs, enable switches, etc. with the use of an I2C interface. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for details on controlling a GPO using PMBus commands. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 27 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com 13.4.12 GPO Dependencies GPIOs can be configured as outputs that are based on Boolean combinations of up to two ANDs all ORed together (Figure 18). Inputs to the logic blocks can include the first 8 defined GPOs, GPIs and rail-status flags. One rail status type is selectable as an input for each AND gate in a Boolean block. For a selected rail status, the status flags of all active rails can be included as inputs to the AND gate. _LATCH rail-status types stay asserted until cleared by a MFR PMBus command or by a specially configured GPI pin. The different rail-status types are shown in Table 5. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for complete definitions of rail-status types. The GPO response can be configured to have a delayed assertion or deassertion. Sub block repeated for each of GPI(1:7) GPI_INVERSE(0) GPI_POLARITY(0) GPI_ENABLE(0) 1 AND_INVERSE(0) _GPI(0) GPI(0) _GPI(1:7) _STATUS(0:10) _STATUS(11) _GPO(1:7) There is one STATUS_TYPE_SELECT for each of the two AND gates in a boolean block STATUS_TYPE_SELECT STATUS(0) OR_INVERSE(x) Status Type 0 STATUS(1) Sub block repeated for each of STATUS(0:8) GPOx STATUS_INVERSE(11) Status Type 32 STATUS_ENABLE(11) STATUS(11) ASSERT_DELAY(x) 1 AND_INVERSE(1) DE-ASSERT_DELAY(x) _GPI(0:7) _STATUS(0:11) _GPO(0:7) Sub block repeated for each of GPO(1:7) GPO_INVERSE(0) GPO_ENABLE(0) 1 GPO(0) _GPO(0) Figure 18. Boolean Logic Combinations Figure 19. Fusion Boolean Logic Builder 28 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Table 5. Rail-Status Types for Boolean Logic Rail-Status Types POWER_GOOD IOUT_UC_FAULT TON_MAX_FAULT_LATCH MARGIN_EN TEMP_OT_FAULT TOFF_MAX_WARN_LATCH MRG_LOW_nHIGH TEMP_OT_WARN IOUT_OC_FAULT_LATCH VOUT_OV_FAULT SEQ_ON_TIMEOUT IOUT_OC_WARN_LATCH VOUT_OV_WARN SEQ_OFF_TIMEOUT IOUT_UC_FAULT_LATCH VOUT_UV_WARN FAN_FAULT TEMP_OT_FAULT_LATCH VOUT_UV_FAULT SYSTEM_WATCHDOG_TIMEOUT TEMP_OT_WARN_LATCH TON_MAX_FAULT VOUT_OV_FAULT_LATCH SEQ_ON_TIMEOUT_LATCH TOFF_MAX_WARN VOUT_OV_WARN_LATCH SEQ_OFF_TIMEOUT_LATCH IOUT_OC_FAULT VOUT_UV_WARN_LATCH SYSTEM_WATCHDOG_TIMEOUT_LATCH IOUT_OC_WARN VOUT_UV_FAULT_LATCH 13.4.12.1 GPO Delays The GPOs can be configured so that they manifest a change in logic with a delay on assertion, deassertion, both or none. GPO behavior using delays will have different effects depending if the logic change occurs at a faster rate than the delay. On a normal delay configuration, if the logic for a GPO changes to a state and reverts back to previous state within the time of a delay then the GPO will not manifest the change of state on the pin. In Figure 20 the GPO is set so that it follows the GPI with a 3ms delay at assertion and also at de-assertion. When the GPI first changes to high logic state, the state is maintained for a time longer than the delay allowing the GPO to follow with appropriate logic state. The same goes for when the GPI returns to its previous low logic state. The second time that the GPI changes to a high logic state it retuns to low logic state before the delay time expires. In this case the GPO does not change state. A delay configured in this manner serves as a glitch filter for the GPO. 3ms 3ms GPI GPO 1ms Figure 20. GPO Behavior When Not Ignoring Inputs During Delay The Ignore Input During Delay bit allows to output a change in GPO even if it occurs for a time shorter than the delay. This configuration setting has the GPO ignore any activity from the triggering event until the delay expires. Figure 21 represents the two cases for when ignoring the inputs during a delay. In the case in which the logic changes occur with more time than the delay, the GPO signal looks the same as if the input was not ignored. Then on a GPI pulse shorter than the delay the GPO still changes state. Any pulse that occurs on the GPO when having the Ignore Input During Delay bit set will have a width of at least the time delay. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 29 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 3ms www.ti.com 3ms 3ms 3ms GPI GPO 1ms Figure 21. GPO Behavior When Ignoring Inputs During Delay 13.4.12.2 State Machine Mode Enable When this bit within the GPO_CONFIG command is set, only one of the AND path will be used at a given time. When the GPO logic result is currently TRUE, AND path 0 will be used until the result becomes FALSE. When the GPO logic result is currently FALSE, AND path 1 will be used until the result becomes TRUE. This provides a very simple state machine and allows for more complex logical combinations. 13.4.13 GPI Special Functions There are five special input functions for which GPIs can be used. There can be no more than one pin assigned to each of these functions. • • • • • GPI Fault Enable - When set, the de-assertion of the GPI is treated as a fault. Latched Statuses Clear Source - When a GPO uses a latched status type (_LATCH), you can configure a GPI that will clear the latched status. Input Source for Margin Enable - When this pin is asserted, all rails with margining enabled will be put in a margined state (low or high). Input Source for Margin Low/Not-High - When this pin is asserted all margined rails will be set to Margin Low as long as the Margin Enable is asserted. When this pin is de-asserted the rails will be set to Margin High. Fans Installed - Fan control is enabled while this pin is asserted. The polarity of GPI pins can be configured to be either Active Low or Active High. The first 3 GPIs that are defined regardless of their main purpose will be used for the PIN_SELECTED_RAIL_STATES command. 13.4.14 Power-Supply Enables Each GPIO can be configured as a rail-enable pin with either active-low or active-high polarity. Output mode options include open-drain or push-pull outputs that can be actively driven to 3.3 V or ground. During reset, the GPIO pins are high-impedance except for FPWM/GPIO pins 17–24, which are driven low. External pulldown or pullup resistors can be tied to the enable pins to hold the power supplies off during reset. The UCD90124A can support a maximum of 12 reset enable pins. NOTE GPIO pins that have FPWM capability (pins 17-24) should only be used as power-supply enable signals if the signal is active high. 13.4.15 Cascading Multiple Devices A GPIO pin can be used to coordinate multiple controllers by using it as a power good-output from one device and connecting it to the PMBUS_CNTRL input pin of another. This imposes a master/slave relationship among multiple devices. During startup, the slave controllers initiate their start sequences after the master has completed its start sequence and all rails have reached regulation voltages. During shutdown, as soon as the master starts to sequence-off, it sends the shut-down signal to its slaves. 30 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple controllers, but it does not enforce interdependency between rails within a single controller. The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are regulating at their programmed voltage. The UCD90124A allows GPIOs to be configured to respond to a desired subset of power-good signals. 13.4.16 PWM Outputs 13.4.16.1 FPWM1-8 Pins 17–24 can be configured as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to 125 MHz. FPWMs can be configured as closed-loop margining outputs, fan controllers or general-purpose PWMs. Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a PWM output and the other pin can be used as a GPO. The FPWM pins are actively driven low from reset when used as GPOs. The frequency settings for the FPWMs apply to pairs of pins: • FPWM1 and FPWM2 – same frequency • FPWM3 and FPWM4 – same frequency • FPWM5 and FPWM6 – same frequency • FPWM7 and FPWM8 – same frequency If an FPWM pin from a pair is not used while its companion is set up to function as a PWM, it is recommended to configure the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the system. By setting an FPWM, it automatically enables the other FPWM within the pair if it was not configured for any other functionality. The frequency for the FPWM is derived by dividing down a 250MHz clock. To determine the actual frequency to which an FPWM can be set, must divide 250MHz by any integer between 2 and (214-1). The FPWM duty cycle resolution is dependent on the frequency set for a given FPWM. Once the frequency is known the duty cycle resolution can be calculated as Equation 1. Change per Step (%)FPWM = frequency ÷ (250 × 106 × 16) (1) Take for an example determining the actual frequency and the duty cycle resolution for a 75MHz target frequency. 1. 2. 3. 4. Divide 250MHz by 75MHz to obtain 3.33. Round off 3.33 to obtain an integer of 3. Divide 250MHz by 3 to obtain actual closest frequency of 83.333MHz. Use Equation 1 to determine duty cycle resolution to obtain 2.0833% duty cycle resolution. 13.4.16.2 PWM1-4 Pins 31, 32, 41, and 42 can be used as GPIs or PWM outputs. If configured as PWM outputs, then limitations apply: • PWM1 has a fixed frequency of 10 kHz • PWM2 has a fixed frequency of 1 kHz • PWM3 and PWM4 frequencies can be 0.93 Hz to 7.8125 MHz. The frequency for PWM3 and PWM4 is derived by dividing down a 15.625MHz clock. To determine the actual frequency to which these PWMs can be set, must divide 15.625MHz by any integer between 2 and (224-1). The duty cycle resolution will be dependent on the set frequency for PWM3 and PWM4. The PWM3 or PWM4 duty cycle resolution is dependent on the frequency set for the given PWM. Once the frequency is known the duty cycle resolution can be calculated as Equation 2 Change per Step (%)PWM3/4 = frequency ÷ 15.625 × 106 (2) Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 31 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com To determine the closest frequency to 1MHz that PWM3 can be set to calculate as the following: 1. 2. 3. 4. Divide 15.625MHz by 1MHz to obtain 15.625. Round off 15.625 to obtain an integer of 16. Divide 15.625MHz by 16 to obtain actual closest frequency of 976.563kHz. Use Equation 2 to determine duty cycle resolution to obtain 6.25% duty cycle resolution. All frequencies below 238Hz will have a duty cycle resolution of 0.0015%. 13.4.17 Programmable Multiphase PWMs The FPWMs can be aligned with reference to their phase. The phase for each FPWM is configurable from 0° to 360°. This provides flexibility in PWM-based applications such as power-supply controller, digital clock generation, and others. See an example of four FPWMs programmed to have phases at 0°, 90°, 180° and 270° (Figure 22). Figure 22. Multiphase PWMs 13.4.18 Margining Margining is used in product validation testing to verify that the complete system works properly over all conditions, including minimum and maximum power-supply voltages, load range, ambient temperature range, and other relevant parameter variations. Margining can be controlled over PMBus using the OPERATION command or by configuring two GPIO pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG command in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference describes different available margining options, including ignoring faults while margining and using closed-loop margining to trim the power-supply output voltage one time at power up. 13.4.18.1 Open-Loop Margining Open-loop margining is done by connecting a power-supply feedback node to ground through one resistor and to the margined power supply output (VOUT) through another resistor. The power-supply regulation loop responds to the change in feedback node voltage by increasing or decreasing the power-supply output voltage to return the feedback voltage to the original value. The voltage change is determined by the fixed resistor values and the voltage at VOUT and ground. Two GPIO pins must be configured as open-drain outputs for connecting resistors from the feedback node of each power supply to VOUT or ground. 32 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 MON(1:12) 3.3V UCD90124A POWER SUPPLY 10k W GPIO(1:12) /EN 3.3V Vout VOUT VFB Rmrg_HI V FB GPIO GPIO “0” or “1” VOUT “0” or “1” Rmrg_LO 3. 3V POWER SUPPLY 10k W /EN Vout VOUT VFB VFB Rmrg_HI VOUT . 3.3V Rmrg_LO Open Loop Margining Figure 23. Open-Loop Margining 13.4.18.2 Closed-Loop Margining Closed-loop margining uses a PWM or FPWM output for each power supply that is being margined. An external RC network converts the FPWM pulse train into a DC margining voltage. The margining voltage is connected to the appropriate power-supply feedback node through a resistor. The power-supply output voltage is monitored, and the margining voltage is controlled by adjusting the PWM duty cycle until the power-supply output voltage reaches the margin-low and margin-high voltages set by the user. The voltage setting resolutions will be the same that applies to the voltage measurement resolution (Table 3). The closed loop margining can operate in several modes (Table 6). Given that this closed-loop system has feed back through the ADC, the closed-loop margining accuracy will be dominated by the ADC measurement. The relationship between duty cycle and margined voltage is configurable so that voltage increases when duty cylce increases or decreases. For more details on configuring the UCD90124A for margining, see the Voltage Margining Using the UCD9012x application note (SLVA375). Table 6. Closed Loop Margining Modes Mode Description DISABLE Margining is disabled. ENABLE_TRI_STATE When not margining, the PWM pin is set to high impedance state. ENABLE_ACTIVE_TRIM When not margining, the PWM duty-cycle is continuously adjusted to keep the voltage at VOUT_COMMAND. ENABLE_FIXED_DUTY_CYCLE When not margining, the PWM duty-cycle is set to a fixed duty-cycle. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 33 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com MON(1:12) 3.3V UCD90124A POWER SUPPLY /EN VOUT 10k W GPIO VFB 250 kHz – 1MHz FPWM1 Vout R1 VFB Vmarg R3 R4 C1 Closed Loop Margining R2 Figure 24. Closed-Loop Margining 13.4.19 Fan Control The UCD90124A can control and monitor up to four two-, three- or four-wire fans. Up to four GPIO pins can be used as tachometer inputs. The number of fan tach pulses per revolution for each fan can be entered using the Fusion GUI. A fan speed-fault threshold can be set to trigger an alarm if the measured speed drops below a user-defined value. The two- and three-wire fans are controlled by connecting the positive input of the fan to the specified supply voltage for the fan. The negative input of the fan is connected to the collector or drain of a transistor. The transistor is turned off and on using a GPIO pin. Four-wire fans can be controlled the same way. However, fourwire fans should use the fan PWM input (the fourth wire). It can be driven directly by one of the eight FPWM or the two adjustable PWM outputs. The normal frequency range for the PWM input is 15 kHz to 40 kHz, but the specifications for the fan confirm the interface procedure. Temperature sensor MONx AVSS3 12 V 2--wire Fan 12 V UCD90124A MOSFET turns fan on and off GPIO GND DC Fan GPIO controls MOSFET Figure 25. Two-Wire Fan Connection 34 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Temperature sensor MONx AVSS3 12 V 3--wire Fan 12 V UCD90124A GPIO Fan Tach output to GPI/GPIO for fan speed monitoring TACH MOSFET turns fan on and off GPIO GND DC Fan GPIO controls MOSFET Figure 26. Three-Wire Fan Connection Temperature sensor MONx AVSS3 44-wire Fan 12 V UCD90124A FPWM GPIO 15kHz – 30kHz 3.3V PWM signal changes fan speed with duty cycle 12V PWM TACH 3.3V TACH output to GPI/GPIO for fan speed monitoring DC Fan GND Figure 27. Four-Wire Fan Connection The UCD90124A autocalibrate feature automatically finds and records the turn-on, turn-off and maximum speeds and duty cycles for any fan. Fans have a minimum speed at which they turn on, a turn-off speed that is usually slightly lower than the turn-on speed, and a maximum speed that occurs at slightly less than 100% duty cycle. Each speed has a PWM duty cycle that goes with it. Every fan is slightly different, even if the model numbers are the same. The built-in temperature control algorithms use the actual measured operating speed range instead of 0 RPM to rated speed of the fan to improve the fan control algorithms. The user can choose whether to use autocalibrate or to manually enter the fan data. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 35 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com The UCD90124A can control up to four independent fans as defined in the PMBus standard. When enabled, the FAN-PWM control output provides a digital signal with a configurable frequency and duty cycle, with a duty cycle that is set based on the FAN_COMMAND_1 PMBus command. The PWM can be set to frequencies between 1 Hz and 125 MHz based on the UCD90124A PWM type selected for the fan control. The duty cycle can be set from 0% to 100% with 1% resolution. The FAN-TACH fan-control input counts the number of transitions in the tachometer output from the fan in each 1-second interval. The tachometer can be read by issuing the READ_FAN_SPEED_1 command. The speed is returned in RPMs. Fault limits can also be set for the tachometer speed by issuing the FAN_SPEED_FAULT_LIMIT command and the status checked by issuing the STATUS_FAN_1_2 command. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for a complete description of each command. The UCD90124A also supports two fan control algorithms. 13.4.19.1 Hysteretic Fan Control TempON and TempOFF levels are input by the user. TempON is higher than TempOFF. A GPIO pin is used to turn the fan or fans on at full speed when the monitored temperature reaches TempON and to turn the fans off when the temperature drops below TempOFF. TOT Temp increase above TON : Assert GPO to turn on Fan Temp drops below above TOFF : De-assert GPO to turn off Fan TON TOFF Temp drops below TON : GPO and Fan stays on (hysteresis) MEAS_TEMP Inputs: TON, TOFF, TOT, Update Interval, Rail where MEAS_TEMP is monitored, GPOx pin • System starts up at t = 0 seconds • MEAS_TEMP = 25°C → ambient temp • GPO/PWM is low and Fan is off • Check MEAS_TEMP every 1 second (or 250 msec) • When MEAS_TEMP = TON, set GPO/PWM = 1 → turn fan on • Leave GPO/PWM = 1 unless MEAS_TEMP < TOFF • If MEAS_TEMP is > TON, declare a fault and take the prescribed action. 25°C (tamb) t = 0 sec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 GPO output 0 t = 0 sec 1 MaxSpeed Fan Speed Off t = 0 sec 1 Figure 28. Hysteretic Temperature Control for 2- or 3-wire Fans 13.4.19.2 Set Point Fan Control The second algorithm (Figure 29) uses five control set points that each have a temperature and a fan speed. When the monitored temperature increases above one of the set point temperatures, the fan speed is increased to the corresponding set point value. When the monitored temperature drops below a set point temperature, the fan speed is reduced to the corresponding set point value. The ramp rate for speed can be selected, allowing the user to optimize fan performance and minimize audible noise. The fan speed is varied by changing the duty cycle of a PWM output. For two- and three-wire fans, as the fan is turned on and off, the inertia of the fan smoothes out the fan speed changes, resulting in variable speed operation. This approach can be taken with any fan, but would most likely be used with two- or three-wire fans at a PWM frequency in the 40-Hz to 80-Hz range. Four-wire fans would use the PWM input as described earlier in this section. 36 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 TOT TEMP5, SPD5 TEMP4, SPD4 MEAS_TEMP TEMP3, SPD3 TEMP2, SPD2 TEMP1, SPD1 25°C (Tamb) t = 0 sec 5 10 15 20 Max Speed 25 30 35 40 45 50 • • Target and Ramp Speed Fan Speed ramps down to Target Speed by reducing PWM Duty Cycle SPD3 SPD2 Temp rises above TEMP1 à Target Speed increases to SPD1 60 SPD5 SPD4 Inputs: TOT, Updates Interval, Rail that MEAS_TEMP is being monitored on, PWM pin, PWM freq, PWM temp rate, FANTAC pin, 5x (TEMPn, SPEEDn) setpoints. • System starts up at t = 0 seconds • MEAS_TEMP = 25°C at ambient temp • PWM DUTY_CYCLE = 0% and fan is off • Check MEAS_TEMP every 250 ms (or 1 s) • When MEAS_TEMP > TEMP1: – set SPEED_TARGET = SPEED1 – increase DUTY_CYCLE to DUTY_CYCLE_ON – increase DUTY_CYCLE by ramp rate (10%/second) until SPEED = SPEED_TARGET When MEAS_TEMP > TEMP2: – set SPEED_TARGET = SPEED2 – increase DUTY_CYCLE by ramp rate until SPEED = SPEED_TARGET • Repeat as temperature is increased for each new setpoint • If MEAS_TEMP > TOT, declare a fault and take the prescribed action 55 SPD1 Fan Speed ramps up to Target Speed by increasing PWM Duty Cycle Temp falls below TEMP2 à Target Speed decreases to SPD1 Off (SPD0) t = 0 sec 5 10 15 20 25 30 35 40 45 50 55 60 t = 0 sec 5 10 15 20 25 30 35 40 45 50 55 60 100% PWM duty cycle 0% Figure 29. Temperature and Speed Set Point PWM Control for FourWire Fans If temperature drops - above TEMP4 to below TEMP3 for example – when MEAS_TEMP drops below TEMP4, maintain SPEED4 → do not change the DUTY_CYCLE – when MEAS_TEMP drops below TEMP3, set SPEED_TARGET = SPEED3 – decrease DUTY_CYCLE by ramp rate (10%/second) until SPEED = SPEED_TARGET To turm the fan off when MEAS_TEMP < TEMP1, set SPEED1 = 0 RPM EXAMPLE: MEAS_TEMP = 25°C at ambient temp: • t = 0 to 5 sec: MEAS_TEMP increases from ambient to TEMP1 → increases SPEED_TARGET from SPD0 (Off) to SPD1 → increases DUTY_CYCLE from 0% to DUTYON (30%) → ACTUAL fan speed ramps up from 0 RPM to SPD1. • t = 5 to 10 sec: MEAS_TEMP increases > TEMP2 → increases SPEED_TARGET from SPD1 to SPD2 → increases DUTY_CYCLE → ACTUAL fan speed ramps up from SPD1 to SPD2. • t = 10 to 25 sec: MEAS_TEMP increases to > TEMP5 → SPEED_TARGET increases from SPD2 to SPD5 → DUTY_CYCLE ramps to DUTYMAX → ACTUAL fan speed increases SPD5. • t = 25 to 30 sec: MEAS_TEMP stays > TEMP5 → SPEED_TARGET and DUTY_CYCLE do not change → ACTUAL fan speed stays at SPD5. • t = 30 to 35 sec: MEAS_TEMP decreases to < TEMP4 → SPEED_TARGET drops to SPD4 and then to SPD3 → decreases DUTY_CYCLE → ACTUAL fan speed ramps down from SPD5 to SPD3. • t = 35 to 60 sec: MEAS_TEMP decreases to < TEMP1 → SPEED_TARGET drops to SPD0 → decreases DUTY_CYCLE to DUTYOFF → ACTUAL fan speed ramps down from SPD3 to SPD0 (Off). Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 37 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 www.ti.com 13.4.20 System Reset Signal The UCD90124A can generate a programmable system-reset pulse as part of sequence-on. The pulse is created by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach their respective POWER_GOOD_ON levels plus a programmable delay time. The system-reset delay duration can be programmed as shown in Table 7. See an example of two SYSTEM RESET signals Figure 30. The first SYSTEM RESET signal is configured so that it de-asserts on Power Good On and it asserts on Power Good Off after a given common delay time. The second SYSTEM RESET signal is configured so that it sends a pulse after a delay time once Power Good On is achieved. The pulse width can be configured between 0.001s to 32.256s. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for pulse width configuration details. Power Good On Power Good On Power Good Off POWER GOOD Delay Delay Delay SYSTEM RESET configured without pulse Pulse Pulse SYSTEM RESET configured with pulse Figure 30. System Reset with and without Pulse Setting The system reset can react to watchdog timing. In Figure 31 The first delay on SYSTEM RESET is for the initial reset release that would get a CPU running once all necessary voltage rails are in regulation. The watchdog is configured with a Start Time and a Reset Time. If these times expire without the WDI clearing them then it is expected that the CPU providing the watchdog signal is not operating. The SYSTEM RESET is toggled either using a Delay or GPI Tracking Release Delay to see if the CPU recovers. Power Good On POWER GOOD WDI Watchdog Start Time Watchdog Reset Time Watchdog Start Time Delay Watchdog Reset Time SYSTEM RESET Delay or GPI Tracking Release Delay Figure 31. System Reset with Watchdog Table 7. System-Reset Delay Delay 0 ms 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms 38 Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A UCD90124A www.ti.com SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 Table 7. System-Reset Delay (continued) Delay 64 ms 128 ms 256 ms 512 ms 1.02 s 2.05 s 4.10 s 8.19 s 16.38 s 32.8 s 13.4.21 Watch Dog Timer A GPI and GPO can be configured as a watchdog timer (WDT). The WDT can be independent of power-supply sequencing or tied to a GPIO functioning as a watchdog output (WDO) that is configured to provide a systemreset signal. The WDT can be reset by toggling a watchdog input (WDI) pin or by writing to SYSTEM_WATCHDOG_RESET over I2C. The WDI and WDO pins are optional when using the watchdog timer. The WDI can be replaced by SYSTEM_WATCHDOG_RESET command and the WDO can be manifested through the Boolean Logic defined GPOs or through the System Reset function. The WDT can be active immediately at power up or set to wait while the system initializes. Table 8 lists the programmable wait times before the initial timeout sequence begins. Table 8. WDT Initial Wait Time WDT INITIAL WAIT TIME 0 ms 100 ms 200 ms 400 ms 800 ms 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s 51.2 s 102 s 205 s 410 s 819 s 1638 s The watchdog timeout is programmable from 0.001s to 32.256s. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for details on configuring the watchdog timeout. If the WDT times out, the UCD90124A can assert a GPIO pin configured as WDO that is separate from a GPIO defined as system-reset pin, or it can generate a system-reset pulse. After a timeout, the WDT is restarted by toggling the WDI pin or by writing to SYSTEM_WATCHDOG_RESET over I2C. Submit Documentation Feedback Copyright © 2012–2020, Texas Instruments Incorporated Product Folder Links: UCD90124A 39 UCD90124A SLVSAN8A – JANUARY 2012 – REVISED FEBRUARY 2020 WDI