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UCD90120A
SLVSAN9C – APRIL 2011 – REVISED MARCH 2019
UCD90120A 12-Rail Power Supply Sequencer and Monitor With ACPI Support
•
•
•
•
•
•
2 Applications
•
•
•
•
Industrial / ATE
Telecommunications and Networking Equipment
Servers and Storage Systems
Any System Requiring Sequencing and Monitoring
of Multiple Power Rails
3 Description
The TI Fusion Digital Power™ designer software is
provided for device configuration. This PC-based
graphical user interface (GUI) offers an intuitive
interface for configuring, storing, and monitoring all
system operating parameters.
Device Information(1)
PART NUMBER
PACKAGE
UCD90120A
BODY SIZE (NOM)
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
12V
I12V
12V OUT
3.3V
Supply
INA196
12V OUT
V33DIO
•
Monitor and Sequence 12 Voltage Rails
– All Rails Sampled Every 400 μs
– 12-bit ADC With 2.5-V, 0.5% Internal VREF
– Sequence Based on Time, Rail and Pin
Dependencies
– Four Programmable Undervoltage and
Overvoltage Thresholds per Monitor
Nonvolatile Error and Peak-Value Logging per
Monitor (up to 12 Fault Detail Entries)
Closed-Loop Margining for 10 Rails
– Margin Output Adjusts Rail Voltage to Match
User-Defined Margin Thresholds
Programmable Watchdog Timer and System
Reset
Flexible Digital I/O Configuration
Pin-Selected Rail States
Multiphase PWM Clock Generator
– Clock Frequencies From 15.259 kHz to
125 MHz
– Capability to Configure Independent Clock
Outputs for Synchronizing Switch-Mode Power
Supplies
JTAG and I2C/SMBus/PMBus™ Interfaces
V33A
•
1
Specific power states can be achieved using the PinSelected Rail States feature. This feature allows with
the use of up to 3 GPIs to enable and disable any
rail. This is useful for implementing system low-power
modes and the Advanced Configuration and Power
Interface (ACPI) specification that is used for
hardware devices.
V33D
1 Features
TEMP IC
GPIO
VIN
VMON
/EN
GPIO
3.3V OUT
VMON
1.8V OUT
VMON
0.8V OUT
VMON
I0.8V
VMON
TEMP0.8V
VMON
TEMP12V
3.3V OUT
VOUT
DC-DC 1
VFB
VIN
/EN
GPIO
VOUT
1.8V OUT
LDO1
I12V
VMON
TEMP12V
VMON
TEMP IC
VIN
UCD90120A
WDI from main
processor
GPIO
WDO
GPIO
POWER_GOOD
GPIO
/EN
GPIO
VOUT
TEMP0.8V
0.8V OUT
DC-DC 2
VFB
INA196
PWM
WARN_OC_0.8V_
OR_12V
GPIO
SYSTEM RESET
GPIO
OTHER
SEQUENCER DONE
(CASCADE INPUT)
GPIO
2MHz
I0.8V
Vmarg
Closed Loop
Margining
2
The UCD90120A is a 12-rail PMBus/I C addressable
power-supply sequencer and monitor. The device
integrates a 12-bit ADC for monitoring up to 12
power-supply voltage inputs. Twenty-six GPIO pins
can be used for power supply enables, power-on
reset signals, external interrupts, cascading, or other
system functions. Twelve of these pins offer PWM
functionality. Using these pins, the UCD90120A offers
support for margining, and general-purpose PWM
functions.
I2C/
PMBUS
JTAG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCD90120A
SLVSAN9C – APRIL 2011 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
I2C/SMBus/PMBus Timing Requirements................. 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 18
7.5 Programming .......................................................... 39
8
Application and Implementation ........................ 44
8.1 Application Information............................................ 44
8.2 Typical Application ................................................. 45
9 Power Supply Recommendations...................... 48
10 Layout................................................................... 48
10.1 Layout Guidelines ................................................. 48
10.2 Layout Example .................................................... 48
11 Device and Documentation Support ................. 50
11.1
11.2
11.3
11.4
11.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
50
50
50
50
50
12 Mechanical, Packaging, and Orderable
Information ........................................................... 50
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2015) to Revision C
Page
•
Clarified instructions in Device Configuration and Programming section ............................................................................ 39
•
Added steps 6 through 9 in Design Requirements section .................................................................................................. 46
Changes from Revision A (October 2015) to Revision B
•
Page
Updated Voltage Monitoring section for clarification. ........................................................................................................... 20
Changes from Original (April 2011 ) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added Monitoring section with Votage Monitoring as a subordinate section. ...................................................................... 20
•
Changed Updated Voltage Monitoring section ..................................................................................................................... 20
•
Deleted the end of second paragraph in Voltage Monitoring section that read "'and 62.2....analog inputs". ...................... 20
•
Added Current Monitoring section with Remote Temperature Monitoring And Internal Temperature Sensor as
subsections........................................................................................................................................................................... 21
•
Changed the first sentence of Fault Responses....Processing section ................................................................................ 23
•
Added Run Time Clock section ............................................................................................................................................ 36
•
Changed 'CAUTION' to 'NOTE' and added new first paragraph.......................................................................................... 39
•
Changed second sentence in paragraph under Figure 31 from "For small runs,...GUI". to "For small runs....for this
purpose"................................................................................................................................................................................ 41
•
Added new paragraph in JTAG Interface section................................................................................................................. 43
2
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5 Pin Configuration and Functions
NOTE
The maximum number of configurable rails is 12. The maximum number of configurable
GPIs is 8. The maximum number of configurable Boolean Logic GPOs is 12.
AVSS3
MON9
MON8
PMBUS_ADDR0
PMBUS_ADDR1
MON7
V33FB
NC4
MON13
NC3
MON12
NC2
MON11
NC1
MON10
AVSS1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RGC Package
64-Pin VQFN
Top View
MON1
1
48
AVSS2
MON2
2
47
BPCAP
MON3
3
46
V33A
MON4
4
45
V33D
MON5
5
44
V33DIO2
MON6
6
43
DVSS3
V33DIO1
7
42
PWM3/GPI3
DVSS1
8
41
PWM4/GPI4
RESET
9
40
TRST
TRCK
10
39
TMS/GPIO22
GPIO1
11
38
TDI/GPIO21
GPIO2
12
37
TDO/GPIO20
GPIO3
13
36
TCK/GPIO19
GPIO4
14
35
GPIO18
PMBUS_CLK
15
34
GPIO17
PMBUS_DATA
16
33
GPIO16
21
22
23
24
25
26
27
28
29
30
FWPM4/GPIO8
FPWM5/GPIO9
FPWM6/GPIO10
FPWM7/GPIO11
FPWM8/GPIO12
GPIO13
DVSS2
PMBUS_ALERT
PMBUS_CNTRL
GPIO14
GPIO15
32
20
PWM2/GPI2
19
FPWM3/GPIO7
31
18
FPWM2/GPIO6
PWM1/GPI1
17
FPWM1/GPIO5
UCD90120A
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Simplified Pinout View
V33FB
V33A
BPCAP
V33D
V33DIO1
V33DIO2
7 44 45 46 47 58
1
MON1
TRCK
10
2
MON2
TCK/GPIO19
36
3
MON3
TDO/GPIO20
37
4
MON4
TDI/GPIO21
38
5
MON5
TMS/GPIO22
39
6
MON6
TRST
40
59
MON7
62
MON8
GPIO1
11
63
MON9
GPIO2
12
50
MON10
GPIO3
13
52
MON11
GPIO4
14
54
MON12
GPIO13
25
56
MON13
GPIO14
29
UCD90120A
GPIO15
30
15
PMBUS_CLK
GPIO16
33
16
PMBUS_DATA
GPIO17
34
27
PMBUS_ALERT
GPIO18
35
28
PMBUS_CNTRL
61
PMBUS_ADDR0
FPWM1/GPIO5
17
60
PMBUS_ADDR1
FPWM2/GPIO6
18
FPWM3/GPIO7
19
FPWM5/GPIO9
21
42
PWM3/GPI3
FPWM6/GPIO10
22
41
PWM4/GPI4
FPWM7/GPIO11
23
FPWM8/GPIO12
24
RESET
9
51
NC1
53
NC2
55
NC3
57
NC4
AVSS3
PWM2/GPI2
AVSS1
32
AVSS2
20
DVSS3
FPWM4/GPIO8
DVSS2
PWM1/GPI1
DVSS1
31
8 26 43 48 49 64
4
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SLVSAN9C – APRIL 2011 – REVISED MARCH 2019
Pin Functions
PIN
NAME
I/O
TYPE
NO.
DESCRIPTION
ANALOG MONITOR INPUTS
MON1
1
I
Analog input (0 V–2.5 V)
MON2
2
I
Analog input (0 V–2.5 V)
MON3
3
I
Analog input (0 V–2.5 V)
MON4
4
I
Analog input (0 V–2.5 V)
MON5
5
I
Analog input (0 V–2.5 V)
MON6
6
I
Analog input (0 V–2.5 V)
MON7
59
I
Analog input (0 V–2.5 V)
MON8
62
I
Analog input (0 V–2.5 V)
MON9
63
I
Analog input (0 V–2.5 V)
MON10
50
I
Analog input (0.2 V–2.5 V)
MON11
52
I
Analog input (0.2 V–2.5 V)
MON12
54
I
Analog input (0.2 V–2.5 V)
MON13
56
I
Analog input (0.2 V–2.5 V)
GPIO1
11
I/O
General-purpose discrete I/O
GPIO2
12
I/O
General-purpose discrete I/O
GPIO3
13
I/O
General-purpose discrete I/O
GPIO4
14
I/O
General-purpose discrete I/O
GPIO13
25
I/O
General-purpose discrete I/O
GPIO14
29
I/O
General-purpose discrete I/O
GPIO15
30
I/O
General-purpose discrete I/O
GPIO16
33
I/O
General-purpose discrete I/O
GPIO17
34
I/O
General-purpose discrete I/O
GPIO18
35
I/O
General-purpose discrete I/O
GPIO
PWM OUTPUTS
FPWM1/GPIO5
17
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM2/GPIO6
18
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM3/GPIO7
19
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM4/GPIO8
20
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM5/GPIO9
21
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM6/GPIO1
0
22
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM7/GPIO1
1
23
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM8/GPIO1
2
24
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
PWM1/GPI1
31
I/PWM
Fixed 10-kHz PWM output or GPI
PWM2/GPI2
32
I/PWM
Fixed 1-kHz PWM output or GPI
PWM3/GPI3
42
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM4/GPI4
41
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
PMBus COMM INTERFACE
PMBUS_CLK
15
I/O
PMBus clock (must have pullup to 3.3 V)
PMBUS_DATA
16
I/O
PMBus data (must have pullup to 3.3 V)
PMBALERT#
27
O
PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)
PMBUS_CNTR
L
28
I
PMBus control
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Pin Functions (continued)
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
PMBUS_ADDR
0
61
I
PMBus analog address input. Least-significant address bit
PMBUS_ADDR
1
60
I
PMBus analog address input. Most-significant address bit
JTAG
TRCK
10
O
Test return clock
TCK/GPIO19
36
I/O
Test clock or GPIO
TDO/GPIO20
37
I/O
Test data out or GPIO
TDI/GPIO21
38
I/O
Test data in (tie to Vdd with 10-kΩ resistor) or GPIO
TMS/GPIO22
39
I/O
Test mode select (tie to Vdd with 10-kΩ resistor) or GPIO
TRST
40
I
Test reset – tie to ground with 10-kΩ resistor
INPUT POWER AND GROUNDS
RESET
9
Active-low device reset input. Hold low for at least 2 μs to reset the device.
V33FB
58
Linear Regulator Feedback connection. Leave unconnected.
V33A
46
Analog 3.3-V supply.
V33D
45
Digital core 3.3-V supply.
V33DIO1
7
Digital I/O 3.3-V supply.
V33DIO2
44
Digital I/O 3.3-V supply.
BPCap
47
1.8-V bypass capacitor.
AVSS1
49
Analog ground
AVSS2
48
Analog ground
AVSS3
64
Analog ground
DVSS1
8
Digital ground
DVSS2
26
Digital ground
DVSS3
43
Digital ground
QFP ground
pad
NA
Thermal pad – tie to ground plane.
Refer to the Layout Guidelines section.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Voltage applied at V33D to DVSS
–0.3
3.8
V
Voltage applied at V33A to AVSS
–0.3
3.8
V
–0.3
(V33A +
0.3)
V
–55
150
°C
Voltage applied to any other pin
(2)
Storage temperature, Tstg
(1)
(2)
6
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage during operation (V33D, V33DIO, V33A)
Operating free-air temperature range, TA
MIN
NOM
3
3.3
MAX
–40
Junction temperature, TJ
UNIT
3.6
V
110
°C
125
°C
6.4 Thermal Information
UCD90120A
THERMAL METRIC
(1)
RGC (VQFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
26.4
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
21.2
°C/W
RθJB
Junction-to-board thermal resistance
1.7
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
8.8
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
1.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IV33A
VV33A = 3.3 V
8
mA
IV33DIO
VV33DIO = 3.3 V
2
mA
VV33D = 3.3 V
40
mA
VV33D = 3.3 V, storing configuration parameters in
flash memory
50
mA
Supply current (1)
IV33D
IV33D
ANALOG INPUTS (MON1–MON13)
VMON
Input voltage range
MON1–MON9
MON10–MON13
INL
ADC integral nonlinearity
DNL
ADC differential nonlinearity
Ilkg
Input leakage current
3 V applied to pin
IOFFSET
Input offset current
1-kΩ source impedance
2.5
2.5
–4
4
LSB
2
LSB
-2
MON1–MON9, ground reference
RIN
Input impedance
CIN
Input capacitance
tCONVERT
ADC sample period
14 voltages sampled, 3.89 μsec/sample
ADC 2.5 V, internal reference accuracy
0°C to 125°C
VREF
0
0.2
MON10–MON13, ground reference
–40°C to 125°C
100
–5
5
8
0.5
V
V
nA
μA
MΩ
1.5
3
MΩ
10
pF
400
μs
–0.5%
0.5%
–1%
1%
ANALOG INPUT (PMBUS_ADDRx)
(1)
Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
IBIAS
Bias current for PMBus Addr pins
VADDR_OPEN
Voltage – open pin
PMBUS_ADDR0, PMBUS_ADDR1 open
VADDR_SHORT
Voltage – shorted pin
PMBUS_ADDR0, PMBUS_ADDR1 short to ground
TYP
9
MAX
11
2.26
UNIT
μA
V
0.124
V
Dgnd +
0.25
V
DIGITAL INPUTS AND OUTPUTS
VOL
Low-level output voltage
IOL = 6 mA (2), V33DIO = 3 V
VOH
High-level output voltage
IOH = –6 mA (3), V33DIO = 3 V
VIH
High-level input voltage
V33DIO = 3 V
VIL
Low-level input voltage
V33DIO = 3.5 V
V33DIO
– 0.6
V
2.1
3.6
V
1.4
V
MARGINING OUTPUTS
TPWM_FREQ
MARGINING-PWM frequency
FPWM1-8
PWM3-4
DUTYPWM
MARGINING-PWM duty cycle range
15.260
125000
0.001
7800
0%
100%
kHz
SYSTEM PERFORMANCE
VDDSlew
Minimum VDD slew rate
VDD slew rate between 2.3 V and 2.9 V
VRESET
Supply voltage at which device comes
out of reset
For power-on reset (POR)
tRESET
Low-pulse duration needed at RESET pin To reset device during normal operation
f(PCLK)
Internal oscillator frequency
TA = 125°C, TA = 25°C
240
tretention
Retention of configuration parameters
TJ = 25°C
100
Years
Write_Cycles
Number of nonvolatile erase/write cycles
TJ = 25°C
20
K cycles
(2)
(3)
0.25
V/ms
2.4
V
260
MHz
2
μS
250
The maximum total current, IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
The maximum total current, IOHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
6.6 I2C/SMBus/PMBus Timing Requirements
Timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBus
TA = –40°C to 85°C, 3 V < VDD < 3.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
MIN
FSMB
SMBus/PMBus operating frequency
Slave mode, SMBC 50% duty cycle
2
NOM
UNIT
400
kHz
10
400
kHz
FI2C
I C operating frequency
t(BUF)
Bus free time between start and stop
1.3
μs
t(HD:STA)
Hold time after (repeated) start
0.6
μs
t(SU:STA)
Repeated-start setup time
0.6
μs
t(SU:STO)
Stop setup time
0.6
μs
t(HD:DAT)
Data hold time
0
ns
t(SU:DAT)
Data setup time
100
ns
t(TIMEOUT)
Error signal/detect
t(LOW)
Clock low period
t(HIGH)
Clock high period
Slave mode, SCL 50% duty cycle
MAX
10
Receive mode
See
(1)
See
(2)
35
ms
1.3
μs
0.6
μs
t(LOW:SEXT)
Cumulative clock low slave extend time
See
(3)
25
ms
tf
Clock/data fall time
See
(4)
20 +
0.1 Cb
300
ns
tr
Clock/data rise time
See
(5)
20 +
0.1 Cb
300
ns
(1)
(2)
(3)
(4)
(5)
8
The device times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
Fall time tf = 0.9 VDD to (VILMAX – 0.15)
Rise time tr = (VILMAX – 0.15) to (VIHMIN + 0.15)
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I2C/SMBus/PMBus Timing Requirements (continued)
TA = –40°C to 85°C, 3 V < VDD < 3.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
MIN
Cb
NOM
Total capacitance of one bus line
MAX
UNIT
400
pF
Figure 1. I2C/SMBus Timing Diagram
Start
Stop
TLOW:SEXT
TLOW:MEXT
TLOW:MEXT
TLOW:MEXT
PMB_Clk
Clk ACK
Clk ACK
PMB_Data
Figure 2. Bus Timing in Extended Mode
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2.500
1.3
2.498
1.0
2.496
0.8
2.494
DNL High
0.5
2.492
DNL (LSB)
ADC Reference Voltage (V)
6.7 Typical Characteristics
2.490
2.488
0.3
0.0
-0.3
2.486
DNL Low
-0.5
2.484
-0.8
2.482
-50
-30
-10
10
30
50
70
90
110
130
-1.0
Temperature ( °C)
-50
-30
-10
10
30
50
70
90
110
130
Temperature ( °C)
Figure 3. ADC Reference Voltage vs Temperature
Figure 4. ADC Difference Nonlinearity vs Temperature
2.5
2.0
1.5
INL High
INL (LSB)
1.0
0.5
0.0
INL Low
-0.5
-1.0
-1.5
-50
-30
-10
10
30
50
70
90
110
130
Temperature ( °C)
Figure 5. ADC Integral Nonlinearity vs Temperature
10
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7 Detailed Description
7.1 Overview
Electronic systems that include CPU, DSP, microcontroller, FPGA, ASIC, and so forth, can have multiple voltage
rails and require certain power on/off sequences in order to function correctly. The UCD90120A can control up to
12 voltage rails and ensure correct power sequences during normal condition and fault conditions.
In addition to sequencing, UCD90120A can continuously monitor rail voltages, currents, temperatures, fault
conditions, and report the system health information to a PMBus host, improving systems’ long term reliability.
Also, the UCD90120A can protect electronic systems by responding to power system faults. The fault responses
are conveniently configured by users through Fusion GUI. Fault events are stored in on-chip nonvolatile flash
memory with time stamp in order to assist failure analysis.
System reliability can be improved through four-corner testing during system verification. During four-corner
testing, each voltage rail is required to operate at the minimum and maximum output voltages, commonly known
as margining. UCD90120A can perform closed-loop margining for up to 10 voltage rails. During normal
operation, UCD90120A can also actively trim DC output voltages using the same margining circuitry.
The UCD90120A supports both PMBus- and pin-based control environments. UCD90120A functions as a PMBus
slave. It can communicate with PMBus host with PMBus commands, and control voltage rails accordingly. Also,
UCD90120A can be controlled by up to 8 GPIO configured GPI pins. The GPIs can be used as Boolean logic
input to control up to 12 Logic GPO outputs. Each Logic GPO has a flexible Boolean logic builder. Input signals
of the Boolean logic builder can include GPIs, other Logic GPO outputs, and selectable system flags such as
POWER_GOOD, faults, warnings, etc. A simple state machine is also available for each Logic GPO pin.
The UCD90120A provides additional features such as pin-selected states, system watchdog, system reset,
runtime clock, peak value log, reset counter, and so on. Pin-selected states feature allows users to use up to 3
GPIs to define up to 8 rail states. These states can implement system low-power modes as set out in the
Advanced Configuration and Power Interface (ACPI) specification. Other features will be introduced in the
following sections of this data sheet.
7.2 Functional Block Diagram
Comparators
JTAG
Or
GPIO
I2C/PMBus
General Purpose I/O
(GPIO)
Rail Enables (12 max)
6
Digital Outputs (12 max)
Monitor
Inputs
Digital Inputs (8 max)
13
12-bit
200ksps,
ADC
(0.5% Int. Ref)
22
SEQUENCING ENGINE
Multi-phase PWM (8 max)
FLASH Memory
User Data, Fault
and Peak Logging
BOOLEAN
Logic Builder
Margining Outputs (10 max)
64-pin QFN
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7.3 Feature Description
7.3.1 TI Fusion GUI
The Texas Instruments Fusion Digital Power Designer is provided for device configuration. This PC-based
graphical user interface (GUI) offers an intuitive I2C/PMBus interface to the device. It allows the design engineer
to configure the system operating parameters for the application without directly using PMBus commands, store
the configuration to on-chip nonvolatile memory, and observe system status (voltage, etc). Fusion Digital Power
Designer is referenced throughout the data sheet as Fusion GUI and many sections include screenshots. The
Fusion GUI can be downloaded from www.ti.com.
spacer
7.3.2 PMBus Interface
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
interface that is built on the I2C physical specification. The UCD90120A supports revision 1.1 of the PMBus
standard. Wherever possible, standard PMBus commands are used to support the function of the device. For
unique features of the UCD90120A, MFR_SPECIFIC commands are defined to configure or activate those
features. These commands are defined in the UCD90xxx Sequencer and System Health Controller PMBUS
Command Reference (SLVU352). The most current UCD90xxx PMBus™ Command Reference can be found
within the TI Fusion Digital Power Designer software via the Help Menu (Help, Documentation & Help Center,
Sequencers tab, Documentation section).
This document makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power
System Management Protocol Specification Part II – Command Language, Revision 1.1, dated 5 February 2007.
The specification is published by the Power Management Bus Implementers Forum and is available from
www.pmbus.org.
The UCD90120A is PMBus compliant, in accordance with the Compliance section of the PMBus specification.
The firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT
function. The hardware can support either 100-kHz or 400-kHz PMBus operation.
7.3.3 Rail Configuration
A rail includes voltage, a power-supply enable and a margining output. At least one must be included in a rail
definition. Once the user has defined how the power-supply rails should operate in a particular system, analog
input pins and GPIOs can be selected to monitor and enable each supply (Figure 6).
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Feature Description (continued)
Figure 6. Fusion GUI Pin-Assignment Tab
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Feature Description (continued)
After the pins have been configured, other key monitoring and sequencing criteria are selected for each rail from
the Vout Config tab (Figure 7):
• Nominal operating voltage (Vout)
• Undervoltage (UV) and overvoltage (OV) warning and fault limits
• Margin-low and margin-high values
• Power-good on and power-good off limits
• PMBus or pin-based sequencing control (On/Off Config)
• Rails and GPIs for Sequence On dependencies
• Rails and GPIs for Sequence Off dependencies
• Turn-on and turn-off delay timing
• Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled
or disabled
• Other rails to turn off in case of a fault on a rail (fault-shutdown slaves)
Figure 7. Fusion GUI VOUT-Config Tab
The Synchronize Margins/Limits/PG to Vout checkbox is an easy way to change the nominal operating
voltage of a rail and also update all of the other limits associated with that rail according to the percentages
shown to the right of each entry.
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Feature Description (continued)
The plot in the upper left section of Figure 7 shows a simulation of the overall sequence-on and sequence-off
configuration, including the nominal voltage, the turnon and turnoff delay times, the power-good on and powergood off voltages and any timing dependencies between the rails.
After a rail voltage has reached its POWER_GOOD_ON voltage and is considered to be in regulation, it is
compared against two UV and two OV thresholds in order to determine if a warning or fault limit has been
exceeded. If a fault is detected, the UCD90120A responds based on a variety of flexible, user-configured options.
Faults can cause rails to restart, shut down immediately, sequence off using turnoff delay times or shut down a
group of rails and sequence them back on. Different types of faults can result in different responses.
Fault responses, along with a number of other parameters including user-specific manufacturing information and
external scaling and offset values, are selected in the different tabs within the Configure function of the Fusion
GUI. Once the configuration satisfies the user requirements, it can be written to device SRAM if Fusion GUI is
connected to a UCD90120A using an I2C/PMBus. SRAM contents can then be stored to data flash memory so
that the configuration remains in the device after a reset or power cycle.
The Fusion GUI Monitor page has a number of options, including a device dashboard and a system dashboard,
for viewing and controlling device and system status.
Figure 8. Fusion GUI Monitor Page
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Feature Description (continued)
The UCD90120A also has status registers for each rail and the capability to log faults to flash memory for use in
system troubleshooting. This is helpful in the event of a power-supply or system failure. The status registers
(Figure 9) and the fault log (Figure 10) are available in the Fusion GUI. See the UCD90xxx Sequencer and
System Health Controller PMBus Command Reference (SLVU352) and the PMBus Specification for detailed
descriptions of each status register and supported PMBus commands.
Figure 9. Fusion GUI Rail-Status Register
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Feature Description (continued)
Figure 10. Fusion GUI Flash-Error Log (Logged Faults)
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7.4 Device Functional Modes
7.4.1 Power-Supply Sequencing
The UCD90120A can control the turn-on and turn-off sequencing of up to 12 voltage rails by using a GPIO to set
a power-supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a
sequence-on event by asserting the PMBUS_CNTRL pin or by sending the OPERATION command over the I2C
serial bus. In pin-based designs, the PMBUS_CNTRL pin can also be used to sequence-on and sequence-off.
The auto-enable setting ignores the OPERATION command and the PMBUS_CNTRL pin. Sequence-on is
started at power up after any dependencies and time delays are met for each rail. A rail is considered to be on or
within regulation when the measured voltage for that rail crosses the power-good on (POWER_GOOD_ON (1))
limit. The rail is still in regulation until the voltage drops below power-good off (POWER_GOOD_OFF). In the
case that there isn't voltage monitoring set for a given rail, that rail is considered ON if it is commanded on (either
by
OPERATION
command,
PMBUS
CNTRL
pin,
or
auto-enable)
and
(TON_DELAY
+
TON_MAX_FAULT_LIMIT) time passes. Also, a rail is considered OFF if that rail is commanded OFF and
(TOFF_DELAY + TOFF_MAX_WARN_LIMIT) time passes.
7.4.1.1 Turn-On Sequencing
The following sequence-on options are supported for each rail:
• Monitor only – do not sequence-on
• Fixed delay time (TON_DELAY) after an OPERATION command to turn on
• Fixed delay time after assertion of the PMBUS_CNTRL pin
• Fixed time after one or a group of parent rails achieves regulation (POWER_GOOD_ON)
• Fixed time after a designated GPI has reached a user-specified state
• Any combination of the previous options
The maximum TON_DELAY time is 3276 ms.
7.4.1.2 Turn-Off Sequencing
The following sequence-off options are supported for each rail:
• Monitor only – do not sequence-off
• Fixed delay time (TOFF_DELAY) after an OPERATION command to turn off
• Fixed delay time after deassertion of the PMBUS_CNTRL pin
• Fixed time after one or a group of parent rails drop below regulation (POWER_GOOD_OFF)
• Fixed delay time in response to an undervoltage, overvoltage, or max turn-on fault on the rail
• Fixed delay time in response to a fault on a different rail when set as a fault shutdown slave to the faulted rail
• Fixed delay time in response to a GPI reaching a user-specified state
• Any combination of the previous options
The maximum TOFF_DELAY time is 3276 ms.
(1)
18
In this document, configuration parameters such as Power Good On are referred to using Fusion GUI names. The UCD90xxx
Sequencer and System Health Controller PMBus Command Reference name is shown in parentheses (POWER_GOOD_ON) the first
time the parameter appears.
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Device Functional Modes (continued)
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
POWER_GOOD_ON[1]
POWER_GOOD_OFF[1]
RAIL 1 VOLTAGE
RAIL 2 EN
Rail 1 and Rail 2 are both sequenced “ON”
and “OFF” by the PMBUS_CNTRL pin
only
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as an “OFF” dependency
TON_DELAY[2]
TOFF_DELAY[2]
RAIL 2 VOLTAGE
TON_MAX_FAULT_LIMIT[2]
TOFF_MAX_WARN_LIMIT[2]
Figure 11. Sequence-On and Sequence-Off Timing
7.4.1.3 Sequencing Configuration Options
In addition to the turn-on and turn-off sequencing options, the time between when a rail is enabled and when the
monitored rail voltage must reach its power-good-on setting can be configured using max turn-on
(TON_MAX_FAULT_LIMIT). Max turn-on can be set in 1-ms increments. A value of 0 ms means that there is no
limit and the device can try to turn on the output voltage indefinitely.
Rails can be configured to turn off immediately or to sequence-off according to rail and GPI dependencies, and
user-defined delay times. A sequenced shutdown is configured by selecting the appropriate rail and GPI
dependencies, and turn-off delay (TOFF_DELAY) times for each rail. The turn-off delay times begin when the
PMBUS_CNTRL pin is deasserted, when the PMBus OPERATION command is used to give a soft-stop
command, or when a fault occurs on a rail that has other rails set as fault-shutdown slaves.
Shutdowns on one rail can initiate shutdowns of other rails or controllers. In systems with multiple UCD90120As,
it is possible for each controller to be both a master and a slave to another controller.
7.4.2 Pin-Selected Rail States
This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing
system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used
for operating system directed power management in servers and PCs. In up to 8 system states, the power
system designer can define which rails are on and which rails are off. If a new state is presented on the input
pins, and a rail is required to change state, it will do so with regard to its sequence-on or sequence-off
dependencies.
The OPERATION command is modified when this function causes a rail to change its state. This means that the
ON_OFF_CONFIG for a given rail must be set to use the OPERATION command for this function to have any
effect on the rail state. The first 3 pins configured with the GPI_CONFIG command are used to select 1 of 8
system states. Whenever the device is reset, these pins are sampled and the system state, if enabled, will be
used to update each rail state. When selecting a new system state, changes to the status of the GPIs must not
take longer than 1 microsecond. See the UCD90xxx Sequencer and System Health Controller PMBus Command
Reference for complete configuration settings of PIN_SELECTED_RAIL_STATES.
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Table 1. GPI Selection of System States
GPI 2 STATE
GPI 1 STATE
GPI 0 STATE
SYSTEM
STATE
NOT Asserted
NOT Asserted
NOT Asserted
0
NOT Asserted
NOT Asserted
Asserted
1
NOT Asserted
Asserted
NOT Asserted
2
NOT Asserted
Asserted
Asserted
3
Asserted
NOT Asserted
NOT Asserted
4
Asserted
NOT Asserted
Asserted
5
Asserted
Asserted
NOT Asserted
6
Asserted
Asserted
Asserted
7
7.4.3 Monitoring
The UCD90120A has 13 monitor input pins (MONx) that are multiplexed into a 2.5V referenced 12-bit ADC. The
monitor pins can be configured so that they can measure voltage signals to report voltage, current and
temperature type measurements. A single rail can include all three measurement types, each monitored on
separate MON pins. If a rail has both voltage and current assigned to it, then the user can calculate power for the
rail. Digital filtering applied to each MON input depends on the type of signal. Voltage inputs have no filtering.
Current and temperature inputs have a low-pass filter.
7.4.3.1 Voltage Monitoring
Up to 12 voltages can be monitored using the analog input pins. The input voltage range is 0 V to 2.5 V for
MON1-9. MON10-13 can measure down to 0.2 V. Any voltage between 0 V and 0.2 V on these pins is read as
0.2 V. External resistors can be used to attenuate voltages higher than 2.5 V.
The ADC operates continuously, requiring 3.89 μs to convert a single analog input. Each rail is sampled by the
sequencing and monitoring algorithm every 400 μs. The maximum source impedance of any sampled voltage
should be less than 4 kΩ. The source impedance limit is particularly important when a resistor-divider network is
used to lower the voltage applied to the analog input pins.
MON1 - MON6 can be configured using digital hardware comparators, which can be used to achieve faster fault
responses. Each hardware comparator has four thresholds (two UV (Fault and Warning) and two OV (Fault and
Warning)). The hardware comparators respond to UV or OV conditions in about 80 μs (faster than 400 µs for the
ADC inputs) and can be used to disable rails or assert GPOs. The only fault response available for the hardware
comparators is to shut down immediately.
An internal 2.5-V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and
125°C and a tolerance of ±1% between –40°C and 125°C. An external voltage divider is required for monitoring
voltages higher than 2.5 V. The nominal rail voltage and the external scale factor can be entered into the Fusion
GUI and are used to report the actual voltage being monitored instead of the ADC input voltage. The nominal
voltage is used to set the range and precision of the reported voltage according to Table 2.
MON1 – MON6
MON1
MON2
.
.
.
.
MON13
Analog
Inputs
(12)
M
U
X
Fast Digital
Comparators
12-bit
SAR ADC
200ksps
MON1 – MON13
Glitch
Filter
Internal
2.5Vref
0.5%
Figure 12. Voltage Monitoring Block Diagram
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Table 2. Voltage Range And Resolution
VOLTAGE RANGE
(V)
RESOLUTION
(mV)
0 to 127.99609
3.90625
0 to 63.99805
1.95313
0 to 31.99902
0.97656
0 to 15.99951
0.48824
0 to 7.99976
0.24414
0 to 3.99988
0.12207
0 to 1.99994
0.06104
0 to 0.99997
0.03052
Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of
610 μV is fixed by the 2.5-V reference and the 12-bit ADC.
7.4.3.2 Current Monitoring
Current can be monitored using the analog inputs. External circuitry, see Figure 13, must be used in order to
convert the current to a voltage within the range of the UCD90120A MONx input being used.
If a monitor input is configured as a current, the measurements are smoothed by a sliding-average digital filter.
The current for 1 rail is measured every 200μs. If the device is programmed to support 10 rails (independent of
current not being monitored at all rails), then each rail's current will get measured every 2ms. The current
calculation is done with a sliding average using the last 4 measurements. The filter reduces the probability of
false fault detections, and introduces a small delay to the current reading. If a rail is defined with a voltage
monitor and a current monitor, then monitoring for undercurrent warnings begins once the rail voltage reaches
POWER_GOOD_ON. If the rail does not have a voltage monitor, then current monitoring begins after
TON_DELAY.
The device supports multiple PMBus commands related to current, including READ_IOUT, which reads external
currents from the MON pins; IOUT_OC_FAULT_LIMIT, which sets the overcurrent fault limit;
IOUT_OC_WARN_LIMIT, which sets the overcurrent warning limit; and IOUT_UC_FAULT_LIMIT, which sets the
undercurrent fault limit. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference
contains a detailed description of how current fault responses are implemented using PMBus commands.
IOUT_CAL_GAIN is a PMBus command that allows the scale factor of an external current sensor and any
amplifiers or attenuators between the current sensor and the MON pin to be entered by the user in milliohms.
IOUT_CAL_OFFSET is the current that results in 0 V at the MON pin. The combination of these PMBus
commands allows current to be reported in amperes. The example below using the INA196 would require
programming IOUT_CAL_GAIN to Rsense(mΩ)×20.
UCD90120A
MONx
VOUT
Vin+
AVSS1
Rsense
GND
Vin–
3.3 V
Current Path
INA196
V+
Gain = 20 V/V
Figure 13. Current Monitoring Circuit Example Using The INA196
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7.4.3.3 Remote Temperature Monitoring and Internal Temperature Sensor
The UCD90120A has support for internal and remote temperature sensing. The internal temperature sensor
requires no calibration and can report the device temperature via the PMBus interface. The remote temperature
sensor can report the remote temperature by using a configurable gain and offset for the type of sensor that is
used in the application such as a linear temperature sensor (LTS) connected to the analog inputs.
External circuitry must be used in order to convert the temperature to a voltage within the range of the
UCD90120A MONx input being used.
If an input is configured as a temperature, the measurements are smoothed by a sliding average digital filter. The
temperature for 1 rail is measured every 100ms. If the device is programmed to support 10 rails (independent of
temperature not being monitored at all rails), then each rail's temperature will get measured every 1s. The
temperature calculation is done with a sliding average using the last 16 measurements. The filter reduces the
probability of false fault detections, and introduces a small delay to the temperature reading. The internal device
temperature is measured using a silicon diode sensor with an accuracy of ±5°C and is also monitored using the
ADC. Temperature monitoring begins immediately after reset and initialization.
The device supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1,
which reads the internal temperature; READ_TEMPERATURE_2, which reads external temperatures; and
OT_FAULT_LIMIT and OT_WARN_LIMIT, which set the overtemperature fault and warning limit. The UCD90xxx
Sequencer and System Health Controller PMBus Command Reference contains a detailed description of how
temperature-fault responses are implemented using PMBus commands.
TEMPERATURE_CAL_GAIN is a PMBus command that allows the scale factor of an external temperature
sensor and any amplifiers or attenuators between the temperature sensor and the MON pin to be entered by the
user in °C/V. TEMPERATURE_CAL_OFFSET is the temperature that results in 0 V at the MON pin. The
combination of these PMBus commands allows temperature to be reported in degrees Celsius.
TMP20
UCD90120A
MONx
VOUT
AVSS1
GND
3.3 V
V+
Vout = –11.67mV/°C x T + 1.8583
at –40°C < T < 85°C
Figure 14. Remote Temperature Monitoring Circuit Example Using the TMP20
7.4.3.4 Temperature by Host Input
If the host system has the option of not using the temperature-sensing capability of the UCD90120A, it can still
provide the desired temperature to the UCD90120A through PMBus. The host may have temperature
measurements available through I2C or SPI interfaced temperature sensors. The UCD90120A would use the
temperature given by the host in place of an external temperature measurement for a given rail. The temperature
provided by the host would still be used for detecting overtemperature warnings or faults, logging peak
temperatures, input to Boolean logic-builder functions, and feedback for the fan-control algorithms. To write a
temperature associated with a rail, the PMBus command used is the READ_TEMPERATURE_2 command. If the
host writes that command, the value written will be used as the temperature until another value is written. This is
true whether a monitor pin was assigned to the temperature or not. When there is a monitor pin associated with
the temperature, once READ_TEMPERATURE_2 is written, the monitor pin is not used again until the part is
reset. When there is not a monitor pin associated with the temperature, the internal temperature sensor is used
for the temperature until the READ_TEMPERATURE_2 command is written.
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UCD90120A
Faults and
Warnings
REMOTE
TEMP
SENSOR
I2C
I2C or SPI
HOST
Logged Peak
Temperatures
READ_TEMPERATURE_2
Boolean Logic
Figure 15. Temperature Provided by Host
7.4.4 Fault Responses and Alert Processing
The UCD90120A monitors whether the rail stays within a window of normal operation.. There are two
programmable warning levels (under and over) and two programmable fault levels (under and over). When any
monitored voltage goes outside of the warning or fault window, the PMBALERT# pin is asserted immediately,
and the appropriate bits are set in the PMBus status registers (see Figure 9). Detailed descriptions of the status
registers are provided in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference
and the PMBus Specification.
A programmable glitch filter can be enabled or disabled for each MON input. A glitch filter for an input defined as
a voltage can be set between 0 and 102 ms with 400-μs resolution.
Fault-response decisions are based on results from the 12-bit ADC. The device cycles through the ADC results
and compares them against the programmed limits. The time to respond to an individual event is determined by
when the event occurs within the ADC conversion cycle and the selected fault response.
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
TIME BETWEEN
RESTARTS
MAX_GLITCH_TIME +
TOFF_DELAY[1]
MAX_GLITCH_TIME +
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
VOUT_OV_FAULT _LIMIT
VOUT_UV_FAULT _LIMIT
RAIL 1 VOLTAGE
RAIL 2 EN
POWER_GOOD_ON[1]
MAX_GLITCH_TIME
MAX_GLITCH_TIME
TOFF_DELAY[1]
MAX_GLITCH_TIME
TON_DELAY[2]
TOFF_DELAY[2]
RAIL 2 VOLTAGE
Rail 1 and Rail 2 are both sequenced “ON” and
“OFF” by the PMBUS_CNTRL pin only
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as a Fault Shutdown Slave
Rail 1 is set to use the glitch filter for UV or OV events
Rail 1 is set to RESTART 3 times after a UV or OV event
Rail 1 is set to shutdown with delay for a OV event
Figure 16. Sequencing and Fault-Response Timing
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PMBUS_CNTRL PIN
TON_DELAY[1]
Rail 1 and Rail 2 are both sequenced
“ON” and “OFF” by the PMBUS_CNTRL
pin only
Time Between Restarts
RAIL 1 EN
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 is set to shutdown immediately
and RESTART 1 time in case of a Time
On Max fault
POWER_GOOD_ON[1]
POWER_GOOD_ON[1]
RAIL 1 VOLTAGE
TON_MAX_FAULT_LIMIT[1]
TON_DELAY[2]
TON_MAX_FAULT_LIMIT[1]
RAIL 2 EN
RAIL 2 VOLTAGE
Figure 17. Maximum Turn-On Fault
The configurable fault limits are:
TON_MAX_FAULT –
Flagged if a rail that is enabled does not reach the POWER_GOOD_ON limit within
the configured time
VOUT_UV_WARN –
Flagged if a voltage rail drops below the specified UV warning limit after reaching
the POWER_GOOD_ON setting
VOUT_UV_FAULT –
Flagged if a rail drops below the specified UV fault limit after reaching the
POWER_GOOD_ON setting
VOUT_OV_WARN –
Flagged if a rail exceeds the specified OV warning limit at any time during startup
or operation
VOUT_OV_FAULT –
Flagged if a rail exceeds the specified OV fault limit at any time during startup or
operation
MAX_TOFF_WARN – Flagged if a rail that is commanded to shut down does not reach 12.5% of the
nominal rail voltage within the configured time
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Faults are more serious than warnings. The PMBALERT# pin is always asserted immediately if a warning or fault
occurs. If a warning occurs, the following takes place:
Warning Actions
— Immediately assert the PMBALERT# pin
— Status bit is flagged
— Assert a GPIO pin (optional)
— Warnings are not logged to flash
A number of fault response options can be chosen from:
Fault Responses
— Continue Without Interruption: Flag the fault and take no action
— Shut Down Immediately: Shut down the faulted rail immediately and restart according to the rail
configuration
— Shut Down using TOFF_DELAY: If a fault occurs on a rail, exhaust whatever retries are
configured. If the rail does not come back, schedule the shutdown of this rail and all faultshutdown slaves. All selected rails, including the faulty rail, are sequenced off according to their
sequence-off dependencies and T_OFF_DELAY times. If Do Not Restart is selected, then
sequence off all selected rails when the fault is detected.
Restart
— Do Not Restart: Do not attempt to restart a faulted rail after it has been shut down.
— Restart Up To N Times: Attempt to restart a faulted rail up to 14 times after it has been shut down.
The time between restarts is measured between when the rail enable pin is deasserted (after any
glitch filtering and turn-off delay times, if configured to observe them) and then reasserted. It can
be set between 0 and 1275 ms in 5-ms increments.
— Restart Continuously: Same as Restart Up To N Times except that the device continues to restart
until the fault goes away, it is commanded off by the specified combination of PMBus
OPERATION command and PMBUS_CNTRL pin status, the device is reset, or power is removed
from the device.
— Shut Down Rails and Sequence On (Re-sequence): Shut down selected rails immediately or after
continue-operation time is reached and then sequence-on those rails using sequence-on
dependencies and T_ON_DELAY times.
7.4.5 Shut Down All Rails and Sequence On (Resequence)
In response to a fault, or a RESEQUENCE command, the UCD90120A can be configured to turn off a set of rails
and then sequence them back on. To sequence all rails in the system, then all rails must be selected as faultshutdown slaves of the faulted rail. The rails designated as fault-shutdown slaves will do soft shutdowns
regardless of whether the faulted rail is set to stop immediately or stop with delay. Shut-down-all-rails and
sequence-on are not performed until retries are exhausted for a given fault.
While waiting for the rails to turn off, an error is reported if any of the rails reaches its TOFF_MAX_WARN_LIMIT.
There is a configurable option to continue with the resequencing operation if this occurs. After the faulted rail and
fault-shutdown slaves sequence-off, the UCD90120A waits for a programmable delay time between 0 and 1275
ms in increments of 5 ms and then sequences-on the faulted rail and fault-shutdown slaves according to the
start-up sequence configuration. This is repeated until the faulted rail and fault-shutdown slaves successfully
achieve regulation or for a user-selected 1, 2, 3, or 4 times. If the resequence operation is successful, the
resequence counter is reset if all of the rails that were resequenced maintain normal operation for one second.
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Once shut-down-all-rails and sequence-on begin, any faults on the fault-shutdown slave rails are ignored. If there
are two or more simultaneous faults with different fault-shutdown slaves, the more conservative action is taken.
For example, if a set of rails is already on its second resequence and the device is configured to resequence
three times, and another set of rails enters the resequence state, that second set of rails is only resequenced
once. Another example – if one set of rails is waiting for all of its rails to shut down so that it can resequence,
and another set of rails enters the resequence state, the device now waits for all rails from both sets to shut
down before resequencing.
7.4.6 GPIOs
The UCD90120A has 22 GPIO pins that can function as either inputs or outputs. Each GPIO has configurable
output mode options including open-drain or push-pull outputs that can be actively driven to 3.3 V or ground.
There are an additional four pins that can be used as either inputs or PWM outputs but not as GPOs. Table 3
lists possible uses for the GPIO pins and the maximum number of each type for each use. GPIO pins can be
dependents in sequencing and alarm processing. They can also be used for system-level functions such as
external interrupts, power-goods, resets, or for the cascading of multiple devices. GPOs can be sequenced up or
down by configuring a rail without a MON pin but with a GPIO set as an enable.
Table 3. GPIO Pin Configuration Options
PIN NAME
PIN
RAIL EN
(12 MAX)
GPI
(8 MAX)
GPO
(12 MAX)
PWM OUT
(12 MAX)
MARGIN PWM
(10 MAX)
FPWM1/GPIO5
17
X
X
X
X
X
FPWM2/GPIO6
18
X
X
X
X
X
FPWM3/GPIO7
19
X
X
X
X
X
FPWM4/GPIO8
20
X
X
X
X
X
FPWM5/GPIO9
21
X
X
X
X
X
FPWM6/GPIO10
22
X
X
X
X
X
FPWM7/GPIO11
23
X
X
X
X
X
FPWM8/GPIO12
24
X
X
X
X
X
GPI1/PWM1
31
X
X
GPI2/PWM2
32
X
X
GPI3/PWM3
42
X
X
X
GPI4/PWM4
41
X
X
X
GPIO1
11
X
X
X
GPIO2
12
X
X
X
GPIO3
13
X
X
X
GPIO4
14
X
X
X
GPIO13
25
X
X
X
GPIO14
29
X
X
X
GPIO15
30
X
X
X
GPIO16
33
X
X
X
GPIO17
34
X
X
X
GPIO18
35
X
X
X
TCK/GPIO19
36
X
X
X
TDO/GPIO20
37
X
X
X
TDI/GPIO21
38
X
X
X
TMS/GPIO22
39
X
X
X
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7.4.7 GPO Control
The GPIOs when configured as outputs can be controlled by PMBus commands or through logic defined in
internal Boolean function blocks. Controlling GPOs by PMBus commands (GPIO_SELECT and GPIO_CONFIG)
can be used to have control over LEDs, enable switches, etc. with the use of an I2C interface. See the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference for details on controlling a
GPO using PMBus commands.
7.4.8 GPO Dependencies
GPIOs can be configured as outputs that are based on Boolean combinations of up to two ANDs all ORed
together (Figure 18). Inputs to the logic blocks can include the first 8 defined GPOs, GPIs and rail-status flags.
One rail status type is selectable as an input for each AND gate in a Boolean block. For a selected rail status, the
status flags of all active rails can be included as inputs to the AND gate. _LATCH rail-status types stay asserted
until cleared by a MFR PMBus command or by a specially configured GPI pin. The different rail-status types are
shown in Table 4. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for
complete definitions of rail-status types. The GPO response can be configured to have a delayed assertion or
deassertion; see Figure 19.
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Sub block repeated for each of GPI(1:7)
GPI_INVERSE(0)
GPI_POLARITY(0)
GPI_ENABLE(0)
1
AND_INVERSE(0)
_GPI(0)
GPI(0)
_GPI(1:7)
_STATUS(0:10)
_GPO(1:7)
_STATUS(11)
There is one STATUS_TYPE_SELECT for each of the two AND
gates in a boolean block
STATUS_TYPE_SELECT
STATUS(0)
OR_INVERSE(x)
Status Type 1
STATUS(1)
Sub block repeated for each of STATUS(0:10)
GPOx
STATUS_INVERSE(11)
Status Type 33
ASSERT_DELAY(x)
STATUS_ENABLE(11)
STATUS(15)
1
AND_INVERSE(1)
DE-ASSERT_DELAY(x)
_GPI(0:7)
_STATUS(0:11)
_GPO(0:7)
Sub block repeated for each of GPO(1:7)
GPO_INVERSE(0)
GPO_ENABLE(0)
1
GPO(0)
_GPO(0)
Figure 18. Boolean Logic Combinations
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Figure 19. Fusion Boolean Logic Builder
Table 4. Rail-Status Types for Boolean Logic
Rail-Status Types
POWER_GOOD
IOUT_UC_FAULT
TOFF_MAX_WARN_LATCH
MARGIN_EN
TEMP_OT_FAULT
SEQ_ON_TIMEOUT_LATCH
MRG_LOW_nHIGH
TEMP_OT_WARN
SEQ_OFF_TIMEOUT_LATCH
VOUT_OV_FAULT
SEQ_ON_TIMEOUT
SYSTEM_WATCHDOG_TIMEOUT_LATCH
VOUT_OV_WARN
SEQ_OFF_TIMEOUT
IOUT_OC_FAULT_LATCH
VOUT_UV_WARN
SYSTEM_WATCHDOG_TIMEOUT
IOUT_OC_WARN_LATCH
VOUT_UV_FAULT
VOUT_OV_FAULT_LATCH
IOUT_UC_FAULT_LATCH
TON_MAX_FAULT
VOUT_OV_WARN_LATCH
TEMP_OT_FAULT_LATCH
TOFF_MAX_WARN
VOUT_UV_WARN_LATCH
TEMP_OT_WARN_LATCH
IOUT_OC_FAULT
VOUT_UV_FAULT_LATCH
SEQ_TIMEOUT_LATCH
IOUT_OC_WARN
TON_MAX_FAULT_LATCH
7.4.9 GPO Delays
The GPOs can be configured so that they manifest a change in logic with a delay on assertion, deassertion, both
or none. GPO behavior using delays will have different effects depending if the logic change occurs at a faster
rate than the delay. On a normal delay configuration, if the logic for a GPO changes to a state and reverts back
to previous state within the time of a delay then the GPO will not manifest the change of state on the pin. In
Figure 20 the GPO is set so that it follows the GPI with a 3ms delay at assertion and also at de-assertion. When
the GPI first changes to high logic state, the state is maintained for a time longer than the delay allowing the
GPO to follow with appropriate logic state. The same goes for when the GPI returns to its previous low logic
state. The second time that the GPI changes to a high logic state it retuns to low logic state before the delay time
expires. In this case the GPO does not change state. A delay configured in this manner serves as a glitch filter
for the GPO.
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3ms
GPI
GPO
1ms
Figure 20. GPO Behavior When Not Ignoring Inputs During Delay
The Ignore Input During Delay bit allows to output a change in GPO even if it occurs for a time shorter than the
delay. This configuration setting has the GPO ignore any activity from the triggering event until the delay expires.
Figure 21 represents the two cases for when ignoring the inputs during a delay. In the case in which the logic
changes occur with more time than the delay, the GPO signal looks the same as if the input was not ignored.
Then on a GPI pulse shorter than the delay the GPO still changes state. Any pulse that occurs on the GPO when
having the Ignore Input During Delay bit set will have a width of at least the time delay.
3ms
3ms
3ms
3ms
GPI
GPO
1ms
Figure 21. GPO Behavior When Ignoring Inputs During Delay
7.4.10 State Machine Mode Enable
When this bit within the GPO_CONFIG command is set, only one of the AND path will be used at a given time.
When the GPO logic result is currently TRUE, AND path 0 will be used until the result becomes FALSE. When
the GPO logic result is currently FALSE, AND path 1 will be used until the result becomes TRUE. This provides a
very simple state machine and allows for more complex logical combinations.
7.4.11 GPI Special Functions
There are five special input functions for which GPIs can be used. There can be no more than one pin assigned
to each of these functions.
•
•
•
•
Sequencing Timeout Source - When set, the de-assertion of the GPI is treated as a fault.
Latched Statuses Clear Source - When a GPO uses a latched status type (_LATCH), you can configure a
GPI that will clear the latched status.
Input Source for Margin Enable - When this pin is asserted, all rails with margining enabled will be put in a
margined state (low or high).
Input Source for Margin Low/Not-High - When this pin is asserted all margined rails will be set to Margin
Low as long as the Margin Enable is asserted. When this pin is de-asserted the rails will be set to Margin
High.
The polarity of GPI pins can be configured to be either Active Low or Active High. The first 3 GPIs that are
defined regardless of their main purpose will be used for the PIN_SELECTED_RAIL_STATES command.
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7.4.12 Power-Supply Enables
Each GPIO can be configured as a rail-enable pin with either active-low or active-high polarity. Output mode
options include open-drain or push-pull outputs that can be actively driven to 3.3 V or ground. During reset, the
GPIO pins are high-impedance except for FPWM/GPIO pins 17–24, which are driven low. External pulldown or
pullup resistors can be tied to the enable pins to hold the power supplies off during reset. The UCD90120A can
support a maximum of 12 enable pins.
NOTE
GPIO pins that have FPWM capability (pins 17-24) should only be used as power-supply
enable signals if the signal is active high.
7.4.13 Cascading Multiple Devices
A GPIO pin can be used to coordinate multiple controllers by using it as a power good-output from one device
and connecting it to the PMBUS_CNTRL input pin of another. This imposes a master/slave relationship among
multiple devices. During startup, the slave controllers initiate their start sequences after the master has
completed its start sequence and all rails have reached regulation voltages. During shutdown, as soon as the
master starts to sequence-off, it sends the shut-down signal to its slaves.
A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master
shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple
controllers, but it does not enforce interdependency between rails within a single controller.
The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are
regulating at their programmed voltage. The UCD90120A allows GPIOs to be configured to respond to a desired
subset of power-good signals.
7.4.14 PWM Outputs
7.4.14.1 FPWM1-8
Pins 17–24 can be configured as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to
125 MHz. FPWMs can be configured as closed-loop margining outputs, fan controllers or general-purpose
PWMs.
Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a
PWM output and the other pin can be used as a GPO. The FPWM pins are actively driven low from reset when
used as GPOs.
The frequency settings for the FPWMs apply to pairs of pins:
• FPWM1 and FPWM2 – same frequency
• FPWM3 and FPWM4 – same frequency
• FPWM5 and FPWM6 – same frequency
• FPWM7 and FPWM8 – same frequency
If an FPWM pin from a pair is not used while its companion is set up to function as a PWM, it is recommended to
configure the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the
system. By setting an FPWM, it automatically enables the other FPWM within the pair if it was not configured for
any other functionality.
The frequency for the FPWM is derived by dividing down a 250MHz clock. To determine the actual frequency to
which an FPWM can be set, must divide 250MHz by any integer between 2 and (214-1).
The FPWM duty cycle resolution is dependent on the frequency set for a given FPWM. Once the frequency is
known the duty cycle resolution can be calculated as Equation 1.
Change per Step (%)FPWM = frequency ÷ (250 × 106 × 16) × 100
(1)
Take for an example determining the actual frequency and the duty cycle resolution for a 75MHz target
frequency.
1. Divide 250MHz by 75MHz to obtain 3.33.
2. Round off 3.33 to obtain an integer of 3.
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3. Divide 250MHz by 3 to obtain actual closest frequency of 83.333MHz.
4. Use Equation 1 to determine duty cycle resolution to obtain 2.0833% duty cycle resolution.
7.4.14.2 PWM1-4
Pins 31, 32, 41, and 42 can be used as GPIs or PWM outputs.
If configured as PWM outputs, then limitations apply:
• PWM1 has a fixed frequency of 10 kHz
• PWM2 has a fixed frequency of 1 kHz
• PWM3 and PWM4 frequencies can be 0.93 Hz to 7.8125 MHz.
The frequency for PWM3 and PWM4 is derived by dividing down a 15.625MHz clock. To determine the actual
frequency to which these PWMs can be set, must divide 15.625MHz by any integer between 2 and (224-1). The
duty cycle resolution will be dependent on the set frequency for PWM3 and PWM4.
The PWM3 or PWM4 duty cycle resolution is dependent on the frequency set for the given PWM. Once the
frequency is known the duty cycle resolution can be calculated as Equation 2.
Change per Step (%)PWM3/4 = frequency ÷ 15.625 × 106 × 100
(2)
To determine the closest frequency to 1MHz that PWM3 can be set to calculate as the following:
1.
2.
3.
4.
Divide 15.625MHz by 1MHz to obtain 15.625.
Round off 15.625 to obtain an integer of 16.
Divide 15.625MHz by 16 to obtain actual closest frequency of 976.563kHz.
Use Equation 2 to determine duty cycle resolution to obtain 6.25% duty cycle resolution.
All frequencies below 238Hz will have a duty cycle resolution of 0.0015%.
7.4.15 Programmable Multiphase PWMs
The FPWMs can be aligned with reference to their phase. The phase for each FPWM is configurable from 0° to
360°. This provides flexibility in PWM-based applications such as power-supply controller, digital clock
generation, and others. See an example of four FPWMs programmed to have phases at 0°, 90°, 180° and 270°
(Figure 22).
Figure 22. Multiphase PWMs
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7.4.16 Margining
Margining is used in product validation testing to verify that the complete system works properly over all
conditions, including minimum and maximum power-supply voltages, load range, ambient temperature range,
and other relevant parameter variations. Margining can be controlled over PMBus using the OPERATION
command or by configuring two GPIO pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG
command in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference describes
different available margining options, including ignoring faults while margining and using closed-loop margining to
trim the power-supply output voltage one time at power up.
7.4.16.1 Open-Loop Margining
Open-loop margining is done by connecting a power-supply feedback node to ground through one resistor and to
the margined power supply output (VOUT) through another resistor. The power-supply regulation loop responds to
the change in feedback node voltage by increasing or decreasing the power-supply output voltage to return the
feedback voltage to the original value. The voltage change is determined by the fixed resistor values and the
voltage at VOUT and ground. Two GPIO pins must be configured as open-drain outputs for connecting resistors
from the feedback node of each power supply to VOUT or ground.
MON(1:16)
3.3V
UCD90120A
POWER
SUPPLY
10k W
GPIO(1:16)
/EN
3.3V
Vout
VOUT
VFB
Rmrg_HI
V FB
GPIO
GPIO
“0” or “1”
VOUT
“0” or “1”
Rmrg_LO
3. 3V
POWER
SUPPLY
10k W
/EN
Vout
VOUT
VFB
VFB
Rmrg_HI
VOUT
.
3.3V
Rmrg_LO
Open Loop Margining
Figure 23. Open-Loop Margining
7.4.16.2 Closed-Loop Margining
Closed-loop margining uses a PWM or FPWM output for each power supply that is being margined. An external
RC network converts the FPWM pulse train into a DC margining voltage. The margining voltage is connected to
the appropriate power-supply feedback node through a resistor. The power-supply output voltage is monitored,
and the margining voltage is controlled by adjusting the PWM duty cycle until the power-supply output voltage
reaches the margin-low and margin-high voltages set by the user. The voltage setting resolutions will be the
same that applies to the voltage measurement resolution (Table 2). The closed loop margining can operate in
several modes (Table 5). Given that this closed-loop system has feed back through the ADC, the closed-loop
margining accuracy will be dominated by the ADC measurement. The relationship between duty cycle and
margined voltage is configurable so that voltage increases when duty cylce increases or decreases. For more
details on configuring the UCD90120A for margining, see the Voltage Margining Using the UCD9012x application
note (SLVA375).
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Table 5. Closed Loop Margining Modes
MODE
DESCRIPTION
DISABLE
Margining is disabled.
ENABLE_TRI_STATE
When not margining, the PWM pin is set to high impedance state.
ENABLE_ACTIVE_TRIM
When not margining, the PWM duty-cycle is continuously adjusted to keep the voltage at
VOUT_COMMAND.
ENABLE_FIXED_DUTY_CYCLE
When not margining, the PWM duty-cycle is set to a fixed duty-cycle.
MON(1:16)
3.3V
UCD90120A
POWER
SUPPLY
/EN
VOUT
10k W
GPIO
Vout
VFB
250 kHz – 1MHz
VFB
Vmarg
FPWM1
R1
R3
R4
C1
Closed Loop
Margining
R2
Figure 24. Closed-Loop Margining
7.4.17 System Reset Signal
The UCD90120A can generate a programmable system-reset pulse as part of sequence-on. The pulse is created
by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach
their respective POWER_GOOD_ON levels plus a programmable delay time. The system-reset delay duration
can be programmed as shown in Table 6. See an example of two SYSTEM RESET signals Figure 25. The first
SYSTEM RESET signal is configured so that it de-asserts on Power Good On and it asserts on Power Good Off
after a given common delay time. The second SYSTEM RESET signal is configured so that it sends a pulse after
a delay time once Power Good On is achieved. The pulse width can be configured between 0.001s to 32.256s.
See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for pulse width
configuration details.
Power Good On
Power Good On
Power Good Off
POWER GOOD
Delay
Delay
Delay
SYSTEM RESET
configured without pulse
Pulse
Pulse
SYSTEM RESET
configured with pulse
Figure 25. System Reset With and Without Pulse Setting
The system reset can react to watchdog timing. In Figure 26 The first delay on SYSTEM RESET is for the initial
reset release that would get a CPU running once all necessary voltage rails are in regulation. The watchdog is
configured with a Start Time and a Reset Time. If these times expire without the WDI clearing them then it is
expected that the CPU providing the watchdog signal is not operating. The SYSTEM RESET is toggled either
using a Delay or GPI Tracking Release Delay to see if the CPU recovers.
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Power Good On
POWER GOOD
WDI
Watchdog
Start Time
Watchdog
Reset Time
Watchdog
Start Time
Delay
Watchdog
Reset Time
SYSTEM RESET
Delay or
GPI Tracking Release Delay
Figure 26. System Reset With Watchdog
Table 6. System-Reset Delay
DELAY
0 ms
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1.02 s
2.05 s
4.10 s
8.19 s
16.38 s
32.8 s
7.4.18 Watch Dog Timer
A GPI and GPO can be configured as a watchdog timer (WDT). The WDT can be independent of power-supply
sequencing or tied to a GPIO functioning as a watchdog output (WDO) that is configured to provide a systemreset signal. The WDT can be reset by toggling a watchdog input (WDI) pin or by writing to
SYSTEM_WATCHDOG_RESET over I2C. The WDI and WDO pins are optional when using the watchdog timer.
The WDI can be replaced by SYSTEM_WATCHDOG_RESET command and the WDO can be manifested
through the Boolean Logic defined GPOs or through the System Reset function.
The WDT can be active immediately at power up or set to wait while the system initializes. Table 7 lists the
programmable wait times before the initial timeout sequence begins.
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Table 7. WDT Initial Wait Time
WDT INITIAL WAIT TIME
0 ms
100 ms
200 ms
400 ms
800 ms
1.6 s
3.2 s
6.4 s
12.8 s
25.6 s
51.2 s
102 s
205 s
410 s
819 s
1638 s
The watchdog timeout is programmable from 0.001s to 32.256s. See the UCD90xxx Sequencer and System
Health Controller PMBus Command Reference for details on configuring the watchdog timeout. If the WDT times
out, the UCD90120A can assert a GPIO pin configured as WDO that is separate from a GPIO defined as
system-reset pin, or it can generate a system-reset pulse. After a timeout, the WDT is restarted by toggling the
WDI pin or by writing to SYSTEM_WATCHDOG_RESET over I2C.
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