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XTR305
SBOS913 – FEBRUARY 2018
XTR305 Industrial Analog Current or Voltage Output Driver
1 Features
3 Description
•
•
•
•
•
The XTR305 is a complete output driver for costsensitive industrial and process control applications.
The output can be configured as current or voltage by
the digital I/V select pin. No external shunt resistor is
required. Only external gain-setting resistors and a
loop compensation capacitor are required.
1
•
•
•
•
User-Selectable: Current or Voltage Output
VOUT: ±10 V (up to ±17.5 V at ±20-V supply)
IOUT: ±20 mA (Linear up to ±24 mA)
40-V Supply Voltage
Diagnostic Features:
– Short- or Open-Circuit Fault Indicator Pin
– Thermal Protection
– Overcurrent Protection
No Current Shunt Required
Output Disable for Single Input Mode
Separate Driver and Receiver Channels
Designed For Testability
The separate driver and receiver channels provide
flexibility. The instrumentation amplifier (IA) can be
used for remote voltage sense or as a high-voltage,
high-impedance measurement channel. In voltageoutput mode, a copy of the output current is provided,
allowing calculation of load resistance.
The digital output-selection capability, together with
the error flags and monitor pins, makes remote
configuration and troubleshooting possible. Fault
conditions on the output and on the IA input, as well
as overtemperature conditions, are indicated by the
error flags. The monitoring pins provide continuous
feedback about load power or impedance. For
additional protection, the maximum output current is
limited, and thermal protection is provided.
2 Applications
•
•
•
•
•
•
Motor Drives Analog Outputs: 4-20 mA and ±10 V
PLC Output Programmable Driver
Industrial Cross-Connectors
Industrial High-Voltage I/O
Three-Wire Sensor Current or Voltage Output
±10-V Two- and Four-Wire Voltage Output
U.S. Patent Nos. 7,427,898, 7,425,848, and
7,449,873
The XTR305 is specified over the −40°C to +85°C
industrial temperature range and for supply voltages
up to 40 V, and is operational over the extended
industrial temperature range (−55°C to +125°C).
Device Information(1)
PART NUMBER
PACKAGE
XTR305
VQFN (20)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
CC
XTR305
RIMON
1 kΩ
V-
V+
Current Copy
IMON
ICOPY
IDRV
Input Signal
VIN
(Optional)
SET
OPA
DRV
IAIN+
ROS
RSET
IIA
RG1
IA
VREF
RG2
GND1
M2
GND3
GND2
EFCM
OD
M1
Load
IAIN-
IAOUT
RIA
1 kΩ
RGAIN
Digital
Control
Error
Flags
EFLD
EFOT
DGND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
XTR305
SBOS913 – FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.2 Functional Block Diagrams ..................................... 16
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 20
1
1
1
2
3
4
8
8.1 Application Information............................................ 21
8.2 Typical Application ................................................. 21
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 30
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: Voltage Output Mode....... 5
Electrical Characteristics: Current Output Mode....... 6
Electrical Characteristics: Operational Amplifier
(OPA) ......................................................................... 7
6.8 Electrical Characteristics: Instrumentation Amplifier
(IA) ............................................................................. 8
6.9 Electrical Characteristics: Current Monitor................ 9
6.10 Electrical Characteristics: Power and Digital .......... 9
6.11 Typical Characteristics .......................................... 10
7
Application and Implementation ........................ 21
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
VQFN Package and Heat Sinking.........................
Power Dissipation .................................................
30
30
31
32
11 Device and Documentation Support ................. 33
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 16
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
7.1 Overview ................................................................. 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
February 2018
*
Initial release
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5 Pin Configuration and Functions
3
SET
4
IMON
5
Pad
EFOT
EFLD
EFCM
DGND
16
Exposed
Thermal
Die Pad
on
Underside
(must be
connected
to V-)
6
7
8
9
10
RG2
VIN
17
RG1
2
18
IAIN+
M1
19
IAIN-
1
20
IAOUT
M2
OD
RGW Package
20-Pin VQFN With Thermal Pad
Top View
15
V+
14
NC
13
DRV
12
NC
11
V-
Pin Functions
PIN
NO.
1
NAME
I/O
DESCRIPTION
M2
I
Mode input
2
M1
I
Mode input
3
VIN
I
Noninverting signal input
4
SET
I
Input for gain setting; inverting input
5
IMON
O
Current monitor output
6
IAOUT
O
Instrumentation amplifier signal output
7
IAIN–
I
Instrumentation amplifier inverting input
8
IAIN+
I
Instrumentation amplifier noninverting input
9
RG1
I
Instrumentation amplifier gain resistor
10
RG2
I
Instrumentation amplifier gain resistor
11
V–
-
Negative power supply
12
NC
-
No internal connection
13
DRV
O
Operational amplifier output
14
NC
-
No internal connection
15
V+
-
Positive power supply
16
DGND
-
Ground for digital I/O
17
EFCM
O
Error flag for common mode over range, active low
18
EFLD
O
Error flag for load error, active low
19
EFOT
O
Error flag for over temperature, active low
20
OD
I
Output disable, disabled low
Exposed Pad
-
Exposed thermal pad must be connected to V−
Pad
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VVSP
Signal input terminals
Voltage
(2)
(V−) − 0.5
V
mA
±25
mA
Continuous
Operating temperature
–55
Junction temperature
Storage temperature, Tstg
(1)
(2)
(3)
V
±25
DGND
Output short circuit
UNIT
+44
(V+) + 0.5
Current (2)
(3)
MAX
–55
125
°C
150
°C
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current limited. DRV pin allows a peak current of 50 mA. See the Output Protection section in Application and Implementation.
See Driver Output Disable in Application and Implementation for thermal protection.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Specified temperature range
−40
85
°C
Operating temperature range
−55
125 (1)
°C
(1)
EFOT not connected with OD.
6.4 Thermal Information
XTR305
THERMAL METRIC
(1)
RGW (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
32.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
25.1
°C/W
RθJB
Junction-to-board thermal resistance
12.6
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
12.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS913 – FEBRUARY 2018
6.5 Electrical Characteristics: Voltage Output Mode
All specifications at TA = 25°C, VS = ±20 V, RLOAD = 800 Ω, RSET = 2 kΩ, ROS = 2 kΩ, VREF = 4 V, RGAIN = 10 kΩ, input signal
span 0 V to 4 V, and CC = 100 pF, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Offset voltage, RTI
±0.4
±2.5
mV
dVOS/dT
Offset voltage vs temperature
TA = –40°C to 85°C
±1.6
±10
μV/°C
PSRR
Offset voltage vs power supply
VS = ±5 V to ±22 V
±0.2
±10
μV/V
INPUT VOLTAGE RANGE
Nominal setup for ±10-V output
See Figure 35
Input voltage for linear operation
(V+) − 3
(V−) + 3
V
NOISE
Voltage noise, f = 0.1 Hz to 10 Hz,
RTI
Voltage noise density, f = 1 kHz,
RTI
en
3
μVPP
40
nV/√Hz
OUTPUT
Voltage output swing from rail
IDRV ≤ 15 mA, TA = –40°C to 85°C
Gain nonlinearity vs temperature
IB
±0.01
TA = –40°C to 85°C
Gain error
Gain error vs temperature
TA = –40°C to 85°C
Output impedance, dVDRV/dIDRV
ISC
CLOAD
Output leakage current while output
disabled
OD pin = L
Short-circuit current
TA = –40°C to 85°C
Capacitive load drive
(V+) − 3
(V−) +3
Gain nonlinearity
(1)
, TA = –40°C to 85°C
CC = 10 nF, RC = 15
±15
(2)
Rejection of voltage difference
between GND1 and GND2, RTO
±0.2
±0.1
±1
±0.04
±0.2
±0.2
±1
V
%FS
ppm/°C
%FS
ppm/°C
7
mΩ
30
nA
±20
±24
mA
1
μF
130
dB
300
kHz
FREQUENCY RESPONSE
Bandwidth (3)
SR
Slew rate (2)
−3 dB, G = 5
1
CC = 10 nF, CLOAD = 1 μF, RC = 15 Ω
Settling time (2) (4), 0.1%, small signal VDRV = ±1 V
Overload recovery time
(1)
(2)
(3)
(4)
50% overdrive
0.015
V/μs
8
μs
12
μs
Output leakage includes input bias current of INA.
Refer to Driving Capacitive Loads and Loop Compensation section in Application and Implementation.
Small signal with no capacitive load.
8 μs plus number of chopping periods. See Application and Implementation, Internal Current Sources, Switching Noise, and Settling
Time section.
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6.6 Electrical Characteristics: Current Output Mode
All specifications at TA = 25°C, VS = ±20 V, RLOAD = 800 Ω, RSET = 2 kΩ, ROS = 2 kΩ, VREF = 4 V, input signal span 0 V to 4 V,
and CC = 100 pF, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.4
±2.5
mV
±1.5
±10
μV/°C
±0.2
±10
μV/V
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage vs temperature
PSRR
Input offset voltage vs power supply
Output current < 1 μA
VS = ±5 V to ±22 V
INPUT VOLTAGE RANGE
Nominal setup for ±20-mA output
See Figure 36
Maximum input voltage for linear
operation
(V+) − 3
(V−) + 3
V
NOISE
Voltage noise, f = 0.1Hz to 10Hz,
RTI
en
Voltage noise density, f = 1kHz, RTI
3
μVPP
33
nV/√Hz
OUTPUT
IB
(V+) − 3
Compliance voltage swing from rail
IDRV = ±24 mA
Output conductance (dIDRV/dVDRV)
dVDRV = ±15 V, dIDRV = ±24 mA
Transconductance
See transfer function in Figure 36
Gain error
IDRV = ±24 mA
±0.04
±0.2
%FS
Gain error vs temperature
IDRV = ±24 mA
±3.6
±10
ppm/°C
Linearity error
IDRV = ±24 mA
±0.01
±0.2
%FS
Linearity error vs temperature
IDRV = ±24 mA
±1.5
±10
ppm/°C
Output leakage current while output
disabled
OD pin = L
ISC
Short-circuit current
CLOAD
Capacitive load drive (1) (2)
(V−) +3
0.7
0.6
±24.5
±32
1
V
μA/V
nA
±38.5
mA
μF
FREQUENCY RESPONSE
Bandwidth
SR
(1)
(2)
(3)
6
−3 dB
Slew rate (2)
160
kHz
1.3
mA/μs
Settling time (2) (3), 0.1%, Small
Signal
IDRV = ±2 mA
8
μs
Overload recovery time
CLOAD = 0, 50% overdrive
1
μs
Refer to Driving Capacitive Loads and Loop Compensation section in Application and Implementation.
With capacitive load, the slew rate can be limited by the short circuit current and the load error flag can trigger during slewing.
8 μs plus number of chopping periods. See Application and Implementation, Internal Current Sources, Switching Noise, and Settling
Time section.
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6.7 Electrical Characteristics: Operational Amplifier (OPA)
All specifications at TA = 25°C, VS = ±20 V, and RLOAD = 800 Ω, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±2.5
UNIT
OFFSET VOLTAGE
VOS
Offset voltage, RTI
IDRV = 0 A
±0.4
dVOS/dT
Offset voltage drift
TA = –40°C to 85°C
±1.5
PSRR
Offset voltage vs power supply
VS = ±5 V to ±22 V
±0.2
mV
μV/°C
±10
μV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V+) − 3
(V−) + 3
(V−) + 3 V < VCM < (V+) − 3 V
95
V
126
dB
INPUT BIAS CURRENT
IB
Input bias current
±20
±35
nA
IOS
Input offset current
±0.3
±10
nA
INPUT IMPEDANCE
Differential
108 || 5
Ω || pF
Common-mode
108 || 5
Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V−) + 3 V < VDRV < (V+) − 3 V,
IDRV = ±24 mA
Voltage output swing from rail
IDRV = ±24 mA
Short-circuit current
M2 = high
95
126
dB
OUTPUT
ILIMIT
ILIMIT
ILEAK_DRV
M2 = low
Output leakage current while output
disabled
OD pin = L
(V+) − 3
(V−) + 3
V
±25.5
±32
±38.5
mA
±16
±20
±24
mA
10
pA
2
MHz
1
V/μs
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
G=1
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6.8 Electrical Characteristics: Instrumentation Amplifier (IA)
All specifications at TA = 25°C, VS = ±20 V, RIA = 2 kΩ, and RGAIN = 2 kΩ, unless otherwise noted. See Figure 37.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Offset voltage, RTI
IDRV = 0 A
±0.7
±2.7
mV
dVOS/dT
Offset voltage vs temperature
TA = –40°C to 85°C
±2.4
±10
μV/°C
PSRR
Offset voltage vs power supply
VS = ±5 V to ±22 V
±0.8
±10
μV/V
INPUT VOLTAGE RANGE
VCM
Input voltage range
CMRR
Common-mode rejection ratio
(V+) − 3
(V−) + 3
RTI
100
130
V
dB
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±20
±35
nA
±1
±10
nA
INPUT IMPEDANCE
Differential
105 || 5
Ω || pF
Common-mode
105 || 5
Ω || pF
TRANSCONDUCTANCE (Gain) (1)
Transconductance error
IAOUT = ±2.4 mA, (V−) + 3 V <
VIAOUT < (V+) − 3 V
Transconductance error vs
temperature
TA = –40°C to 85°C
Linearity error
(V−) + 3 V < VIAOUT < (V+) − 3 V
±0.04
±0.1
±0.2
±0.01
Input bias current to G1, G2
Input offset current to G1, G2 (2)
%FS
ppm/°C
±0.1
%FS
±20
nA
±1
nA
OUTPUT
ILIMIT
(V+) − 3
Output swing to the rail
IAOUT = ±2.4 mA
Output impedance
IAOUT = ±2.4 mA
600
mΩ
M2 = High
±7.2
mA
M2 = Low
±4.5
mA
Short-circuit current
(V−) + 3
V
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
G = 1, RGAIN = 10 kΩ, RIA = 5 kΩ
1
MHz
SR
Slew rate
G = 1, RGAIN = 10 kΩ, RIA = 5 kΩ
1
V/μs
Settling time (3), 0.1%
IAOUT = ±40 μA, RGAIN = 10 kΩ,
RIA = 5 kΩ, CL = 100 pF
6
μs
Overload recovery time, 50%
RGAIN = 10 kΩ, RIA = 15 kΩ,
CL = 100 pF
10
μs
(1)
(2)
(3)
8
Use equation: IAOUT = 2 (IAIN+ − IAIN−) / RGAIN
See typical characteristics curve (Figure 3).
6 μs plus number of chopping periods. See Application and Implementation, Internal Current Sources, Switching Noise, and Settling
Time.
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6.9 Electrical Characteristics: Current Monitor
All specifications at TA = 25°C and VS = ±20 V, unless otherwise noted. See Figure 37.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±30
±100
UNIT
OUTPUT
IOS
Offset current
IDRV = 0 A
dIOS/dT
Offset current drift
TA = –40°C to 85°C
±0.05
PSRR
Offset current vs power supply
VS = ±5 V to ±22 V
±0.1
Monitor output swing to the rail
IMON = ±2.4 mA
Monitor output impedance
IMON = ±2.4 mA
nA
nA/°C
±10
nA/V
(V+) − 3
(V−) + 3
V
200
MΩ
MONITOR CURRENT GAIN (1)
(1)
Current gain error
IDRV = ±24 mA
Current gain error vs temperature
IDRV = ±24 mA, TA = –40°C to 85°C
Linearity error
IDRV = ±24 mA
Linearity error vs temperature
IDRV = ±24 mA, TA = –40°C to 85°C
±0.04
±0.12
±3.6
±0.01
%FS
ppm/°C
±0.1
±1.5
%FS
ppm/°C
Use equation: IMON = IDRV / 10
6.10 Electrical Characteristics: Power and Digital
All specifications at TA = 25°C and VS = ±20 V, unless otherwise noted. See Figure 37.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
IQ
Specified voltage range
±5
±20
V
Operating voltage range
±5
±22
V
2.3
mA
2.8
mA
Quiescent current
IDRV = IAOUT = 0 A
Quiescent current over temperature
TA = –40°C to 85°C
1.8
THERMAL FLAG (EFOT) OUTPUT
Alarm (EFOT pin LOW)
140
°C
Return to normal operation (EFOT
pin HIGH)
125
°C
VIL low-level input voltage
≤ 0.8
V
VIH high-level input voltage
> 1.4
V
±1
μA
−1.2
μA
DIGITAL INPUTS (M1, M2, OD)
Input current
DIGITAL OUTPUTS (EFLD, EFCM, EFOT)
IOH high-level leakage current (opendrain)
VOL low-level output voltage
IOL = 5 mA
0.8
V
VOL low-level output voltage
IOL = 2.8 mA
0.4
V
−25
μA
DIGITAL GROUND PIN (1)
Current input
(1)
M1 = M2 = L, OD = H, all digital
outputs H
Use equation: (V−) ≤ DGND ≤ (V+) − 7 V
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6.11 Typical Characteristics
at TA = 25°C and V+ = ±20 V, unless otherwise noted
1.90
3.0
1.88
2.5
1.86
1.84
IQ (mA)
IQ (mA)
2.0
1.5
1.0
1.82
1.80
1.78
1.76
1.74
0.5
1.72
1.70
0
-50
0
-25
25
50
75
100
10
125
15
20
Figure 1. Quiescent Current vs Temperature
30
35
40
45
Figure 2. Quiescent Current vs Supply Voltage
0
2.2
IDRV = +24mA
IDRV = -24mA
-5
½VS - VOUT½ (V)
2.0
-10
IB (nA)
25
Total Supply Voltage (V)
Temperature (°C)
-15
-20
IDRV = +20mA
1.8
1.6
IDRV = +10mA
1.4
IDRV = -20mA
-25
IDRV = -10mA
1.2
-30
1.0
-50
0
-25
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
Temperature (°C)
(VIN, SET, IAIN+, IAIN−, RG1, RG2)
Figure 3. Input Bias Current vs Temperature
180
0
160
-20
140
-40
60
-100
60
-120
-140
40
Gain
-160
20
-20
0.001 0.01 0.1
1
10
100
1k
10k 100k 1M
-200
10M
0
-180
RIA = 5kW
-20
-225
RIA = 1kW
Gain
Phase
-40
1
10
100
1k
10k
100k
1M
-270
10M
Frequency (Hz)
Frequency (Hz)
Figure 5. OPA Gain and Phase vs Frequency
10
-135
RIA = 10kW
-180
0
-90
RIA = 50kW
Phase (°)
80
-45
RIA = 500kW
40
Phase (°)
-80
0
RGAIN = 10kW
-60
Phase
100
20
80
Gain (dB)
120
Gain (dB)
Figure 4. OPA Output Swing to Rail vs Temperature
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Figure 6. IA Gain and Phase vs Frequency
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Typical Characteristics (continued)
160
140
140
120
120
CMRR, PSRR (dB)
CMRR, PSRR (dB)
at TA = 25°C and V+ = ±20 V, unless otherwise noted
100
PSRR80
60
PSRR+
40
PSRR+
80
PSRR60
CMRR
40
CMRR
20
20
0
0
10
100
1k
10k
1
100k
10
1k
10k
Frequency (Hz)
Figure 7. OPA CMRR and PSRR vs Frequency
Figure 8. IA CMRR and PSRR vs Frequency
IOUT = ±200mA
G=8
CL = 100nF || RL = 800W
CC = 4.7nF
RSET = 1kW
RGAIN = 10kW
See Figure 3
200ms/div
100k
IOUT = ±20mA
G=8
CL = 100nF || RL = 800W
CC = 4.7nF
RSET = 1kW
RGAIN = 10kW
See Figure 3
200ms/div
Figure 10. Large-Signal Step Response
Current Mode
5V/div
Figure 9. Small-Signal Step Response
Current Mode
50mV/div
100
Frequency (Hz)
10V/div
1
100mV/div
100
G=5
CL = 100nF || RL = 800W
CC = 4.7nF
RSET = 1kW
RGAIN = 10kW
See Figure 2
200ms/div
G=5
CL = 100nF || RL = 800W
CC = 4.7nF
RSET = 1kW
RGAIN = 10kW
See Figure 2
200ms/div
Figure 11. Small-Signal Step Response
Voltage Mode
Figure 12. Large-Signal Step Response
Voltage Mode
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Typical Characteristics (continued)
at TA = 25°C and V+ = ±20 V, unless otherwise noted
1M
G=5
10k
1mV/div
Noise (nV/ÖHz)
100k
1k
100
10
1
1
10
100
1k
10k
1s/div
100k
Frequency (Hz)
Figure 13. Input-Referred Noise Spectrum
Voltage Output Mode
Figure 14. Input-Referred 0.1-Hz to 10-Hz Noise
Voltage Output Mode
1M
10k
1mV/div
Input- Referred Noise (nV/ÖHz)
G = 10
100k
1k
100
10
1
1
10
100
1k
10k
100k
1s/div
Frequency (Hz)
Figure 15. Input-Referred Noise Spectrum
Current Output Mode
Figure 16. Input-Referred 0.1-Hz to 10-Hz Noise
Current Output Mode
1M
10k
1mV/div
Input-Referred Noise (nV/ÖHz)
G = 20
100k
1k
100
10
1
1
10
100
1k
10k
1s/div
100k
Frequency (Hz)
Figure 17. IA Input-Referred Noise Spectrum
12
Figure 18. IA Input-Referred 0.1-Hz to 10-Hz Noise
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Typical Characteristics (continued)
at TA = 25°C and V+ = ±20 V, unless otherwise noted
18
30
Percent of Population (%)
14
12
10
8
6
4
2
0
20
15
10
5
3.0
2.4
1.8
1.2
0.6
0
-0.6
Offset Voltage (mV)
Offset Voltage (mV)
Figure 19. OPA Offset Voltage Distribution
Figure 20. IA Offset Voltage Distribution
40
35
Percent of Population (%)
50
40
30
20
10
30
25
20
15
10
5
0
10
8
6
4
2
0
-2
-4
-6
-10
10
8
6
4
2
0
-2
-4
-6
-10
-8
0
Offset Voltage Drift (mV/°C)
Offset Voltage Drift (mV/°C)
Figure 21. OPA Offset Voltage Drift Distribution
Figure 22. IA Offset Voltage Drift Distribution
30
40
Percent of Population (%)
35
30
25
20
15
10
5
25
20
15
10
5
1000
800
600
400
200
0
-200
-400
-600
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-800
0
0
-1000
Percent of Population (%)
-1.2
-1.8
-2.4
-3.0
2.0
1.6
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
-2.0
0
60
Percent of Population (%)
25
-8
Percent of Population (%)
16
Gain Error (ppm)
Gain Error (ppm)
Figure 23. Voltage Mode Gain Error Distribution
Figure 24. Current Mode Gain Error Distribution
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Typical Characteristics (continued)
60
60
50
50
Percent of Population (%)
40
30
20
10
30
20
10
1000
800
600
400
200
Nonlinearity (ppm)
Figure 25. Voltage Mode Nonlinearity Distribution
Figure 26. Current Mode Nonlinearity Distribution
60
10
8
6
-10
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
0
-0.6
0
-0.8
10
-1.0
10
4
20
2
20
30
0
30
40
-2
40
-4
50
50
-6
Percent of Population (%)
60
Gain Error Drift (ppm/°C)
Gain Error Drift (ppm/°C)
Figure 28. Current Mode Gain Error Drift Distribution
Figure 27. Voltage Mode Gain Error Drift Distribution
80
100
70
90
Percent of Population (%)
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
10
8
6
4
2
0
-2
-4
-6
-8
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
-10
Percent of Population (%)
0
Nonlinearity (ppm)
70
Nonlinearity Drift (ppm/°C)
Nonlinearity Drift (ppm/°C)
Figure 29. Voltage Mode Nonlinearity Drift Distribution
14
-200
-400
-800
-1000
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-600
0
0
Percent of Population (%)
40
-8
Percent of Population (%)
at TA = 25°C and V+ = ±20 V, unless otherwise noted
Figure 30. Current Mode Nonlinearity Drift Distribution
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Typical Characteristics (continued)
at TA = 25°C and V+ = ±20 V, unless otherwise noted
36
-16
34
-18
32
-22
ILIMIT (mA)
ILIMIT (mA)
30
28
26
24
Voltage Mode
22
-24
-26
-28
-30
20
-32
18
-34
16
Current Mode
-36
-50
0
-25
25
50
75
100
125
-50
-25
25
0
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 31. Positive Current Limit vs Temperature
Figure 32. Negative Current Limit vs Temperature
0.025
0.025
+25°C
0
Nonlinearity (%)
-0.025
-55°C
+25°C
-55°C
0
Nonlinearity (%)
Voltage Mode
-20
Current Mode
+85°C
-0.050
-0.025
+125°C
+85°C
-0.050
-0.075
-0.075
+125°C
-0.100
-24 -20 -16 -12 -8
-4
0
4
8
12
16
20
24
-0.100
-24 -20 -16 -12 -8
-4
0
4
8
12
16
20
24
Output Current (mA)
Output Current (mA)
(±24-mA End Point Calibration)
(±20-mA End Point Calibration)
Figure 33. Nonlinearity vs Output Current
Figure 34. Nonlinearity vs Output Current
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7 Detailed Description
7.1 Overview
Built on a robust high-voltage BiCMOS process, the XTR305 is designed to interface the 5-V or 3-V supply
domain used for processors, signal converters, and amplifiers to the high-voltage and high-current industrial
signal environment. The device is specified for up to ±20-V supply, but can also be powered asymmetrically (for
example, +24 V and −5 V). It is designed to allow insertion of external circuit protection elements and drive large
capacitive loads.
7.2 Functional Block Diagrams
CC
XTR305
V-
V+
Current Copy
IMON
RIMON
1 kΩ
Input Signal
VIN = 0 V to 4.0 V
GND3
ICOPY
IDRV
VIN
OPA
SET
DRV
IAIN+
ROS
RSET
IIA
RG1
IA
RG2
Transfer Function:
RGAIN
Load
VOUT =
RGAIN
2
(
VIN
RSET
+
VIN - VREF
ROS
)
VREF = 4.0 V
IAIN-
IAOUT
H
L
L
EFCM
OD
M1
M2
Digital
Control
Error
Flags
EFLD
EFOT
DGND
DVGND
GND2
GND1
Copyright © 2017, Texas Instruments Incorporated
Figure 35. Standard Circuit for Voltage Output Mode
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Functional Block Diagrams (continued)
CC
XTR305
V-
V+
Current Copy
IMON
ICOPY
IDRV
Input Signal
VIN = 0 V to 4.0 V
VIN
OPA
SET
DRV
Transfer Function:
IAIN+
ROS
RSET
IOUT = 10
IIA
RG1
(
VIN
RSET
+
VIN - VREF
ROS
(
IA
RG2
VREF = 4.0 V
IAIN-
IAOUT
H
L
H
GND1
EFCM
OD
M1
M2
Digital
Control
Error
Flags
IOUT
EFLD
EFOT
DGND
GND2
Copyright © 2017, Texas Instruments Incorporated
Figure 36. Standard Circuit for Current Output Mode
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Functional Block Diagrams (continued)
Feedback
Network
XTR305
V-
V+
Current Copy
IMON
ICOPY
IDRV
GND3
VIN
Input Signal
OPA
SET
DRV
IAIN+
RSET
IIA
RG1
IA
RG2
GND1
IAIN-
IAOUT
EFCM
OD
RIA
H
M1
M2
RGAIN
Digital
Control
Error
Flags
EFLD
EFOT
DGND
GND3
Copyright © 2017, Texas Instruments Incorporated
Figure 37. Standard Circuit for Externally Configured Mode
7.3 Feature Description
7.3.1 Functional Features
The XTR305 provides two basic functional blocks: an instrumentation amplifier (IA) and a driver that is a unique
operational amplifier (OPA) for current or voltage output. This combination represents an analog output stage
which can be digitally configured to provide either current or voltage output to the same terminal pin.
Alternatively, it can be configured for independent measurement channels.
Three open collector error signals are provided to indicate output related errors such as overcurrent or open-load
(EFLD) or exceeding the common-mode input range at the IA inputs (EFCM). An overtemperature flag (EFOT) can
be used to control output disable to protect the circuit. The monitor outputs (IMON and IAOUT) and the error flags
offer optimal testability during operation and configuration. The IMON output represents the current flowing into the
load in voltage output mode, while the IAOUT represents the voltage across the connectors in current output
mode. Both monitor outputs can be connected together when used in current or voltage output mode because
the monitor signals are multiplexed accordingly.
7.3.2 Current Monitor
In current output mode (M2 = high), the XTR305 provides high output impedance. A precision current mirror
generates an exact 1/10th copy of the output current and this current is either routed to the summing junction of
the OPA to close the feedback loop (in the current output mode) or to the IMON pin for output current monitoring in
other operating modes.
The high accuracy and stability of this current split results from a cycling chopper technique. This design
eliminates the need for a precise shunt resistor or a precise shunt voltage measurement, which would require
high common-mode rejection performance.
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Feature Description (continued)
During a saturation condition of the DRV output (the error flag is active), the monitor output (IMON) shows a
current peak because the loop opens. Glitches from the current mirror chopper appear during this time in the
monitor signal. This part of the signal cannot be used for measurement.
7.3.3 Error Flags
The XTR305 is designed for testability of its proper function and allows observation of the conditions at the load
connection without disrupting service.
If the output signal is not in accordance to the transfer function, an error flag is activated (limited by the dynamic
response capabilities). These error flags are in addition to the monitor outputs, IMON and IAOUT, which allow the
momentary output current (in voltage mode) or output voltage (in current mode) to be read back.
This combination of error flag and monitor signal allows easy observation of the XTR305 for function and working
condition, providing the basis for not only remote control, but also for remote diagnosis.
All error flags of the XTR305 have open collector outputs with a weak pullup of approximately 1 μA to an internal
5 V. External pullup resistors to the logic voltage are required when driving 3-V or 5-V logic.
The output sink current should not exceed 5 mA. This is just enough to directly drive optical-couplers, but a
current-limiting resistor is required.
There are three error flags:
1. IA Common-Mode Over Range (EFCM): goes low as soon as the inputs of the IA reach the limits of the
linear operation for the input voltage. This flag shows noise from the saturated current mirrors which can be
filtered with a capacitor to GND.
2. Load Error (EFLD): indicates fault conditions driving voltage or current into the load. In voltage output mode
it monitors the voltage limits of the output swing and the current limit condition caused from short or low load
resistance. In current output mode it indicates a saturation into the supply rails from a high load resistance or
open load.
3. Overtemperature Flag (EFOT): a digital output that goes low if the chip temperature reaches a temperature
of 140°C and resets as soon as it cools down to 125°C. It does not automatically shut down the output; it
allows the user system to take action on the situation. If desired, this output can be connected to output
disable (OD) which disables the output and therefore removes the source of power. This connection acts like
an automatic shut down, but requires a 2.2-kΩ external pullup resistor to safely override the internal current
sources. The IA channel is not affected, which allows continuous observation of the voltage at the output.
7.3.4 Power On/Off Glitch
When power is turned on or off, most analog amplifiers generate some glitching of the output because of internal
circuit thresholds and capacitive charges. Characteristics of the supply voltage, as well as its rise and fall time,
directly influence output glitches. Load resistance and capacitive load also affect the amplitude.
The output disable control (OD) cannot fully suppress glitches during power-on and power-off, but reduces the
energy significantly. The glitch consists of a small amount of current and capacitive charge (voltage) that reacts
with the resistive and capacitive load. The bias current of the IA inputs that are normally connected to the output
also generate a voltage across the load.
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Feature Description (continued)
Figure 38 indicates no glitches when transitioning between disable and enable. This measurement is made with
a load resistance of 1 kΩ and tested in the circuit configuration of Figure 40.
Output
0.5V/div
OD
2.0V/div
Time (10ms/div)
Figure 38. Output Signal During Toggle of OD
When the power is off or with low supply, the output is diode clamped to the momentary supply voltage, but can
float while output disabled within those limits unless terminated. Only an external switch (relays or opto-relays)
can isolate the output under such conditions. Refer to Figure 39 for an illustration of this configuration. The same
consideration applies if low impedance zero output is required, even during power off.
VEN_OPTO
0 V to 5 V
CC
47 nF
RLED
5 k:
XTR305
+
RC
15 :
DRV
OPA
±
SOUT
CPC1017N
4
1
C4
100 nF
IAIN+
+
RG1
IA
RG2
±
ILED
0 mA to 1
mA
R6
2.2 k:
RGAIN
10 k:
C5
10 nF
R7
2.2 k:
3
2
RLOAD
1 k:
IAIN±
Copyright © 2017, Texas Instruments Incorporated
Figure 39. Example for Opto-Relay Output Isolation
7.4 Device Functional Modes
The XTR305 has a three functional modes: voltage output mode as shown in Figure 35, current output mode as
shown in Figure 36, and externally configured mode as shown in Figure 37.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following sections provide details regarding the typical application of the XTR305 using three different
functional modes: voltage output mode as shown in Figure 35, current output mode as shown in Figure 36, and
externally configured mode as shown in Figure 37.
8.2 Typical Application
V-
V+
GND
C2
100 nF
C3
100 nF
CC
47 nF
GND1
XTR305
ICOPY
R3
1 kΩ
IDRV
VIN
SIN
ROS
2 kΩ
OPA
RC
15 Ω
DRV
GND1
IAIN+
RSET
2 kΩ
IIA
SG
RGAIN
10 kΩ
IA
IAO
RG2
M2
Digital
Control
Error
Flags
R7
2.2 kΩ
GND2
EFLD
Logic Supply
(+2.7 V to +5 V)
EFOT
DGND
GND3
RLOAD
EFCM
OD
M1
C5
10 nF
IAIN-
IAOUT
RIA
1 kΩ
R6
2.2 kΩ
CLOAD
RG1
GND1
External Load
C4
100 nF
SET
OS
RIMON
1 kΩ
Thermal
Pad (2)
Current Copy
IMON
IMON
V-
V+
(1)
Pull-up Resistors
(10 kΩ)
GND4
Copyright © 2017, Texas Instruments Incorporated
(1)
See the Electrical Characteristics: Power and Digital and Digital I/O and Ground Considerations section for operating
limits of DGND.
(2)
Connect thermal pad to V−.
Figure 40. Standard Circuit Configuration
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8.2.1 Design Requirements
Consider the following information during XTR305 circuit configuration:
• Recommended bypassing: 100 nF or more for supply bypassing at each supply.
• RIMON can be in the kΩ range or short-circuited if not used. Do not leave this current output unconnected — it
would saturate the internal current source. The current at this IMON output is IDRV / 10. Therefore, VIMON =
RIMON (IDRV /1 0).
• R3 is not required but can match RSET (or RSET||ROS) to compensate for the bias current.
• RIA can be short-circuited if not used. Do not leave this current output unconnected. RGAIN is selected to 10
kΩ to match the output of 10 V with 20 mA for the equal input signal.
• RC ensures stability for unknown load conditions and limits the current into the internal protection diodes. C4
helps protect the device. Overvoltage clamp diodes (standard 1N4002) might be necessary to protect the
output.
• R6, R7, and C5 protect the IA.
• RLOAD and CLOAD represent the load resistance and load capacitance.
• RSET defines the transfer gain. It can be split to allow a signal offset and, therefore, allow a 5-V single-supply
digital-to-analog converter (DAC) to control a ±10-V or ±20-mA output signal.
The XTR305 can be used with asymmetric supply voltages; however, the minimum negative supply voltage must
be equal to or more negative than −3 V (typically −5 V). This supply value ensures proper control of 0 V and 0
mA with wire resistance, ground offsets, and noise added to the output. For positive output signals, the current
requirement from this negative voltage source is less than 5 mA.
GND1 through GND4 must be selected to fulfill specified operating ranges. DGND must be in the range of (V−) ≤
DGND ≤ (V+) −7 V.
8.2.2 Detailed Design Procedure
8.2.2.1 Voltage Output Mode
In voltage output mode (M1 and M2 are connected low or left unconnected), the feedback loop through the IA
provides high impedance remote sensing of the voltage at the destination, compensating the resistance of a
protection circuit, switches, wiring, and connector resistance. The output of the IA is a current that is proportional
to the input voltage. This current is internally routed to the OPA summing junction through a multiplexer, as
shown in Figure 41.
A 1:10 copy of the output current of the OPA can be monitored at the IMON pin. This output current and the
known output voltage can be used to calculate the load resistance or load power.
During an output short-circuit or an overcurrent condition the XTR305 output current is limited and EFLD (load
error, active low) flag is activated.
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CC
XTR305
Current Copy
IMON
ICOPY
RIMON
GND3
Input Signal
V-
V+
IDRV
VIN
DRV
OPA
SET
IAIN+
RSET
IIA
RG1
IA
RG2
GND1
EFCM
OD
L
L
M2
Load
IAIN-
IAOUT
M1
RGAIN
Digital
Control
EFLD
Error
Flags
GND2
EFOT
DGND
Copyright © 2017, Texas Instruments Incorporated
Figure 41. Simplified Voltage Output Mode Configuration
Applications not requiring the remote sense feature can use the OPA in stand-alone operation (M1 = high). In
this case, the IA is available as a separate input channel.
The IA gain can be set by two resistors, RGAIN and RSET (Equation 1):
R
VOUT = GAIN VIN
2RSET
(1)
or when adding an offset, VREF, to get bidirectional output with a single-ended input shown in Equation 2:
VIN
V - VREF
R
+ IN
VOUT = GAIN
RSET
ROS
2
(2)
(
(
The RSET resistor is also used in current output mode. Therefore, it is useful to define RSET for the current mode,
then set the ratio between current and voltage span with RGAIN.
8.2.2.2 Current Output Mode
The XTR305 does not require a shunt resistor for current control because it uses a precise current mirror
arrangement.
In current output mode (M1 connected low, or left unconnected and M2 connected high), a precise copy of 1/10th
of the output is internally routed back to the summing junction of the OPA through a multiplexer, closing the
control loop for the output current.
The OPA driver can deliver more than ±24 mA within a wide output voltage range. An open-output condition or
high-impedance load that prevents the flow of the required current activates the EFLD flag and the IA can become
overloaded and draw greater than 7-mA saturation current.
While in current output mode, a current (IIA) that is proportional to the voltage at the IA input is routed to IAOUT
and can be used to monitor the load voltage. A resistor converts this current into voltage. This arrangement
makes level shifting easy.
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Alternatively, the IA can be used as an independent monitoring channel. If this output is not used, connect it to
GND to maintain proper function of the monitor stage, as shown in Figure 42.
XTR305
V-
V+
Current Copy
IMON
ICOPY
IDRV
Input Signal
VIN
OPA
SET
DRV
IAIN+
RSET
IIA
RG1
IA
RG2
GND1
GND2
EFCM
OD
L
H
M1
M2
Load
IAIN-
IAOUT
RIA
RGAIN
Digital
Control
Error
Flags
EFLD
EFOT
DGND
GND3
Copyright © 2017, Texas Instruments Incorporated
Figure 42. Simplified Current Output Mode Configuration
The transconductance (gain) can be set by the resistor, RSET, according to Equation 3:
IOUT = 10 VIN
RSET
(3)
or when adding an offset VREF to get bidirectional output with a single-ended input shown in Equation 4:
VIN
V - VREF
+ IN
IOUT = 10
RSET
ROS
(4)
(
24
(
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8.2.2.3 Input Signal Connection
It is possible to drive the XTR305 with a unidirectional input signal and still get a bidirectional output by adding an
additional resistor, ROS, and an offset voltage signal, VREF. It can be a mid-point voltage or a signal to shift the
output voltage to a desired value.
This design is illustrated in Figure 43a, Figure 43b, and Figure 43c. As with a normal operational amplifier, there
are several options for offset-shift circuits. The input can be connected for inverting or noninverting gain. Unlike
many op amp input circuits, however, this configuration uses current feedback, which removes the voltage
relationship between the noninverting input and output potential because there is no feedback resistor.
a) Noninverting Input
XTR305
VIN
(0 to VOFFSET)
OPA
VREF
ROS
2 kΩ
RSET
2 kΩ
IFeedback
b) Noninverting Input
XTR305
VIN
( VMIDSCALE)
OPA
VMIDSCALE
RSET
1 kΩ
IFeedback
c) Inverting Input (VREF = VOFFSET)
XTR305
VOFFSET
VIN
(±VOFFSET)
OPA
RSET
1 kΩ
IFeedback
Copyright © 2017, Texas Instruments Incorporated
Figure 43. Circuit Options for Op Amp Output Level Shifting
The input bias current effect on the offset voltage can be reduced by connecting a resistor in series with the
positive input that matches the approximate resistance at the negative input. This resistor placed close to the
input pin acts as a damping element and makes the design less sensitive to RF noise. See R3 in Figure 40.
8.2.2.4 Externally-Configured Mode: OPA and IA
It is possible to use the precision of the operational amplifier (OPA) and instrumentation amplifier (IA)
independently from each other by configuring the digital control pins (M1 high). In this mode, the IA output
current is routed to IAOUT and the copy of the OPA output current is routed to IMON, as shown in Figure 37.
This mode allows external configuration of the analog signal routing and feedback loop.
The current output IA has high input impedance, low offset voltage and drift, and very high common-mode
rejection ratio. An external resistor (RIA) can be used to convert the output current of the IA (IIA) to an output
voltage. The gain is given by Equation 5:
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IIA =
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2 V or V = 2RIA V
IA
IN
RGAIN IN
RGAIN
(5)
The OPA provides low drift and high voltage output swing that can be used like a common operational amplifier
by connecting a feedback network around it. In this mode, the copy of the output current is available at the IMON
pin (it includes the current into the feedback network). It provides an output current limit for protection, which can
be set between two ranges by M2. The error flag indicates an overcurrent condition, as well as indicating driving
the output into the supply rails.
Alternatively, the feedback can be closed through the IMON pin to create a precise voltage-to-current converter.
8.2.2.5 Driver Output Disable
The OPA output (DRV) can be switched to a high-impedance mode by driving the OD control pin low. This input
can be connected to the overtemperature flag, EFOT, and a pullup resistor to protect the IC from overtemperature by disconnecting the load.
The output disable mode can be used to sense and measure the voltage at the IA input pins without loading from
the DRV output. This mode allows testing of any voltage present at the I/O connector. However, consider the
bias current of the IA input pins.
The digital control inputs, M1 and M2, set the four operation modes of the XTR305 as shown in Table 1. When
M1 is asserted low, M2 determines voltage or current mode and the corresponding appropriate current limit (ISC)
setting. When M1 is high, the internal feedback connections are opened; IAOUT and IMON are both connected to
the output pins; and M2 only determines the current limit (ISC) setting.
M1 and M2 are pulled low internally with 1 μA. Terminate these two pins to avoid noise coupling. Output disable
(OD) is internally pulled high with approximately 1 μA. When connecting OD to EFOT, a 2.2-kΩ pullup resistor is
recommended.
Table 1. Summary of Configuration Modes (1)
M1
(1)
M2
MODE
DESCRIPTION
L
L
VOUT
Voltage output mode, ISC = 20 mA
L
H
IOUT
Current output mode, ISC = 32 mA
H
L
Ext
IA and IMON on external pins, ISC = 20 A
H
H
Ext
IA and IMON on external pins, ISC = 32
mA
OD is a control pin independent of M1 or M2.
8.2.2.6 Driving Capacitive Loads and Loop Compensation
For normal operation, the driver OPA and the IA are connected in a closed loop for voltage output. In current
output mode, the current copy closes the loop directly.
In current output mode, loop compensation is not critical, even for large capacitive loads. However, in voltage
output mode, the capacitive load, together with the source impedance and the impedance of the protection
circuit, generates additional phase lag. The IA input might also be protected by a low-pass filter that influences
phase in the closed loop.
The loop compensation low-pass filter consists of CC and the parallel resistance of ROS and RSET. For loop
stability with large capacitive load, the external phase shift has to be added to the OPA phase. With CC, the
voltage gain of the OPA has to approach zero at the frequency where the total phase approaches 180° + 135°.
The best stability for large capacitive loads is provided by adding a small resistor, RC (15 Ω). See the Output
Protection section.
An empirical method of evaluation is using a square wave input signal and observing the settling after transients.
Use small signal amplitudes only—steep signal edges cause excessive current to flow into the capacitive load
and may activate the current limit, which hides or prevents oscillation. A small-signal oscillation can be hidden
from large capacitive loads, but observing the IMON output on an appropriate resistor (use a similar value like
RSET||ROS) would indicate stability issues. Note that noise pulses at IMON during overload (EFLD active) are normal
and are caused by cycling of the current mirror.
26
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The voltage output mode includes the IA in the loop. An additional low-pass filter in the input reverses the phase
and therefore increases the signal bandwidth of the loop, but also increases the delay. Again, loop stability has to
be observed. Overloading the IA disconnects the closed loop and the output voltage rails.
8.2.2.7 Internal Current Sources, Switching Noise, and Settling Time
The accuracy of the current output mode and the DC performance of the IA rely on dynamically-matched current
mirrors.
Identical current sources are rotated to average out mismatch errors. It can take several clock cycles of the
internal 100-kHz oscillator (or a submultiple of that frequency) to reach full accuracy. This may dominate the
settling time to the 0.1% accuracy level and can be as much as 100 μs in current output mode or 40 μs in voltage
output mode.
A small portion of the switching glitches appear at the DRV output, and also at the IMON and IAMON outputs. The
standard circuit configuration, with RC, C4, and CC, which are required for loop compensation and output
protection, also helps reduce the noise to negligible levels at the signal output. If necessary, the monitor outputs
can be filtered with a shunt capacitor.
8.2.2.8 IA Structure, Voltage Monitor
The instrumentation amplifier has high-impedance NPN transistor inputs that do not load the output signal, which
is especially important in current output mode. The output signal is a controlled current that is multiplexed either
to the SET pin (to close the voltage output loop) or to IAOUT (for external access).
The principal circuit is shown in Figure 44. The two input buffer amplifiers reproduce the input difference voltage
across RGAIN. The resulting current through this resistor is bidirectionally mirrored to the output. That mirroring
results in the transfer function of Equation 6:
(IAIN+ – IAIN-)
IIA = IAOUT = 2
RGAIN
(6)
The accuracy and drift of RGAIN defines the accuracy of the voltage to current conversion. The high accuracy and
stability of the current mirrors result from a cycling chopper technique.
Current Mirror
IR
IR
IAIN+
A1
Current Mirror
IR
RGAIN
IR
Current Mirror
2IR
2IR
IIA
A2
IAIN-
2IR
2IR
Current Mirror
Copyright © 2017, Texas Instruments Incorporated
Figure 44. IA Block Diagram
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The output current, IAOUT, of the instrumentation amplifier is limited to protect the internal circuitry. This current
limit has two settings controlled by the state of M2 (see Electrical Characteristics: Instrumentation Amplifier (IA),
Short-Circuit Current specification).
NOTE
If RSET is too small, the current output limitation of the instrumentation amplifier can disrupt
the closed loop of the XTR305 in voltage output mode.
With M2 = low, the nominal RGAIN of 10 kΩ allows an input voltage of 20 VPP, which produces an output current
of 4 mAPP. When using lower resistors for RGAIN that can allow higher currents, the IA output current limitation
must be taken into account.
8.2.2.9 Digital I/O and Ground Considerations
The XTR305 offers voltage output mode, current output mode, external configuration, and instrumentation mode
(voltage input). In addition, the internal feedback mode can be disconnected and external loop connections can
be made. These modes are controlled by M1 and M2 (see Table 1). The OD input pin controls enable or disable
of the output stage (OD is active low).
The digital I/O is referenced to DGND and signals on this pin must remain within 5 V of the DGND potential. This
DGND pin carries the output low-current (sink current) of the logic outputs. DGND can be connected to a
potential within the supply voltage but needs to be 8 V below the positive supply. Proper connection avoids
current from the digital outputs flowing into the analog ground.
CAUTION
The DGND has normally reverse-biased diodes connected to the supply. Therefore,
high and destructive currents could flow if DGND is driven beyond the supply rails by
more than a diode forward voltage. Avoid this condition during power on and power off.
8.2.2.10 Output Protection
The XTR305 is intended to operate in a harsh industrial environment. Therefore, a robust semiconductor process
was chosen for this design. However, some external protection is still required.
The instrumentation amplifier inputs can be protected by external resistors that limit current into the protection
cell behind the IC pins, as shown in Figure 45. This cell conducts to the power-supply connection through a
diode as soon as the input voltage exceeds the supply voltage. The circuit configuration example shows how to
arrange these two external resistors.
The bias current is best cancelled if both resistors are equal. The additional capacitor reduces RF noise in the
input signal to the IA.
R6
2.2 kΩ
IAIN+
VSENSE+
RG1
IA
RG2
RGAIN
C5
10 nF
R7
2.2 kΩ
VSENSE-
IAIN-
Figure 45. Current-Limiting Resistors
The load connection to the DRV output must be low impedance; therefore, external protection diodes may be
necessary to handle excessive currents, as shown in Figure 46. The internal protection diodes start to conduct
earlier than a normal external PN-type diode because they are affected by the higher die temperature. Therefore,
either Schottky diodes are required, or an additional resistor (RC) can be placed in series with the input. An
example of this protection is shown in Figure 46. Assuming the standard diodes limit the voltage to 1.4 V and the
internal diodes clamp at 0.7 V, this resistor can limit the current into the internal protection diodes to 50 mA
shown in Equation 7:
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(1.4V – 0.7V)
= 47mA
15W
(7)
RC is also part of the recommended loop compensation. C4 helps protect the output against RFI and high-voltage
spikes.
CC
47 nF
V+
XTR305
DRV
OPA
D
1N4002
RC
15 Ω
I/V OUT
D
1N4002
C4
100 nF
VCopyright © 2017, Texas Instruments Incorporated
Figure 46. Example for DRV Output Protection
8.2.3 Application Curves
The nonlinearity of the XTR305 when operating in current output mode is shown in Figure 47 and Figure 48.
V-
V+
0.025
+25°C
-55°C
0
L2
10 µH
Nonlinearity (%)
L1
10 µH
CB1
100 nF
CB2
100 nF
CB3
1 µF
-0.025
+85°C
-0.050
-0.075
+125°C
CB4
1 µF
-0.100
-24 -20 -16 -12 -8
-4
0
4
8
12
16
20
24
Output Current (mA)
V+
(±24-mA End Point Calibration)
V-
XTR305
Copyright © 2017, Texas Instruments Incorporated
(±20-mA End Point Calibration)
Figure 47. Nonlinearity vs Output Current
Figure 48. Nonlinearity vs Output Current
9 Power Supply Recommendations
Built on a robust high-voltage BiCMOS process, the XTR305 is designed to interface the 5-V or 3-V supply
domain used for processors, signal converters, and amplifiers to the high-voltage and high-current industrial
signal environment. The device is specified for up to ±20-V supply, but can also be powered asymmetrically (for
example, +24 V and −5 V). XTR305 is designed to allow insertion of external circuit protection elements and
drive large capacitive loads.
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10 Layout
10.1 Layout Guidelines
Supply bypass capacitors must be close to the package and connected with low-impedance conductors. Avoid
noise coupled into RGAIN, and observe wiring resistance. For thermal management, see the VQFN Package and
Heat Sinking section.
Layout for the XTR305 is not critical; however, its internal current chopping works best with good (low dynamic
impedance) supply decoupling. Therefore, avoid through-hole contacts in the connection to the bypass
capacitors or use multiple through-hole contacts. Switching noise from power supplies should be filtered enough
to reduce influence on the circuit. Small resistors (2-Ω, for example) or damping inductors in series with the
supply connection (between the DC-DC converter and the XTR circuit) act as a decoupling filter together with the
bypass capacitor as shown in Figure 49.
Resistors connected close to the input pins help dampen environmental noise coupled into conductor traces.
Therefore, place the OPA input- and IA input-related resistors close to the package. Also, avoid additional wire
resistance in series to RSET, ROS, and RGAIN (observe the reliability of the through-hole contacts), because this
resistance could produce gain and offset error as well as drift; 1 Ω is already 0.1% of the 1-kΩ resistor.
The exposed lead-frame die pad on the bottom of the package must be connected to V−, pin 11 (see the VQFN
Package and Heat Sinking section for more details).
V-
V+
L1
10 µH
L2
10 µH
CB1
100 nF
CB2
100 nF
CB3
1 µF
CB4
1 µF
V+
V-
XTR305
Copyright © 2017, Texas Instruments Incorporated
Figure 49. Suggested Supply Decoupling for Noisy Chopper-Type Supplies
10.2 Layout Example
A detailed layout example can be found in the technical document XTR300EVM. This document is available for
download at www.ti.com. The example layout is also shown in Figure 50.
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Layout Example (continued)
Figure 50. Layout Example
10.3 VQFN Package and Heat Sinking
The XTR305 is available in a VQFN package. This leadless, near-chip-scale package maximizes board space
and enhances thermal and electrical characteristics of the device through an exposed thermal pad.
Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but
printed circuit board (PCB) layout greatly influences overall heat dissipation. The thermal resistance from
junction-to-ambient (θJA) is specified for the packages with the exposed thermal pad soldered to a normalized
PCB, as described in the technical brief PowerPAD™ Thermally-Enhanced Package. See also EIA/JEDEC
Specifications JESD51-0 to 7, VQFN/SON PCB Attachment, and Quad Flatpack No-Lead Logic Packages.
These documents are available for download at www.ti.com.
NOTE
All thermal models have an accuracy variation of ±20%.
Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load
conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress
for proper long-term operation with a junction temperature well below +125°C.
The exposed lead-frame die pad on the bottom of the package must be connected to the V− pin.
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10.4 Power Dissipation
Power dissipation depends on power supply, signal, and load conditions. It is dominated by the power dissipation
of the output transistors of the OPA. For DC signals, power dissipation is equal to the product of output current,
IOUT and the output voltage across the conducting output transistor (VS – VOUT).
It is very important to note that the temperature protection does not shut the device down in overtemperature
conditions, unless the EFOT pin is connected to the output enable pin OD; see the Driver Output Disable section.
The power that can be safely dissipated in the package is related to the ambient temperature and the heat sink
design and conditions. The VQFN package with an exposed thermal pad is specifically designed to provide
excellent power dissipation, but board layout greatly influences the heat dissipation.
To appropriately determine the required heat sink area, calculate required power dissipation; also consider the
relationship between power dissipation and thermal resistance to minimize overheat conditions and allow for
reliable long-term operation.
The heat-sinking efficiency can be tested using the EFOT output signal. This output goes low at nominally 140°C
junction temperature (assume 6% tolerance). With full power dissipation (for example, maximum current into a 0Ω load), the ambient temperature can be slowly raised until the OT flag goes low. This flag would indicate the
minimum heat sinking for the usable operation condition.
The recommended landing pattern for the VQFN package is shown at the end of this data sheet.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally-Enhanced Package
• EIA/JEDEC Specifications JESD51-0 to 7, VQFN/SON PCB Attachment
• Quad Flatpack No-Lead Logic Packages
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
XTR305IRGWR
ACTIVE
VQFN
RGW
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
XTR
305
XTR305IRGWT
ACTIVE
VQFN
RGW
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
XTR
305
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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