SPT7720SIT

SPT7720 8-BIT, 200 MSPS A/D CONVERTER TECHNICAL DATA MAY 9, 2001 FEATURES • Pin-compatible with AD9054 • High conversion rate: 200 MSPS • Less than ±1/2 LSB DLE • 7.16 effective number of bits (ENOB) at 70 MHz • Single +5 V power supply • Internal THA and voltage reference • Low power : 430 mW • 500 MHz full-power bandwidth • 1V PP input range • Single or demuxed TTL output por ts • 44-lead TQFP APPLICATIONS • Digital sampling oscilloscopes (DSO) • RGB video processing • Digital communications • High-speed instrumentation • Projection display systems GENERAL DESCRIPTION The SPT7720 is an 8-bit, high-speed, analog-to-digital conver ter implemented in a 0.5 µm BiCMOS process. It utilizes a folding and inter polating architecture that provides both high sample rates and low power. The device comes complete with a high bandwidth track-and-hold amplifier and internal voltage reference. The SPT7720 digital inputs interface directly to TTL, CMOS or positive ECL (PECL) logic. The digital outputs are user selectable in either single-channel or dual-channel modes. It is a pin-compatible, direct replacement for the AD9054. The SPT7720 is available in a 44-lead TQFP surface mount package over the industrial temperature range of –40 to +85 °C. BLOCK DIAGRAM VREF IN VREF OUT AIN AIN + – Reference THA Quantizer 8 Channel A ENCODE ENCODE DA7 – DA0 Timing & Control Binary Encoder Channel B 8 DB7 – DB0 DEMUX DS DS ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages VDD ........................................................................ +6 V Input Voltages Analog Inputs ............................................... 0.0 to VDD Digital Inputs ................................................ 0.0 to VDD VREFL, VREFH ................................................ 0.0 to VDD Temperatures Operating Temperature .......................... –40 to +85 °C Storage Temperature ............................ –65 to +125 °C Note 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, VDD=+5.0 V, external reference, ƒS=200 MSPS, input amplitude = –1 dBFS, unless otherwise noted PARAMETERS DC Accuracy Differential Linearity Error (DLE) Integral Linearity Error (ILE) No Missing Codes Gain Error Gain Tempco Switching Performance Encode Pulsewidth High Encode Pulsewidth Low Aperture Delay (tA) Aperture Uncertainty (Jitter) & Noise Data Sync Setup Time (tSDS) Data Sync Hold Time (tHDS) Data Sync Pulsewidth Time (tPWDS) Output Valid Time (tV) Output Prop. Delay (tPD) Dynamic Performance Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (without harmonics) ƒIN = 19.7 MHz ƒIN = 19.7 MHz ƒIN = 70.1 MHz ƒIN = 70.1 MHz Signal-to-Noise Ratio and Distortion (SINAD) ƒIN = 19.7 MHz ƒIN = 19.7 MHz ƒIN = 70.1 MHz ƒIN = 70.1 MHz 2nd Harmonic Distortion ƒIN = 19.7 MHz ƒIN = 70.1 MHz 3rd Harmonic Distortion ƒIN = 19.7 MHz ƒIN = 70.1 MHz Total Harmonic Distortion (THD) ƒIN = 70.1 MHz ƒIN = 70.1 MHz Effective Number of Bits (ENOB) ƒIN = 70.1 MHz ƒIN = 70.1 MHz TEST CONDITIONS +25 °C –40 °C to +85 °C +25 °C –40 °C to +85 °C +25 °C TEST LEVEL I V I V VI I V IV IV V V IV IV IV IV IV V V V V I V V V I V V V V V I V I V MIN SPT7720 TYP ±0.41 ±1.0 ±0.56 ±0.9 Guaranteed ±1.06 0 MAX ±0.75 ±1.0 ±1.0 ±1.2 ±1.08 UNITS LSB LSB LSB LSB %FS ppm/°C ns ns ns ps rms ns ns ns ns ns ns ns dB dB dB dB dB dB dB dB dBc dBc dBc dBc +25 +25 +25 +25 +25 +25 +25 °C °C °C °C °C °C °C 2.125 2.125 0 0.5 2.0 4.4 15 15 0.57 4.5 5.7 6.7 1.5 1.5 47 47 46.3 45.8 47 43 44.9 44.5 –59 –55.4 –58 –56.4 –50.9 –48.3 8.0 +25 °C +25 °C +25 °C –40 °C to +85 °C +25 °C –40 °C to +85 °C +25 °C –40 °C to +85 °C +25 °C –40 °C to +85 °C +25 °C +25 °C +25 °C +25 °C +25 °C –40 to +85 °C +25 °C –40 to +85 °C 44 43 –46.0 dBc dBc Bits Bits 6.9 6.5 7.16 SPT7720 2 5/9/01 ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, VDD=+5.0 V, external reference, ƒS=200 MSPS, input amplitude = –1 dBFS, unless otherwise noted PARAMETERS Analog Input Input Voltage Range (differential) Compliance Range Input Offset Voltage Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Input Bias Current Full Power Bandwidth Reference Output Voltage Temperature Coefficient Differential Digital Inputs High Level Current Low Level Current Input Capacitance Differential Inputs Differential Signal Amplitude High Input Voltage Low Input Voltage Common-Mode Input Voltage Demux Input High Input Voltage Low Input Voltage Digital Outputs High Output Voltage Low Output Voltage Output Coding Power Supply VDD Supply Current Power Dissipation Power Supply Sensitivity TEST CONDITIONS TEST LEVEL V V I V V V I V V VI V MIN SPT7720 TYP ±0.5 MAX UNITS V V mV mV kΩ pF µA µA MHz V ppm/°C µA µA pF mV V V V V V V V 1.8 36 ±4 ±8 62 4 11 500 2.4 2.5 110 500 500 3 400 1.5 0 1.5 2.0 0 2.4 3.9 0.8 Binary 86 430 0.005 +25 °C –40 °C to +85 °C +25 °C +25 °C –40 °C to +85 °C 3.2 ±16 ±19 50 75 2.6 –40 to +85 °C >1.5 V differential –40 to +85 °C >1.5 V differential V V V IV IV IV IV VI VI 625 625 VDD VDD–0.4 VDD 0.8 Source 800 µA Sink 1.6 mA VI VI 0.4 –40 to +85 °C +25 °C VI VI IV 111 555 0.015 mA mW V/V TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL TEST PROCEDURE I II III IV V VI 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT7720 3 5/9/01 Figure 1 – Timing Diagram – Single-Channel Mode N+4 N+3 N+2 N N–1 tA N+1 N+6 N+5 N+7 ENCODE ENCODE tPD DA0 – DA7 OUTPUT DATA tV N N+1 N+2 N–5 N–4 N–3 N–2 N–1 Figure 2 – Timing Diagram – Dual-Channel Mode N+4 N+3 N+2 N N–1 tA N+1 N+6 N+5 N+7 ENCODE ENCODE tHDS tSDS tHDS tSDS DS tPWDS tPD INTERLEAVED DATA OUT tV DA0 – DA7 OUTPUT DATA DB0 – DB7 OUTPUT DATA N–6 N–4 N–2 N N–5 N–3 N–1 SPT7720 4 5/9/01 TYPICAL PERFORMANCE CHARACTERISTICS 60 55 SNR, SINAD vs Sample Rate ƒIN = 70.1 MHz –30 –35 SFDR, THD vs Sample Rate ƒIN = 70.1 MHz SNR, SINAD (dB) 45 40 35 30 25 20 0 50 100 150 200 SFDR, THD (dB) 50 SNR SINAD –40 –45 –50 –55 –60 –65 THD SFDR 250 THD SFDR Sample Rate (MSPS) 250 –70 0 50 Sample Rate (MSPS) 100 150 200 60 55 SNR, SINAD vs Temperature ƒIN = 70.1 MHz ƒS = 200 MSPS SNR SINAD –30 –35 –40 THD vs Temperature ƒIN = 70.1 MHz ƒS = 200 MSPS SNR, SINAD (dB) 50 45 40 35 30 25 20 –40 –25 0 25 50 THD (dB) –45 –50 –55 –60 –65 Temperature (Degrees C) SNR, SINAD vs VDD 75 100 –70 –40 –25 Temperature (Degrees C) THD vs VDD 0 25 50 75 100 60 55 –30 –35 –40 ƒIN = 70.1 MHz ƒS = 200 MSPS SNR SINAD ƒIN = 70.1 MHz ƒS = 200 MSPS SNR, SINAD (dB) 50 45 40 35 30 25 20 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 THD (dB) –45 –50 –55 –60 –65 Volts 5.3 5.4 5.5 –70 4.5 4.6 4.7 4.8 4.9 Volts 5.0 5.1 5.2 5.3 5.4 5.5 SPT7720 5 5/9/01 TYPICAL PERFORMANCE CHARACTERISTICS 60 55 SNR, SINAD vs Encode Pulsewidth ƒIN = 70.1 MHz ƒS = 200 MSPS –30 –35 SFDR, THD vs Encode Pulsewidth ƒIN = 70.1 MHz ƒS = 200 MSPS THD SFDR SNR, SINAD (dB) 45 40 35 30 25 20 1.0 1.5 2.0 2.5 3.0 3.5 SINAD SFDR, THD (dB) 50 SNR –40 –45 –50 –55 –60 –65 –70 1.0 1.5 2.0 2.5 3.0 3.5 Encode Pulsewidth (nS) DLE vs Sample Rate Encode Pulsewidth (nS) DLE vs Temperature 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –40 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 LSB LSB ƒIN = 70.1 MHz ƒIN = 70.1 MHz ƒS = 200 MSPS 0 50 Sample Rate (MSPS) 100 150 200 250 –25 0 25 50 Temperature (Degrees C) 75 100 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 4.5 4.6 DLE vs VDD ƒIN = 70.1 MHz ƒS = 200 MSPS 120 Supply Current vs Temperature ƒIN = 70.1 MHz ƒS = 200 MSPS Supply Current (mA) 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 100 LSB 80 60 Volts 40 –40 –25 Temperature (Degrees C) 0 25 50 75 100 SPT7720 6 5/9/01 Figure 3 – Typical Interface Circuit +A5 Single Mode Dual Mode Data Sync Clock In 0.1 µF 0.1 µF 1KW AIN VREFOUT VREFIN ENCODE ENCODE Port A DA0–7 DEMUX DS DS (+2.5 V typ) SPT7720 GND (10) VDD (9) Interfacing Logics (1 VP-P) VIN AIN 0.1 µF DB0–7 Port B .01 µF (9x) + +A5 R3 VCM (R3)/2 – + R2 R2 Notes: 1) FB = Ferrite bead. It must placed as close to the DUT as possible. 2) All 0.01 microfarad capacitors are surface mount caps. They must be placed as close to the respective pin as possible. FB 10 µF +D5 TYPICAL INTERFACE CIRCUIT Very few external components are required to achieve the stated device performance. Figure 3 shows the typical interface requirements when using the SPT7720 in normal circuit operation. The following sections provide descriptions of the major functions and outline performance criteria to consider for achieving the optimal device performance. ANALOG INPUT The input of the SPT7720 can be configured in various ways depending on whether a single-ended or differential input is desired. The AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary winding. The center tap is connected to the VCM pin as shown in figure 3. To obtain low distortion, it is important that the selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the input attenuates kickback noise from the internal trackand-hold. Figure 4 illustrates a solution (based on operational amplifiers) that can be used if a DC-coupled single-ended input is desired. It is very important to select op amps with a high open-loop gain, a bandwidth high enough so as not to impair the performance of the ADC, low THD, and high SNR. Figure 4 – DC-Coupled Single-Ended to Differential Conversion (power supplies and bypassing are not shown) R3 R – + R ADC 51 W 15 pF VIN– 51 W R R VIN+ Input Voltage (±0.5 V) + – R 51 W INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit. This circuit provides ESD robustness and prevents latchup under severe discharge conditions without degrading analog transmission times. POWER SUPPLIES AND GROUNDING The SPT7720 is operated from a single power supply in the range of 4.75 to 5.25 volts. Normal operation is suggested to be 5.0 volts. All power supply pins should be bypassed as close to the package as possible. SPT7720 7 5/9/01 REFERENCES To save on parts count, design time, and PC board real estate, the SPT7720 utilizes an internal reference. No other external components are required to implement this feature. VOLTAGE REFERENCE CIRCUIT The SPT7720 has an on-board voltage reference circuit (VREF). It is 2.5 volts and is capable of driving 50 µA loads typically. The circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. ENCODE INPUT The ENCODE input on the SPT7720 can be driven by either a single-ended or differential clock circuit and can handle TTL, PECL, and CMOS signals. When operating at high sample rates it is important to keep the pulse width of the duty signal as close to 50% as possible. For TTL/ CMOS single-ended ENCODE inputs, the rise time of the signal also becomes an important consideration. The ENCODE input is 300 Ω into a bipolar differential pair. ENCODE is internally biased to 1.5 V with a Thevenin equivalent of 5.25 kΩ. DIGITAL INPUTS The DS input is 35 Ω into one side of a differential pair. There is a two-diode clamp from DS to DS in both directions. DS is biased to 1.5 V with a Thevenin equivalent of 5.25 kΩ. The DEMUX pin is input to one side of a CMOS differential pair. The other side is internally biased to 1.5 V and does not connect to the outside. DIGITAL OUTPUTS The output circuitry of the SPT7720 has been designed to be able to support two separate output modes. The demuxed (double-wide) mode supports interleaved data output. The single-channel mode is not demuxed and can support direct output at speeds up to 100 MSPS. The output format is straight binary (table I). Table I – Output Data Format Output Code D7–D0 +FS 1111 1111 +FS – 1 /2 LSB 1111 111 Ø +1/2 FS ØØØØ ØØØØ – FS + 1/2 LSB 0000 000 Ø –FS 0000 0000 Ø indicates the flickering bit between logic 0 and 1 Analog Input The data output mode is set using the DEMUX input (pin 42). Table II describes the mode switching options. Table II – Output Data Modes Output Mode Interleaved Dual Channel Output Single Channel Data Output (Bank A only 100 MSPS max) DEMUX 0 1 EVALUATION BOARD The EB7720 evaluation board is available to aid designers in demonstrating the full performance of the SPT7720. This board includes a clock driver and reset circuit, adjustable references and common mode, a single-ended to differential input buffer and a single-ended to differential transformer (1:1). An application note (AN7720) describing the operation of this board, as well as information on the testing of the SPT7720, is also available. Contact the factory for price and availability of the EB7720. SPT7720 8 5/9/01 PACKAGE OUTLINE 44-Lead TQFP A B INCHES SYMBOL A MIN MAX MILLIMETERS MIN MAX 0.472 Typ 0.394 Typ 0.394 Typ 0.472 Typ 0.031 Typ 0.012 0.053 0.002 0.018 0.018 0.057 0.006 0.030 0.039 Typ 0-7° 12.00 Typ 10.00 Typ 10.00 Typ 12.00 Typ 0.80 Typ 0.300 1.35 0.05 0.450 0.45 1.45 0.15 0.750 1.00 Typ 0-7° Pin 1 Index B C D C D E F G H I J K E F G I J K H SPT7720 9 5/9/01 PIN ASSIGNMENTS DEMUX VREF IN GND GND GND VDD VDD AIN AIN PIN FUNCTIONS Pin Name Description AIN, AIN ENCODE ENCODE Differential Input Pins Differential Clock Input Power Supply Ground Digital Outputs, Channel A Digital Outputs, Channel B Reference Input Voltage, High Format Select: LOW = Dual-Channel Mode, HIGH = Single-Channel Mode Data Sync and Data Sync Complement – Aligns Output Channels in Dual-Channel Mode DS 44 1 2 3 4 5 6 7 8 9 10 11 DS 43 VDD 33 32 31 30 VREF OUT GND VDD VDD GND VDD GND DB7 (MSB) DB6 DB5 DB4 42 41 40 39 38 37 36 35 34 ENCODE ENCODE VDD GND VDD GND DA7 (MSB) DA6 DA5 DA4 DA3 GND DA0–DA7 DB0–DB7 VREF IN DEMUX SPT7720 TOP VIEW 44L TQFP 29 28 27 26 25 24 23 VREF OUT Reference Output Voltage DS, DS ORDERING INFORMATION PART NUMBER SPT7720SIT TEMPERATURE RANGE –40 to +85 °C PACKAGE 44L TQFP 12 DA2 13 DA1 14 DA0 (LSB) 15 VDD 16 GND 17 GND 18 VDD 19 DB0 (LSB) 20 DB1 21 DB2 22 DB3 SPT7720 10 5/9/01