SPT8100SIT

SPT8100 16-BIT, 5 MSPS CMOS A/D CONVERTER TECHNICAL DATA JANUARY 9, 2002 FEATURES • 16-bit, 5 MSPS CMOS analog-to-digital conver ter • On-chip PGA: gain range from 0 to 19.5 dB in seven selectable settings: 0 dB, +2.9 dB, +5.8 dB, +11.8 dB, +14.8 dB, +17.5 dB, +19.5 dB • DLE: ±0.5 LSB, ILE: ±1.25 LSB • SFDR: 94 dB @ ƒ IN = 900 kHz, –8.1 dBFS • Internal sample-and-hold and voltage reference • Power dissipation: 465 mW at 5 MSPS • +5 V analog supply and +3.3 to +5.25 V digital output supply • 44-lead LQFP plastic package APPLICATIONS • Data acquisition systems • IR imaging • Scanners and digital copiers • High-end CCD cameras • Medical imaging • Wireless communications • Lab and test equipment • Automatic test equipment DESCRIPTION The SPT8100 is a high-perfor mance, 16-bit analog-todigital conver ter that operates at a sample rate of up to 5 MSPS. Excellent dynamic perfor mance and high linearity is achieved by a digitally calibrated pipelined architecture fabricated in CMOS process technology. A low-noise programmable gain amplifier (PGA) is also incorporated on chip. The PGA is digitally programmable in seven selected settings over a 0 to +19.5 dB range. The SPT8100 also features an on-chip internal sample-andhold and internal reference for minimal external circuitr y. It operates from a single +5 V supply. Total power dissipation, including internal reference, is 465 mW. A separate digital output supply pin is provided for +3.3 V or 5 V logic output levels. The SPT8100 is available in a 44-lead LQFP package over the industrial temperature range of –40 °C to +85 °C. DVDD +5V OVDD +3/5 V BLOCK DIAGRAM AVDD +5V OE (Output Enable) Low-Noise PGA VIN+ OVR (Over-Range) 16-bit, 5 MSPS ADC VIN– VCM GS2 – GS0 (Gain Set) VREF 16-bits D15 – D0 (Data Outputs) RS (Reset) RDY (Ready) AGND DGND OGND BIASC (Ext Bias Capacitor) BIASR (Ext Bias Resistor) VRT VRB CLK ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages AVDD ...................................................................... +6 V DVDD ..................................................................... +6 V OVDD ..................................................................... +6 V Input Voltages Analog Input ................................. –0.5 V to VDD +0.5 V CLK Input ............................................................... VDD AVDD – DVDD .................................................. ±100 mV Delta between AGND, DGND, and OGND ...... ±100 mV Output Digital Outputs .................................................... 10 mA Temperature Operating Temperature ........................... –40 to +85 °C Junction Temperature ...................................... +175 °C Lead Temperature (soldering 10 seconds) ...... +300 °C Storage Temperature ............................ –65 to +150 °C Note 1: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, Gain=0 dB, REXT=1.43 kΩ, unless otherwise specified. PARAMETERS Resolution DC Accuracy Integral Linearity Error (ILE) Differential Linearity Error (DLE) Gain Error1 Offset Error2 Analog Input (into PGA) Differential Input Voltage Range VIN+, VIN– Input Capacitance PGA Gain = 0 dB Input Resistance3 Input Bandwidth4 PGA Gain = 0 dB Input Common Mode Voltage Range Programmable Gain Amp Composite Input-Referred Noise Floor ƒIN > 300 kHz PGA Gain = 0 dB PGA Gain = 2.9 dB PGA Gain = 5.8 dB PGA Gain = 11.8 dB PGA Gain = 14.8 dB PGA Gain = 17.5 dB PGA Gain = 19.5 dB V V IV IV TEST CONDITIONS TEST LEVEL MIN 15.9 SPT8100 TYP 16 ±1.25 ±0.5 –7.5 –5 +7.5 +5 MAX UNITS Bits LSB LSB %FSR %FSR V IV IV V V 5 15 1.15 5.5 12 2.40 3.65 VPPD pF kΩ MHz V PGA Range PGA Gain Steps3 PGA Gain Accuracy Conversion Characteristics Maximum Conversion Rate Pipeline Delay (Latency)5 Reset Pulse Time (RS) Reset Calibration Time References and External Bias VRT – VRB (Internal Ref) Bias Resistor Range (External) VCM Output Voltage VCM Output Current VRT VRB Total gain error of PGA and ADC using internal references. Total offset error of PGA and ADC relative to mid-scale. 3 See table I for input resistance as a function of PGA gain. 1 2 4 5 V V V V V V V V VI VI VI IV IV V VI V IV IV V V 1.4 1.5 1.6 2.0 2.3 2.6 2.8 19.5 0,2.9,5.8,11.8,14.8,17.5,19.5 ±0.3 5 5.5 3 150 2.375 800 2.275 3.45 0.95 2.5 1430 2.40 3.65 1.15 2.625 2500 2.525 47 3.85 1.35 LSBRMS LSBRMS LSBRMS LSBRMS LSBRMS LSBRMS LSBRMS dB dB dB MSPS Clocks Clocks ms V Ω V µA V V FS = 5 MSPS Input bandwidth is a frequency to which the fundamental energy drops by 3 dB The input is sampled on the falling edge of the clock and is available on the output after the rising edge of the clock, 5.5 clock cycles later. SPT8100 2 1/9/02 ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, Gain=0 dB, REXT=1.43 kΩ, unless otherwise specified. PARAMETERS Dynamic Performance1 Effective Number of Bits ƒIN = 60 kHz ƒIN = 900 kHz Signal-to-Noise Ratio (without Harmonics) ƒIN = 75 kHz ƒIN = 900 kHz Harmonic Distortion ƒIN = 60 kHz ƒIN = 900 kHz Signal-to-Noise and Distortion (SINAD) ƒIN = 60 kHz ƒIN = 900 kHz Spurious Free Dynamic Range3 ƒIN = 60 kHz ƒIN = 900 kHz ƒIN = 2 MHz ƒIN = 3 MHz Two-Tone Intermodulation 3rd Order Distortion Inputs GS0–GS2 Logic 1 Voltage GS0–GS2 Logic 0 Voltage CLK, RS Logic 1 Voltage CLK, RS Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage CLK to Output Delay Time (tD) Power Supply Requirements Voltages OVDD AVDD DVDD Currents IDD Power Dissipation 1 2 3 TEST CONDITIONS ADC Input = –1 dBFS2 TEST LEVEL MIN SPT8100 TYP MAX UNITS IV V ADC Input = –1 dBFS2 IV V ADC Input = –0.5 dBFS IV V ADC Input = –1 dBFS IV V ADC Input = –0.5 dB REXT = 1 kΩ @ 10 MSPS REXT = 1 kΩ @ 10 MSPS ƒ1=400 kHz, ƒ2=410 kHz4 ƒ1=890 kHz, ƒ2=900 kHz5 IV V V V V V VI VI VI VI VI VI V IOH = –2 mA IOL = 2 mA CLOAD = 20 pF VI VI IV IV IV IV VI VI 4 5 12.2 13.0 12.7 81 80 –92 –82 –84 Bits Bits dB dB dB dB dB dB dBc dBc dBc dBc dB dB V V V V µA µA pF V V ns V V V mA mW 78 75 85 80 78 94 94 83 78 –94 –89 2.4 0.8 2.0 –10 –10 5 OVDD – 0.5 0.4 30 3.0 4.75 4.75 3.3 5.0 5.0 93 465 5.25 5.25 5.25 103 515 0.8 +10 +10 Dynamic performance tested at ƒS=4.4 MSPS 0 dBFS is 5.0 V peak-to-peak differential ADC Input = –8.1 dBFS, unless otherwise noted Test Conditions: PGA setting of 5.8 dB; Analog Input at ADC = –0.7 dB Test Conditions: PGA setting of 0 dB; Analog Input at ADC = –1.9 dB TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT8100 3 1/9/02 DEVICE OVERVIEW The SPT8100 combines a high-resolution 5 MSPS 16-bit ADC, a built-in reference, and a programmable gain amplifier (PGA) with resistive input impedance in a 44-pin package. The device includes a digitally calibrated pipeline ADC, which is calibrated on assertion of a simple reset signal. The combination of low noise, high linearity, a high-input impedance buffer (with programmable gain), wideband S/H, on-board voltage references, and simple digital interface (16-bit parallel output word synchronous with the master sampling clock) makes the SPT8100 extremely easy to use in a wide variety of systems. For optimum performance, the analog inputs should be driven differentially, and may be AC-coupled or DCcoupled to a source. Typical applications include high-performance data acquisition systems, automatic test equipment, and wideband digital communications receivers such as wireless basestations. ADC CLOCK The chip requires a single low-jitter clock to be applied at the CLK pin, with nominal 40–60% duty cycle. All clock generation is performed internally and all converter and S/H clocks in the ADC path are directly derived from CLK. If the sample rate is changed by more than a factor of 2, the device must be recalibrated using the RS (reset) pin. DEVICE STARTUP/INITIALIZATION SEQUENCE Note: This initialization sequence is required. Without it, the device will not work. Allow sufficient time for the analog blocks on the SPT8100 to power on and come up to their quiescent DC states. Allowance may also be needed for thermal time constants associated with the package/board. On powerup, the SPT8100’s RS (reset) should be held low for at least three clock cycles. The power supply voltages applied to the device must be stable during this time. The clock signal (CLK) must be running for at least three clock cycles prior to the rising edge of RS, and must continue running. When the RS signal goes from low to high, calibration is initiated. RDY is driven low two clock cycles after the rising edge of RS, and will stay low for 150 ms with a 5 MHz clock. When the initialization is complete, RDY returns high and the device is ready for normal operation. Note that the calibration of the ADC can be interrupted (before completion) by changing the RS signal from high to low, which will cause another reset to occur. When RS goes from low back to high, another calibration cycle will begin. RDY cannot be tri-stated: it is always driven either high or low. The CLK must be constantly running throughout the OPERATIONAL DESCRIPTION The following sections describe in greater detail individual blocks and functions of the SPT8100. The incoming analog differential signal (maximum level 5 V peak-to-peak differential) enters the device at the pins VIN+/VIN–. The analog signal path is partitioned into a programmable gain amplifier (PGA) and an ADC. The PGA has maximum gain of +19.5 dB; the gain is set by the digital control signals GS0 to GS2. The output of the PGA is fed directly to the ADC, which samples at a rate equal to the CLK frequency and outputs a 16-bit wide parallel word. The ADC uses a pipeline multistage architecture. Latency is 5.5 clock cycles. Figure 1 – Device Initialization Timing PWR ON N+7 N+8 AIN N+4 N+6 N+5 CLK RS 3 clock cycles min 2 clock cycles 5 ns typ Initialization period: 150 ms with 5 MHz clock RDY 24 ns typ DOUT Requires external reset on powerup INVALID DATA N N+1 N+2 SPT8100 4 1/9/02 initialization phase until RDY is deasserted. Note that, although typically the device is initialized when power is first applied, the initialization is only started when the RS is asserted; there is no “power-on-reset” circuitry on chip. RS may be held low for an indefinite period of time. While RS is low, RDY will remain high. After RS is returned to high, RDY will go low for the duration of the calibration. TYPICAL INTERFACE CIRCUIT ANALOG INPUT DRIVER The differential analog inputs (VIN+, VIN–) have a resistive input impedance of 1 kΩ minimum. For best performance, the input source should be a differential input, as shown in figure 2, typical interface circuit. The SPT8100 provides its own common-mode voltage on the pin marked VCM. Output drive capability of VCM is a maximum of 47 µA (50 kΩ to ground). The SPT8100 application note (AN8100) shows an example of two modes of driving the SPT8100. One mode is through a transformer and the other is through a single-todifferential converter. In all cases, both inputs VIN+ and VIN– must be kept within the input common-mode range (1.15 V to 3.65 V). BIASC CONNECTION An external capacitor, CEXT on the BIASC pin, is used only for noise filtering of an internal voltage associated with the references. Its value is not critical: 1 µF in parallel with 0.01 µF is recommended. BIASR CONNECTION As shown in the typical interface circuit, REXT is needed to connect between BIASR to ground. This resistor ranges from 800 Ω to 2.5 kΩ. The proper selection of REXT is a function of the sample rate and input frequency. Nominally, at 5 MSPS, REXT=1.43 kΩ is recommended. If linearity for large signal levels at an analog bandwidth of 2 MHz is critical, the value should be decreased to REXT=1.24 kΩ; and for even higher-frequency analog inputs, REXT=1.0 kΩ can be used. At lower sample rates (for example 2 MSPS), and lower analog input frequencies, the value may be increased to REXT=2 kΩ. (Refer to the typical interface circuit table in figure 2b.) PROGRAMMABLE GAIN AMPLIFIER The programmable gain amplifier (PGA) precedes the ADC inputs. The differential inputs, which are resistive, are at pins VIN+ and VIN–.The maximum input range is 5 V peak-to-peak differential (2.5 V single-ended). To achieve maximum overall system noise performance, the source driving these inputs needs to be as low-noise and as lowjitter as possible, while maintaining the required distortion performance. In addition, the driving source must be low impedance to maintain the accuracy of the PGA gain. The internal 0 dB analog signal level and ADC full-scale output level is 5 V peak-to-peak differential (2.5 V singleended). The PGA may be used to provide gain for an input less than 5 V peak-to-peak differential. The gain of the PGA can be programmed using a three-bit control, available at pins GS0 to GS2. See table I. Note that the input resistance is a function of the gain setting. Table I – PGA Gain Control GS2 GS1 GS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PGA Input V/V Gain Resistance Gain (dB) (kΩ) 0 2.9 5.8 11.8 14.8 17.5 19.5 X 5.57 4.65 3.97 2.23 1.66 1.25 1.00 1 1.40 1.95 3.9 5.5 7.5 9.5 Forbidden 3 dB BW LSBRMS 12 10 8 7 6 5.5 5 1.4 1.5 1.6 2.0 2.3 2.6 2.8 POWER SUPPLIES AND GROUNDING The SPT8100 requires three power supplies: analog AVDD, digital DVDD and output supply OVDD. This device works best if all three supplies are coming from the analog supply side of the system as shown in the typical interface circuit (figure 2a). Note, in figure 2a, that the supplies to the logic interface circuit and the OVDD are separate from each other. In a case where the +A3.3/5 V supply is not available, try to implement the design as close as possible to that shown in figure 2b. Place the ferrite bead (FB1) as close to the device as possible. To avoid latch-up, the delta between all three grounds must stay with 100 mV; this includes transients. (Refer to the absolute maximum ratings specifications.) SPT8100 5 1/9/02 Figure 2a – Typical Interface Circuit 1.0 + Gain Control Reset Output Enable Clock (active Hi) Input .01 1.43K REXT Transformer BIASC RS GS2 GS1 GS0 BIASR VCM VIN+ RT (50) VIN– Mini-Circuit T1-6T OE CLK RDY 16 AIN SPT8100 VRT VRB 0.1 1nF AVDD DVDD AGND DGND OGND D0–15 Logic Interfacing Circuit 0.1 + 4.7 + 10 OVR OVDD 0.1 10 10 0.1 + +A5V + FB1 +A3.3/5V +D3.3/5V Figure 2b – Typical Interface Circuit 1.0 + Gain Control Reset Output Enable Clock (active Hi) Input .01 1.43K REXT Transformer BIASC RS GS2 GS1 GS0 BIASR VCM VIN+ RT (50) VIN– Mini-Circuit T1-6T OE CLK RDY 16 AIN SPT8100 VRT VRB 0.1 1nF AVDD DVDD AGND DGND OGND 0.1 0.1 10 FB1 D0–15 Logic Interfacing Circuit 0.1 + 4.7 + 10 OVR OVDD + ƒS (MSPS) REXT (kΩ) –5 –2 –5 –2 1.43 2.00 1.24 1.00 FB2 FB3 ƒIN