CMLDM7585

CMLDM7585 SURFACE MOUNT N-CHANNEL AND P-CHANNEL ENHANCEMENT-MODE COMPLEMENTARY MOSFETS w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR CMLDM7585 consists of complementary N-Channel and P-Channel Enhancement-mode silicon MOSFETs designed for high speed pulsed amplifier and driver applications. These MOSFETs offer Very Low rDS(ON) and Low Threshold Voltage. MARKING CODE: 87C SOT-563 CASE APPLICATIONS: • Load/Power Switches • Power Supply Converter Circuits • Battery Powered Portable Devices MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (Steady State) Maximum Pulsed Drain Current (tp=10μs) Power Dissipation (Note 1) Power Dissipation (Note 2) Power Dissipation (Note 3) Operating and Storage Junction Temperature Thermal Resistance (Note 1) ELECTRICAL CHARACTERISTICS: (TA=25°C) SYMBOL TEST CONDITIONS IGSSF, IGSSR VGS=4.5V, VDS=0 IDSS BVDSS VGS(th) VSD VSD rDS(ON) rDS(ON) rDS(ON) rDS(ON) rDS(ON) rDS(ON) VDS=16V, VGS=0 VGS=0, ID=250μA VDS=VGS, ID=250μA VGS=0, IS=200mA VGS=0, IS=250mA VGS=4.5V, ID=600mA VGS=4.5V, ID=350mA VGS=2.5V, ID=500mA VGS=2.5V, ID=300mA VGS=1.8V, ID=350mA VGS=1.8V, ID=150mA FEATURES: • ESD Protection up to 2kV • 350mW Power Dissipation • Very Low rDS(ON) • Low Threshold Voltage • Logic Level Compatible • Small, SOT-563 Surface Mount Package SYMBOL N-CH (Q1) VDS 20 VGS ID IDM PD PD PD TJ, Tstg ΘJA N-CH (Q1) MIN TYP MAX 1.0 20 0.5 100 1.1 1.1 0.7 1.3 350 300 150 -65 to +150 357 P-CH (Q2) MIN TYP MAX 10 20 0.5 0.37 100 1.0 1.1 0.5 0.8 8.0 650 1.0 P-CH (Q2) UNITS V V mA A mW mW mW °C °C/W UNITS μA nA V V V V Ω Ω Ω Ω Ω Ω 0.14 0.23 0.2 0.275 0.25 0.36 Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm2 (2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm2 (3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm2 R3 (27-September 2011) CMLDM7585 SURFACE MOUNT N-CHANNEL AND P-CHANNEL ENHANCEMENT-MODE COMPLEMENTARY MOSFETS ELECTRICAL CHARACTERISTICS - Continued: (TA=25°C) SYMBOL TEST CONDITIONS Qg(tot) VDS=10V, VGS=4.5V, ID=500mA Qg(tot) VDS=10V, VGS=4.5V, ID=200mA Qgs VDS=10V, VGS=4.5V, ID=500mA Qgs VDS=10V, VGS=4.5V, ID=200mA Qgd VDS=10V, VGS=4.5V, ID=500mA Qgd VDS=10V, VGS=4.5V, ID=200mA gFS VDS=10V, ID=400mA gFS VDS=10V, ID=200mA Crss VDS=16V, VGS=0, f=1.0MHz Ciss VDS=16V, VGS=0, f=1.0MHz Coss VDS=16V, VGS=0, f=1.0MHz ton VDD=10V, VGS=4.5V, ID=200mA, RG=10Ω toff VDD=10V, VGS=4.5V, ID=200mA, RG=10Ω N-CH MIN 1.0 - (Q1) TYP 1.58 0.17 0.24 18 100 16 10 25 P-CH MIN 0.2 - (Q2) TYP 1.2 0.24 0.36 25 100 21 38 48 UNITS nC nC nC nC nC nC S S pF pF pF ns ns SOT-563 CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Source Q1 2) Gate Q1 3) Drain Q2 4) Source Q2 5) Gate Q2 6) Drain Q1 MARKING CODE: 87C R3 (27-September 2011) w w w. c e n t r a l s e m i . c o m