CS5111YDWFR24

CS5111 CS5111 1.4A Switching Regulator with 5V, 100mA Linear Regulator with Watchdog, RESET and ENABLE Description The CS5111 is a dual output power supply integrated circuit. It contains a 5V ±2%, 100mA linear regulator, a watchdog timer, a linear output voltage monitor to provide a Power On Reset (POR) and a 1.4A current mode PWM switching regulator. The 5V linear regulator is comprised of an error amplifier, reference, and supervisory functions. It has low internal supply current consumption and provides 1.2V (typical) dropout voltage at maximum load current. The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal. If a correct watchdog signal is not received within the externally programmable time, a reset signal is issued. The externally programmable active reset circuit operates correctly for an output voltage (VLIN) as low as 1V. During power up, or if the output voltage shifts below the regulation limit, RESET toggles low and remains low for the duration of the delay after proper output voltage regulation is restored. Additionally a reset pulse is issued if the correct watchdog is not received within the programmed time. Reset pulses continue until the correct watchdog signal is received. The reset pulse width and frequency, as well as the Power On Reset delay, are set by one external RC network. The current mode PWM switching regulator is comprised of an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator, and a 1.4A output power switch with anti-saturation control. The switching regulator can be configured in a variety of topologies. The CS5111 is load dump capable and has protection circuitry which includes overvoltage shutdown, current limit on the linear and switcher outputs, and an overtemperature limiter. Features s Linear Regulator 5V ± 2% @ 100mA s Switching Regulator 1.4A Peak Internal Switch 120kHz Maximum Switching Frequency 5V to 26V Operating Supply Range s Smart Functions Watchdog RESET ENABLE s Protection Overvoltage Overtemperature Current Limit s 54V Peak Transient Capability Block Diagram VFB1 VFB2 SELECT COMP IBIAS COSC Oscillator Multiplexer + Switcher Error Amplifier COMP VIN Logic Base Drive + Gnd VSW 1.4A Package Option 24 Lead SO Wide (Internally Fused Leads) VIN NC 1 Current Sense Amplifier ENABLE VREG VLIN IBIAS Gnd Gnd Gnd Gnd RESET CDelay WDI COSC + Switcher Shutdown ENABLE VREG Over Voltage + Linear Error Amplifier NC VSW Gnd VLIN Current Limit Over Temperature Gnd Gnd Gnd VFB1 VFB2 1.25V Bandgap Reference CDELAY WDI RESET & Watchdog Timer RESET SELECT COMP Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com Rev. 12/28/98 1 A ® Company CS5111 Absolute Maximum Ratings Logic Inputs/Outputs ( ENABLE , SELECT, WDI, RESET ) ................................................................................-0.3V to VLIN VLIN ................................................................................................................................................................................-0.3V to 10V VIN, VREG: DC Input Voltage .................................................................................................................................................-0.3V to 26V Peak Transient Voltage (40V Load Dump @ 14V VIN)....................................................................................-0.3V to 54V VSW Peak Transient Voltage .....................................................................................................................................................54V COSC, CDelay, COMP,VFB1, VFB2 ..................................................................................................................................-0.3V to VLIN Power Dissipation.............................................................................................................................................Internally Limited VLIN Output Current ........................................................................................................................................Internally Limited VSW Output Current .........................................................................................................................................Internally Limited RESET Output Sink Current ..................................................................................................................................................5mA ESD Susceptibility (Human Body Model)..............................................................................................................................2kV ESD Susceptibility (Machine Model).....................................................................................................................................200V Storage Temperature ...................................................................................................................................................-65 to 150°C Lead Temperature Soldering: Reflow (SMD styles only) ..........................................60 sec. max above 183°C, 230°C peak Electrical Characteristics: 5V ≤ VIN ≤ 26V and -40°C ≤ TJ ≤ 150°C, COUT = 100µF (ESR≤8Ω), CDelay = 0.1µF, RBIAS = 64.9kΩ, COSC = 390 pF, CCOMP = 0.1µF unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT s General IIN Off Current IIN On Current IREG Current Thermal Limit 6.6V ≤ VIN ≤ 26V, ISW = 0A 6.6V ≤ VIN ≤ 26V, ISW = 1.4A ILIN = 100mA, 6.6V ≤ VREG ≤ 26V Guaranteed by design 160 30 2.0 70 6 210 mA mA mA °C s 5V Regulator Section VLIN Output Voltage Dropout Voltage Overvoltage Shutdown Line Regulation Load Regulation Current Limit DC Ripple Rejection 6.6V ≤ VREG ≤ 26V, 1mA ≤ ILIN ≤ 100mA (VREG - VLIN) @ ILIN = 100mA 4.9 30 5.0 1.2 34 5 5 5.1 1.5 38 25 25 V V V mV mV mA dB 6.6V ≤ VREG ≤ 26V, ILIN = 5mA VREG = 19V, 1mA ≤ ILIN ≤ 100mA 6.6V ≤ VREG ≤ 26V 14V ≤ VREG ≤ 24V 120 60 75 s RESET Section Low Threshold (VRTL) High Threshold (VRTH) Hysteresis Active High Active Low Delay Power On Delay VLIN Decreasing VLIN Increasing VRTH - VRTL VLIN > VRTH, IRESET = -25µA VLIN = 1V, 10kΩ pullup from RESET to VLIN VLIN = 4V, IRESET = 1mA Invalid WDI VLIN crossing VRTH 4.05 4.20 140 VLIN - 0.5 4.25 4.45 190 4.45 4.70 240 0.4 0.7 V V mV V V V ms ms 6.25 6.25 8.78 11.0 2 CS5111 Electrical Characteristics: 5V ≤ VIN ≤ 26V and -40°C ≤ TJ ≤ 150°C, COUT=100µF(ESR ≤ 8Ω), CDelay = 0.1µF, RBIAS = 64.9k, COSC = 390 pF, CCOMP = 0.1µF unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT s Watchdog Input (WDI) VIH VIL Hysteresis Pull-Up Resistor Low Threshold Floating Input Voltage WDI Pulse Width Peak WDI needed to activate RESET 0.8 Note 1 WDI=0V 25 20 6.25 3.5 50 50 8.78 2.0 V V mV 100 11.0 5 kΩ ms V µs s Switcher Section Minimum Operating Input Voltage Switching Frequency Switch Saturation Voltage Output Current Limit Max Switching Frequency VFB1 Regulation Voltage VFB2 Regulation Voltage VFB1, VFB2 Input Current Oscillator Charge Current Oscillator Discharge Current CDelay Charge Current Switcher Max Duty Cycle Current Sense Amp Gain Error Amp DC Gain Error Amp Transconductance VFB1 = VFB2 = 5V COSC = 0V COSC = 4V CDelay = 0V VSW = 5V with 50Ω load, VFB1 = VFB2 = 1V ISW = 2.3A 35 270 35 72 40 320 40 85 7 67 2700 VSW = 7.5V with 50Ω load, Refer to Figure 1d. Refer to Figure 1d. ISW = 1.4A 80 0.7 1.4 120 1.206 1.206 1.25 1.25 95 1.1 5.0 110 1.6 2.5 V kHz V A kHz 1.294 1.294 1 45 370 45 95 V V µA µA µA µA % dB µA/V s ENABLE Input VIL VIH Hysteresis Input Impedance 0.8 1.24 1.30 60 2.0 40 V V mV kΩ 10 20 s Select Input VIL (Selects VFB1) VIH (Selects VFB2) SELECT Pull-Up Floating Input Voltage 4.9 ≤ VLIN ≤ 5.1 4.9 ≤ VLIN ≤ 5.1 SELECT = 0V 0.8 10 3.5 1.25 1.25 24 4.5 2.0 50 V V kΩ V Note 1: Guaranteed by Design, not 100% tested in production. 3 CS5111 Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION 24 Lead SO Wide 1 2, 3 4 5,6,7,8,17,18,19,20 9 10 11 12 13 14 15 16 21 22 23 24 VIN NC VSW Gnd VFB1 VFB2 SELECT COMP COSC WDI CDelay RESET IBIAS VLIN VREG ENABLE Supply Voltage. No connection. Collector of NPN power switch for switching regulator section. Connected to the heat removing leads. Feedback input voltage 1 (referenced to 1.25V) Feedback input voltage 2 (referenced to 1.25V) Logic level input that selects either VFB1 or VFB2. An open selects VFB2. Connect to Gnd to select VFB1. Output of the transconductance error amplifier. A capacitor connected to Gnd sets the switching frequency. Refer to Figure 1d. Watchdog input. Active on falling edge. A capacitor connected to Gnd sets the Power On Reset and Watchdog time. RESET output. Active low if VLIN is below the regulation limit. If watchdog timeout is reached, a reset pulse train is issued. A resistor connected to Gnd sets internal bias currents as well as the COSC and CDelay charge currents. Regulated 5V output from the linear regulator section. Input voltage to the linear regulator and the internal supply circuitry. Logic level input to shut down the switching regulator. Typical Performance Characteristics 4.5mA 0A -10mA IREG - ILIN IIN 20mA 40mA 60mA 80mA 100mA 4.0mA -20mA -30mA 3.5mA 0A -40mA 0A 0.5A 1.0A 1.5A 2.0A ILIN ISW Figure 1a. 5V Regulator Bias Current vs. Load Current. 1.4V 1.2V 1.0V Figure 1b. Supply Current vs. Switch Current. 180 160 Frequency (kHz) 140 120 100 80 60 40 20 VSW 0.8V 0.6V 0.4V 0.2V 0.0V 0A 0.5A 1.0A 1.5A 2.0A 0 0 500 1000 1500 2000 2500 3000 ISW COSC (pF) Figure 1c. Switch Saturation Voltage. Figure 1d. Oscillator Frequency (kHz) vs. COSC (pF), assuming RBIAS = 64.9kΩ. 4 CS5111 Circuit Description VREG Over Voltage + 1.25V Current Limit Over Temperature IBIAS RBIAS 64.9kΩ Cdelay WDI Bandgap Reference RESET & Watchdog Timer Figure 2. Block diagram of 5V linear regulator portion of the CS5111. R1 Linear Error Amplifier Q2 Q1 Q3 R2 R3 R4 R5 RESET VLIN COUT = 100µF ESR < 8Ω 5V Linear Regulator The 5V linear regulator consists of an error amplifier, bandgap voltage reference, and a composite pass transistor. The 5V linear regulator circuitry is shown in Figure 2. When an unregulated voltage greater than 6.6V is applied to the VREG input, a 5V regulated DC voltage will be present at VLIN. For proper operation of the 5V linear regulator, the IBIAS lead must have a 64.9kΩ pull down resistor to ground. A 100µF or larger capacitor with an ESR 2V VOUT = 16V, Select < 0.8V VIN NC NC VSW ENABLE VREG VLIN IBIAS Gnd Gnd Gnd Gnd RESET CDelay WDI COSC COSC 390pF Cdelay 0.1µF MICROPROCESSOR C -20dB/dec L=33µH 5V 100µF ESR