CS8183
Dual Micropower 200 mA
Low Dropout Tracking
Regulator/Line Driver
The CS8183 is a dual low dropout tracking regulator designed to
provide adjustable buffered output voltages that closely track
(±10 mV) the reference inputs. The outputs deliver up to 200 mA
while being able to be configured higher, lower or equal to the
reference voltages.
The outputs have been designed to operate over a wide range (2.8 V
to 45 V) while still maintaining excellent DC characteristics. The
CS8183 is protected from reverse battery, short circuit and thermal
runaway conditions. The device also can withstand 45 V load dump
transients and −50 V reverse polarity input voltage transients. This
makes it suitable for use in automotive environments.
The VREF/ENABLE leads serve two purposes. They are used to
provide the input voltage as a reference for the output and they also
can be pulled low to place the device in sleep mode where it nominally
draws less than 30 mA from the supply.
The two trackers can be combined in parallel doubling the capability
to 400 mA for a single application.
•
•
•
•
•
•
•
•
Two Regulated Outputs 200 mA, ±10 mV Track Worst Case
Low Dropout (0.35 V typ @ 200 mA)
Low Quiescent Current
Independent Thermal Shutdown
Short Circuit Protection
Wide Operating Range
Internally Fused Leads in the SO−20W Package
These are Pb−Free Devices
20
1
SO−20WB
DWF SUFFIX
CASE 751D
PIN CONNECTIONS AND
MARKING DIAGRAM
1
20
VIN1
VOUT1
NC
NC
GND
GND
NC
NC
VADJ1
VREF/ENABLE1
8183
A
WL
YY
WW
G
8183
AWLYYWWG
Features
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VOUT2
VIN2
NC
NC
GND
GND
NC
NC
VREF/ENABLE2
VADJ2
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
CS8183YDWF20G
SO−20WB
(Pb−Free)
38 Units/Rail
CS8183YDWFR20G SO−20WB 1000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2008
October, 2008 − Rev. 18
1
Publication Order Number:
CS8183/D
CS8183
VIN1
VOUT1
Current Limit &
VSAT Sense
Adj1
−
ENABLE
+
VREF/ENABLE1
+
GND
Independent
Thermal
Shutdown
−
2.0 V
VIN2
VOUT2
Current Limit &
VSAT Sense
Adj2
−
ENABLE
+
VREF/ENABLE2
+
Independent
Thermal
Shutdown
−
2.0 V
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Package Lead #
SO−20W
Lead Symbol
1
VIN1
2
VOUT1
3, 4, 7, 8, 13, 14, 17, 18
NC
5, 6, 15, 16
GND
Ground (4 leads fused).
9
VADJ1
Adjust lead for VOUT1.
10
VREF/ENABLE1
11
VADJ2
12
VREF/ENABLE2
19
VIN2
20
VOUT2
Function
Input voltage for VOUT1.
Regulated output voltage 1.
No connection.
Reference voltage and ENABLE input for VOUT1.
Adjust lead for VOUT2.
Reference voltage and ENABLE input for VOUT2.
Input voltage for VOUT2.
Regulated output voltage 2.
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2
CS8183
MAXIMUM RATINGS
Rating
Value
Unit
−65 to 150
°C
Supply Voltage Range (continuous)
15 to 45
V
Supply Voltage Range (normal, continuous)
3.4 to 45
V
45
V
−10 to 45
V
Maximum Junction Temperature
150
°C
Package Thermal Resistance
Junction−to−Case, RqJC
Junction−to−Ambient, RqJA
18
73
°C/W
°C/W
2.0
200
kV
V
240 peak
(Note 2)
°C
Storage Temperature
Peak Transient Voltage (VIN = 14 V, Load Dump Transient = 31 V)
Voltage Range (Adj, VREF/ENABLE, VOUT)
ESD Capability
(Human Body Model)
(Machine Model)
Lead Temperature Soldering
Reflow: (SMD styles only) (Note 1)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 second maximum above 183°C.
2. −5°C/+0°C allowable conditions.
ELECTRICAL CHARACTERISTICS (VIN = 14 V; VREF/ENABLE > 2.75 V; −40°C ≤ TJ ≤ +125°C; COUT ≥ 10 mF;
0.1 W < COUT − ESR < 1.0 W @ 10 kHz; unless otherwise stated.)
Test Conditions
Parameter
Min
Typ
Max
Unit
−10
−
10
mV
REGULAR OUTPUT 1, 2
VREF − VOUT
VOUT Tracking Error
4.5 V ≤ VIN ≤ 26 V, 100 mA ≤ IOUT ≤ 200 mA, (Note 3)
Dropout Voltage (VIN − VOUT)
IOUT = 100 mA
IOUT = 200 mA
−
−
100
350
150
600
mV
mV
Line Regulation
4.5 V ≤ VIN ≤ 26 V, (Note 3)
−
−
10
mV
Load Regulation
100 mA ≤ IOUT ≤ 200 mA, (Note 3)
−
−
10
mV
Adj Lead Current
Loop in Regulation
−
0.2
1.0
mA
Current Limit
VIN = 14 V, VREF = 5.0 V, VOUT = 90% of VREF, (Note 3)
225
−
700
mA
Quiescent Current (IIN − IOUT)
VIN = 12 V, IOUT = 200 mA
VIN = 12 V, IOUT = 100 mA
VIN = 12 V, VREF/ENABLE = 0 V
−
−
−
15
75
30
25
150
55
mA
mA
mA
Reverse Current
VOUT = 5.0 V, VIN = 0 V
−
0.2
1.5
mA
Ripple Rejection
f = 120 Hz, IOUT = 200 mA, 4.5 V ≤ VIN ≤ 26 V
60
−
−
dB
−
150
180
210
°C
−
0.80
2.00
2.75
V
−
0.2
1.0
mA
Thermal Shutdown
VREF/ENABLE 1, 2
Enable Voltage
Input Bias Current
VREF/ENABLE 1, 2 > 2.0 V
3. VOUT connected to Adj lead.
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3
CS8183
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT (mA)
18
16
14
12
10
8
6
4
2
0
0
20
40
60
80
100
120 140 160 180 200
OUTPUT CURRENT (mA)
1
100
0.9
90
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
Figure 2. Quiescent Current vs. Output Current
0.8
0.7
0.6
0.5
0.4
I (Vout) = 20 mA
0.3
0.2
0.1
0
5
10
15
20
70
60
50
40
30
20
Vref / ENABLE = 0 V
10
I (Vout) = 1 mA
0
80
25
30
35
40
0
45
0
5
VIN, INPUT VOLTAGE (V)
14
12
10
8
Vin = 6 V*
Vref = 5 V**
6
4
2
0
Vin = 0 V
0
5
10
15
25
30
35
40
45
140
CURRENT INTO Vout (mA)
CURRENT INTO Vout (mA)
16
20
Figure 4. Quiescent Current vs. Input Voltage
(Sleep Mode)
* Graph is duplicate for Vin > 1.6V.
**Dip (@5V) shifts with Vref voltage.
18
15
VIN, INPUT VOLTAGE (V)
Figure 3. Quiescent Current vs. Input Voltage
(Operating Mode)
20
10
20
100
Vin = 0 V
80
60
Vin = 6 V*
Vref = 5 V**
40
20
0
25
* Graph is duplicate for Vin > 1.6V.
**Dip (@5V) shifts with Vref voltage.
120
0
FORCED Vout VOLTAGE (V)
5
10
15
20
25
30
FORCED Vout VOLTAGE (V)
Figure 5. Vout Reverse Current
Figure 6. Vout Reverse Current
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4
35
40
CS8183
CIRCUIT DESCRIPTION
ENABLE Function
The outputs are capable of supplying 200 mA to the load
while configured as a similiar (Figure 7), lower (Figure 9),
or higher (Figure 8) voltage as the reference lead. The Adj
lead acts as the inverting terminal of the op amp and the
VREF lead as the non−inverting.
The device can also be configured as a high−side driver as
displayed in Figure 12.
By pulling the VREF/ENABLE 1, 2 lead below 2.0 V
typically, (see Figure 10 or Figure 11), the IC is disabled and
enters a sleep state where the device draws less than 30 mA
from supply. When the VREF/ENABLE lead is greater than
2.75 V, VOUT tracks the VREF/ENABLE lead normally.
Output Voltage
Figures 7 through 12 only display one channel of the
device for simplicity. The configurations shown apply
for both channels.
Adj
GND
GND
VREF/
ENABLE
Adj
5.0 V
C3***
10 nF
RA
GND
Adj
CS8183
GND
VOUT, 200 mA
B+
VIN
C2**
10 mF
C1*
1.0 mF
GND
VREF/
ENABLE
VOUT
GND
GND
R1
VREF/
ENABLE
GND
VREF
C3***
10 nF
Figure 8. Tracking Regulator at Higher Voltages
Figure 7. Tracking Regulator at the Same Voltage
GND
C1*
1.0 mF
R
VOUT + VREF(1 ) E)
RA
VOUT + VREF
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 mF
B+
VIN
CS8183
C1*
1.0 mF
C3***
10 nF
Adj
VREF
R2
B+
VIN
CS8183
GND
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 mF
RF
GND
B+
VIN
CS8183
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 mF
C1*
1.0 mF
GND
GND
VREF/
ENABLE
from MCU
R
C3***
10 nF
VREF
VOUT + VREF( R2 )
R1 ) R2
Figure 9. Tracking Regulator at Lower Voltages
NCV8501
VREF (5.0 V)
200 mA
100 nF
5.0 V
To Load 10 mF
(e.g. sensor)
GND
GND
Adj
VIN
CS8183
VOUT
GND
GND
mC
C1*
1.0 mF
GND
Adj
GND
VREF/
ENABLE
VOUT
I/O
C3***
10 nF
B+
VIN
CS8183
VIN
6.0 V−40 V
Figure 10. Tracking Regulator with ENABLE Circuit
GND
GND
VREF/
ENABLE
C3***
10 nF
VOUT + B ) * VSAT
Figure 11. Alternative ENABLE Circuit
Figure 12. High−Side Driver
* C1 is required if the regulator is far from the power source filter
** C2 is required for stability
*** C3 is recommended for EMC susceptibility
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5
MCU
CS8183
VOUT
400 mA
400 mA Output Capability
Normally regulator outputs cannot be combined to
increase capability. This can cause damage to an IC because
of mismatches in the output drivers. The tight tolerances in
tracking of the CS8183 allow their outputs to be combined
for increased performance. Figure 13 shows the circuit
connections needed to perform this function.
C2
20 mF
B+
C1
2.0 mF
VIN1
VOUT1
NC
NC
GND
GND
NC
NC
VADJ1
VOUT2
VIN2
NC
NC
GND
GND
NC
NC
VREF/
ENABLE2
VADJ2
VREF/
ENABLE1
VREF
Figure 13. 400 mA Loading
APPLICATION NOTES
Switched Application
Worst−case is determined at the minimum ambient
temperature and maximum load expected.
The output capacitors can be increased in size to any
desired value above the minimum. One possible purpose of
this would be to maintain the output voltage during brief
conditions of negative input transients that might be
characteristic of a particular system.
The capacitors must also be rated at all ambient
temperatures expected in the system. To maintain regulator
stability down to −40°C, a capacitor rated at that temperature
must be used.
More information on capacitor selection for SMART
REGULATOR®s is available in the SMART REGULATOR
application note, “Compensation for Linear Regulators.”
The CS8183 has been designed for use in systems where
the reference voltage on the VREF/ENABLE pin is
continuously on. Typically, the current into the
VREF/ENABLE pin will be less than 1.0 mA when the
voltage on the VIN pin (usually the ignition line) has been
switched out (VIN can be at high impedance or at ground.)
Reference Figure 14.
Ignition
Switch
VOUT
VOUT
VIN
GND
GND
GND
Adj
CS8183
C2
10 mF
C1
1.0 mF
VBAT
Calculating Power Dissipation in a Dual Output Linear
Regulator
GND
VREF/
ENABLE
< 1.0 mA
The maximum power dissipation for a dual output
regulator (Figure 15) is:
VREF
5.0 V
PD(max) + {VIN(max) * VOUT1(min)} IOUT1(max)
) {VIN(max) * VOUT2(min)}IOUT2(max2)
) VIN(max)IQ
(1)
Figure 14.
External Capacitors
where:
VIN(max) is the maximum input voltage,
VOUT1(min) is the minimum output voltage from VOUT1,
VOUT2(min) is the minimum output voltage from VOUT2,
Output capacitors for the CS8183 are required for
stability. Without them, the regulator outputs will oscillate.
Actual size and type may vary depending upon the
application load and temperature range. Capacitor effective
series resistance (ESR) is also a factor in the IC stability.
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6
CS8183
Heatsinks
IOUT1(max) is the maximum output current, for the
application,
IOUT2(max) is the maximum output current, for the
application,
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA + 150C * TA
PD
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
(2)
RqJA + RqJC ) RqCS ) RqSA
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
VIN
IIN
SMART
REGULATOR
(3)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heatsink thermal resistance, and
RqSA = the heatsink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
IOUT
VOUT
Control
Features
IQ
Figure 15. Dual Output Regulator with Key
Performance Parameters Labeled
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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