CS1501-FSZ

CS1501 Digital Power Factor Correction Control IC Features & Description  Digital EMI Noise Shaping  Adaptive Digital Energy Controller • Excellent Efficiency Under All Load and Line Conditions • Zero-voltage Switching Topology Overview The CS1501 is a high-performance digital power factor correction (PFC) controller designed for switching mode power supply (SMPS) applications. The CS1501 actively manages the power factor correction while achieving high efficiency over a wide load range. The CS1501 adaptively controls the input AC current so that it is in phase with the AC mains voltage and its waveform mimics the input voltage waveform. The PFC controller executes adaptive digital algorithms designed to shape the AC mains input current waveform to be in phase with the input voltage waveform. The CS1501 is equipped with a zero-current detection (ZCD) circuit providing the PFC digital controller the capability to turn on the MOSFET when the voltage across the drain and source is near zero. Additionally, a current-sensing circuit is incorporated for instantaneous overcurrent protection.  Minimal External Devices Required  Adaptive Digital Control Loop  Comprehensive Safety Features • Undervoltage Lockout (UVLO) • Output Overvoltage Protection • Cycle-by-cycle Current Limiting • Open/Short Loop Protection for IAC & IFB Pins • Thermal Shutdown  Pin placement similar to traditional boundary mode (CRM) Controllers Applications & Description  LCD and LED TVs  Notebooks  Server/Telecom Ordering Information See page 15. Vrect LB D1 Vlink BR1 BR1 R1 R2 R3 5 ZCD 3 IAC STBY VDD R5 R6 AC Mains 8 VDD 1 IFB GD C1 7 4 Q1 C2 CS1501 CS GND Regulated DC Output BR 1 BR 1 R4 2 6 R7 P reliminary Product Information Cirrus Logic, Inc. http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2011 (All Rights Reserved) JUN ’11 DS927PP6 CS1501 1. INTRODUCTION V DD 600k Voltage Regulator POR + V DD 8 VDD STBY 2 VDD 15k - VDD (on ) VDD (off) VZ Iref 24k ADC IFB 1 VDD 15k Iref 24k ADC 7 GD GND IAC 3 t LEB t ZCB 6 CS 4 600 VCS(th) + + - CS Threshold CS Clamp Zero Crossing Detect VCS(clamp ) - + - V ZCD(th) 5 ZCD Figure 1. CS1501 Block Diagram The CS1501 digital power factor correction (PFC) control IC is designed to deliver the lowest system cost by reducing the total number of system components and optimizing the EMI noise signature, which reduces the conducted EMI filter requirements. The CS1501 digital algorithm determines the behavior of the boost converter during startup, normal operation, and under fault conditions (overvoltage, overcurrent, and overtemperature). Figure 1 illustrates a high-level block diagram of the CS1501. The PFC processor logic regulates the power transfer by using an adaptive digital algorithm to optimize the PFC active-switch (MOSFET) drive signal duty cycle and switching frequency. The adaptive controller uses independent analog-to-digital converter (ADC) channels when sensing the feedback and feedforward analog signals required to implement the digital PFC control algorithm. The AC mains rectified voltage (on pin IAC) and PFC output link voltage (on pin IFB) are transformed by the PFC processor logic and used to generate the optimum PFC active-switch drive signal (GD) by calculating the optimal switching frequency and tON time on a cycle-by-cycle basis. An auxiliary winding is typically added to the PFC boost inductor to provide zero-current detection (ZCD) information. The ZCD acts as a demagnetization sensor used to monitor the PFC active-switching behavior and efficiency. The auxiliary voltage is normalized using an external attenuator and is connected to the ZCD pin, providing the CS1501 a mechanism to detect the valley/zero crossings. The ZCD comparator looks for the zero crossing on the auxiliary winding and switches when the auxiliary voltage is below zero. Switching in the valley of the oscillation minimizes the switching losses and reduces EMI noise. The PFC controller uses a current sensor for overcurrent protection. The boost inductor peak current is measured across an external resistor in the switching circuit on a cycle-by-cycle basis. An overcurrent fault is generated when the sense voltage applied to the CS pin exceeds a predefined reference voltage. The CS1501 includes a supervisor & protection circuit to manage startup, shutdown, and fault conditions. The protection circuit is designed to prevent output overvoltage as a result of load and AC mains transients. The PFC power converter main rectified voltage (Vrect) and output link voltage (Vlink) are monitored for overvoltage faults which would lead to shutdown of the PFC controller. The PFC overvoltage protection is designed for auto-recovery, i.e. operation resumes once the fault clears. 2 DS927PP6 CS1501 2. PIN DESCRIPTION Link V oltage S ens e S tandby Rec tifier V oltage S ens e P FC Current S ens e IFB S TBY IAC CS 1 2 3 4 8 7 6 5 V DD GD GND ZCD IC S upply V oltage P FC Gate Driv er Ground P FC Zero-c urrent Detec t 8-lead S OIC Figure 2. CS1501 Pin Assignments Pin Name IFB STBY IAC Pin # I/O Description Link Voltage Sense — A current proportional to the output link voltage of the PFC is input into this pin. The current is measured with an ADC. Standby — A voltage below 0.8V puts the IC into a non-operating, low-power state. The input has an internal 600k pull-up resistor to the VDD pin. Rectifier Voltage Sense — A current proportional to the rectified line voltage is input into this pin. The current is measured with an ADC. PFC Current Sense — The current flowing in the PFC MOSFET is sensed through a resistor. The resulting voltage is applied to this pin and digitized for use by the PFC computational logic to limit the maximum current through the power FET. Zero-current Detect — Boost Inductor demagnetization sensing input for zero-current detection (ZCD) information. The pin is externally connected to the PFC boost inductor auxiliary winding through an external resistor divider. Ground — Common reference. Current return for both the input signal portion of the IC and the gate driver. PFC Gate Driver — The totem pole stage is able to drive the power MOSFET with a peak current of 0.5A source and 1.0A sink. IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the gate driver. A storage capacitor is connected on this pin to serve as a reservoir for operating current for the device, including the gate drive current to the power transistor. This pin is clamped to a maximum voltage (Vz) by an internal zener function. 1 2 3 IN IN IN CS 4 IN ZCD 5 6 7 IN PWR OUT GND GD VDD 8 PWR DS927PP6 3 CS1501 3. CHARACTERISTICS AND SPECIFICATIONS 3.1 Electrical Characteristics Minimum/Maximum characteristics conditions: TJ = -40° to +125°C, VDD = 10V to 15V, GND = 0V Typical characteristics conditions: TA = 25°C, VDD = 13V, GND = 0V All voltages are measured with respect to GND. Unless otherwise specified, all current are positive when flowing into the IC. Parameter VDD Supply Voltage Operating Range Turn-on Threshold Voltage Turn-off Threshold Voltage (UVLO) UVLO Hysteresis Zener Voltage VDD Supply Current Startup Supply Current Operating Supply Reference Reference Current PFC Gate Drive Output Source Resistance Output Sink Resistance Rise Time 3 Fall Time 3 Output Voltage Low State Output Voltage High State Zero-current Detection (ZCD) ZCD Threshold ZCD Blanking ZCD Sink/Source Current Upper Voltage Clamp Overvoltage Protection (OVP) IFB Current at Startup Mode IFB Current at Normal Mode OVP Threshold OVP Hysteresis Overcurrent Protection (OCP) Current Sense Reference Clamp Threshold on Current Sense Leading Edge Blanking Delay to Output VCS(clamp) VCS(th) tLEB tCS 1.0 0.5 300 60 350 V V ns ns Iref = 129A Iref = 129A IIFB(startup) IIFB(norm) IOVP IOVP(Hy) 116 129 136 2 A A A A VZCD = 50mV IZCD = 1mA VZCD(th) tZCB IZCD VCLP -2 50 200 -1 VDD 2 mV ns mA V IGD = 100mA, VDD = 13V IGD = -200mA, VDD = 13V CL = 1nF, VDD = 13V CL = 1nF, VDD = 13V IGD = -200mA, VDD = 13V IGD = 100mA, VDD = 13V ROH ROL tr tf Vol Voh 11.3 9 6 32 15 0.9 11.8 45 25 1.3   ns ns V V Iref 129 A Current 3 Standby Supply Current VDD = VDD(on) CL = 1nF, fsw = 70kHz STBY < 0.8V IST IDD ISB 68 1.5 80 80 1.7 112 A mA A IDD = 20mA After Turn-on VDD Increasing VDD Decreasing VDD VDD(on) VDD(off) VHys VZ 7.9 9.8 7.9 17.0 10.2 8.1 2.1 17.9 17.0 10.5 8.3 18.7 V V V V V Condition Symbol Min Typ Max Unit 4 DS927PP6 CS1501 Parameter Brownout Protection (BP) Input Brownout Protection Threshold Input Brownout Recovery Threshold Thermal Protection 1 Thermal Shutdown Threshold Thermal Shutdown Hysteresis STBY Input 2 Logic Threshold Low Logic Threshold High Condition gate drive turns off gate drive turns on Symbol IBP(lower) IBP(upper) TSD TSD(Hy) Min 134 VDD-0.8 Typ 31.6 39.6 147 9 - Max 159 0.8 - Unit A A °C °C V V Notes: 1. Specifications guaranteed by design and are characterized and correlated using statistical process methods. 2. 3. STBY is designed to be driven by an open collector. The input is internally pulled up with a 600k resistor. For test purposes, load capacitance (CL) is 1nF and is connected as shown in the following diagram. V DD VDD GD CS GND +15V TP Buffer S1 CL 1nF R1 R2 -15V GD OUT S2 R3 DS927PP6 5 CS1501 3.2 Absolute Maximum Ratings Pin 8 1,3,4,5 1,3,4,5 7 7 All Pins Symbol VDD VGD IGD PD IC Supply Voltage Analog Input Maximum Voltage Analog Input Maximum Current Gate Drive Output Voltage Gate Drive Output Current Total Power Dissipation @ TA = 50 °C Junction-to-Ambient Thermal Impedance Operating Ambient Temperature Range 1 Junction Temperature Operating Range Storage Temperature Range Electrostatic Discharge Capability ESD Human Body Model Machine Model Charged Device Model Parameter Value VZ -0.5 to VZ 50 -0.3 to VZ -1.0 / +0.5 600 107 -40 to +125 -40 to +125 -65 to +150 2000 200 500 Unit V V mA V A mW °C/W °C °C °C V JA TA TJ TStg Notes: 4. The CS1501 has an internal shunt regulator that limits the voltage on the VDD pin. VZ, the shunt regulation voltage, is defined in the VDD Supply Voltage section of the Characteristics and Specifications section on the previous page. 5. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at the rate of 50mW/ °C for variation over temperature. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 6 DS927PP6 CS1501 4. TYPICAL ELECTRICAL PERFORMANCE 3.5 3. 2.5 2 1.8 Supply Current (mA) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 Operating fSW(max) = 70kHz IDD (mA) 2. 1.5 1. Rising Falling 0.5 0. Start-up -50 0 50 100 150 0 2 4 6 8 10 12 14 16 18 0 VDD (V) Figure 3. Supply Current vs. Supply Voltage Temperature (oC) Figure 4. Supply Current (ISB, IST, IDD) vs. Temp 3 11 10.5 10 Turn On UVLO Hysteresis 2 VDD (V) 1 9.5 9 8.5 8 7.5 Turn Off 0 -40 0 40 80 120 7 -60 -10 40 90 140 Temperature (OC) Temperature (OC) Figure 5. UVLO Hysteresis vs. Temp Figure 6. Turn-on & Turn-off Threshold vs. Temp 0.5% 0.0% -0.5% Iref Drift -1.0% -1.5% -2.0% -2.5% -3.0% -50 0 50 100 150 Temperature (oC) Figure 7. Reference Current (Iref) Drift vs. Temp DS927PP6 7 CS1501 14 106% Vlink (Normalized at 25OC) Source 12 10 8 6 4 2 0 -60 Sink VDD = 13 V Isource = 100 mA Isink = 200 mA 104% 102% 100% 98% 96% -50 0 OVP Zout (Ohm) Normal -40 Gate Resistor (ROH, ROL) Temp (oC) -20 0 20 40 60 80 100 120 140 50 Temperature (OC) 100 150 Figure 8. Gate Resistance (ROH, ROL) vs. Temp Figure 9. OVP vs. Temp 19 IDD = 20 mA 18.5 VZ (V) 18 17.5 17 -50 0 50 100 150 Temperature (oC) Figure 10. VDD Zener Voltage vs. Temp 8 DS927PP6 CS1501 5. GENERAL DESCRIPTION The CS1501 offers numerous features, options, and functional capabilities to the designer of switching power converters. This digital PFC control IC is designed to replace legacy analog PFC controllers with minimal design effort. input under full load, the PFC controller will function as a quasi-CRM controller at the peak of the AC line cycle, as shown in Figure 13. DCM Quasi CRM DCM Quasi CRM DCM Inductor Current 5.1 PFC Operation One key feature of the CS1501 is its operating frequency profile. Figure 11 illustrates how the frequency varies over one half cycle of the line voltage in steady-state operation. When power is first applied to the CS1501, it examines the line voltage and adapts its operating frequency to the line voltage as shown in Figure 11. The operating frequency is varied from the peak to the trough of the AC input. During startup, the control algorithm generates maximum power while operating in critical conduction mode (CRM), providing an approximate square-wave current envelop within every half-line cycle. 120 Switching Freq. (% of Max.) ILB IAC t [ms] Figure 13. DCM and quasi-CRM Operation with CS1501 The zero-current detection (ZCD) of the boost inductor is achieved using an auxiliary winding. When the stored energy of the inductor is fully released to the output, the voltage on the ZCD pin decreases, triggering a new switching cycle. This quasi-resonant switching allows the active switch to be turned on with near-zero inductor current, resulting in a nearly lossless switch event. This minimizes turn-on losses and EMI noise created by the switching cycle. Power factor correction control is achieved during light load by using on-time modulation. 100 % of Max 80 60 40 20 0 0 45 90 135 180 Rectified Line Voltage Phase (Deg.) Line Voltage (% of Max.) 5.2 Startup vs. Normal Operation Mode The CS1501 has two discrete operation modes: startup and normal. Startup mode will be activated when Vlink is less than 90% of nominal value, VO(startup) and remains active until Vlink reaches 100% of nominal value, as shown in Figure 14. Startup mode is activated during initial system power-up. Any Vlink drop to less than VO(startup), such as a load change, can cause the system to enter startup mode until Vlink is brought back into regulation. Vlink [V] Figure 11. Switching Frequency vs. Phase Angle Figure 12 illustrates how the operating frequency (as a percentage of maximum frequency) changes with output power and the peak of the line voltage. 70 Vin < 181 VAC F SW max (kHz) 60 56 50 46 40 Burst Mode 100% Startup Mode Startup Mode Vin > 147 VAC 90% 20 Normal Mode Normal Mode 0 5 20 40 60 80 100 % PO max Figure 12. Max. Switching Frequency vs. Output Power When PO falls below 5%, the CS1501 changes to Burst Mode. (Refer to Burst Mode section for more information.) The CS1501 is designed to function as a DCM controller. However, during peak periods, the controller may interchange control methods and operate in a quasi-critical-conduction mode (quasi-CRM) at low line. For example, at 90VAC main t [ms] Figure 14. Startup and Normal Modes Startup mode is defined as a surge of current delivering maximum power to the output regardless of the load. During every active switch cycle, the 'ON' time is calculated to drive a constant peak current over the entire line cycle. However, the 'OFF' time is calculated based on the DCM/CCM boundary equation. DS927PP6 9 CS1501 5.3 Burst Mode Burst mode is utilized to improve system efficiency when the system output power (Po) is