CS5566-ISZ

5/4/09 CS5566 ±2.5 V / 5 V, 5 kSps, 24-bit ΔΣ ADC Features & Description  Differential Analog Input  On-chip Buffers for High Input Impedance  Conversion Time = 200 μS  Settles in One Conversion  Linearity Error = 0.0005%  Signal-to-Noise = 110 dB  24 Bits, No Missing Codes  Simple three/four-wire serial interface  Power Supply Configurations: - Analog: +5V/GND; IO: +1.8V to +3.3V - Analog: ±2.5V; IO: +1.8V to +3.3V General Description The CS5566 is a single-channel, 24-bit analog-to-digital converter capable of 5 kSps conversion rate. The input accepts a fully differential analog input signal. On-chip buffers provide high input impedance for both the AIN inputs and the VREF+ input. This significantly reduces the drive requirements of signal sources and reduces errors due to source impedances. The CS5566 is a delta-sigma converter capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in one conversion. The converter's 24-bit data output is in serial form, with the serial port acting as either a master or a slave. The converter is designed to support bipolar, ground-referenced signals when operated from ±2.5V analog supplies. The converter can operate from an analog supply of 0-5V or from ±2.5V. The digital interface supports standard logic operating from 1.8, 2.5, or 3.3 V.  Power Consumption: 20 mW @ 5 kSps ORDERING INFORMATION: See Ordering Information on page 30. V1+ V2+ VL CS5566 VREF+ VREFCS SMODE ADC AI N + AI N- DIGITAL FILTER LOGIC SERIAL INTERFACE SCLK SDO RDY SLEEP BUFEN RST DIGITAL CONTROL OSC/CLOCK GENERATOR CONV BP/UP MCLK V1- V2- TST DCR VLR VLR2 Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2009 (All Rights Reserved) MAY ‘09 DS806PP2 5/4/09 CS5566 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DIGITAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DIGITAL FILTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 GUARANTEED LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 Output Coding Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7 Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 AIN & VREF Sampling Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 Converter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 Using the CS5566 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4. PIN DESCRIPTIONS 26 5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . 30 8. REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2 DS806PP2 5/4/09 CS5566 LIST OF FIGURES Figure 1. Converter Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SSC Mode - Read Timing, CS falling after RDY falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. SEC Mode - Continuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. SEC Mode - Discontinuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Power Consumption vs. Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. CS5566 Configured Using ±2.5V Analog Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9. CS5566 Configured Using a Single 5V Analog Supply . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10. CS5566 DNL Plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11. Spectral Performance, 0 dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12. Spectral Performance, -6 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13. Spectral Performance, -12 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14. Spectral Performance, -20 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 15. Spectral Performance, -80 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 16. Spectral Performance, -120 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 17. Spectral Performance, -130 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 19. Noise Histogram (4096 Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 18. Spectral Plot of Noise with Shorted Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 20. Digital Filter Response (DC to 2.5 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LIST OF TABLES Table 1. Output Coding, Two’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2. Output Coding, Offset Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DS806PP2 3 5/4/09 1. CHARACTERISTICS AND SPECIFICATIONS • • • CS5566 Min / Max characteristics and specifications are guaranteed over the specified operating conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. VLR = 0 V. All voltages with respect to 0 V. ANALOG CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL. BUFEN = V1+ unless otherwise stated. Connected per Figure 8. Bipolar mode unless otherwise stated. Parameter Accuracy Linearity Error Differential Linearity Error Positive Full-scale Error Negative Full-scale Error Full-scale Drift Bipolar Offset Bipolar Offset Drift Noise Dynamic Performance Peak Harmonic or Spurious Noise Total Harmonic Distortion Signal-to-Noise S/(N + D) Ratio -3 dB Input Bandwidth Analog Input Analog Input Range (Differential) Input Capacitance CVF Current (Note 4) AIN Buffer On (BUFEN = V+) AIN Buffer Off (BUFEN = V-) Unipolar Bipolar -100 0 to +VREF ±VREF 10 600 130 -110 V V pF nA μA dB -0.5 dB Input, 200 Hz -60 dB Input, 200 Hz (Note 3) 200 Hz, -0.5 dB Input 200 Hz, -0.5 dB Input 108 -115 -110 110 109 50 21 -100 dB dB dB dB dB kHz (Note 2) (Note 2) (Note 2) (Note 1) 0.0005 ±0.1 1.0 1.0 1 ±500 1 9.5 ±%FS LSB24 %FS %FS PPM / °C LSB24 LSB / °C μVrms Min Typ Max Unit Common Mode Rejection Ratio (DC to 2 kHz) 1. 2. 3. 4. No missing codes is guaranteed at 24 bits resolution over the specified temperature range. One LSB is equivalent to (2 x VREF) ÷ 224 or (2 x 4.096) ÷ 16,777,216 = 488 nV. Scales with MCLK. Measured using an input signal of 1 V DC. 4 DS806PP2 5/4/09 CS5566 TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL.; BUFEN = V1+ unless otherwise stated. Connected per Figure 8. Parameter Voltage Reference Input Voltage Reference Input Range (VREF+) – (VREF-) Input Capacitance CVF Current VREF+ Buffer On (BUFEN = V+) VREF+ Buffer Off (BUFEN = V-) VREFIV1 IV2 IVL IV1 IV2 IVL (Note 5) 2.4 75 75 4.096 10 3 1 1 20 15 6 85 85 4.2 5 0.6 0.4 9 1.2 280 V pF μA mA mA mA mA mA mA mA μA mW mW mW dB dB Min Typ Max Unit ANALOG CHARACTERISTICS (CONTINUED) Power Supplies Average DC Power Supply Currents (Note 6) Peak DC Power Supply Currents (Note 6) Average Power Consumption Normal Operation Buffers On (Note 6) Buffers Off Sleep (SLEEP = 0) (Note 7) V1+ , V2+ Supplies V1-, V2- Supplies Power Supply Rejection 5. 6. 7. For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer. Specification is for MCLK = 8MHz and 5 kSps conversion rate. MCLK frequency and conversion rate affect power consumption. See Section 3.2 Power Consumption for more details. Tested with 100 mVP-P on any supply up to 2 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at the same voltage potential. DS806PP2 5 5/4/09 SWITCHING CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Master Clock Frequency Master Clock Duty Cycle Reset RST Low Time RST rising to RDY falling Conversion CONV Pulse Width BP/UP setup to CONV falling CONV low to start of conversion Perform Single Conversion (CONV high before RDY falling) Conversion Time Sleep Mode SLEEP low to low-power state SLEEP high to device active (Note 10) 8. 9. CS5566 Symbol Internal Oscillator External Clock XIN fclk Min 6 0.5 40 Typ 7 8 240 3084 1182 50 3083 Max 8 8.1 60 1186 1604 - Unit MHz MHz % µs µs MCLKs MCLKs ns MCLKs MCLKs MCLKs µs MCLKs tres Internal Oscillator External Clock twup 1 4 0 20 - tcpw (Note 8) tscn tscn tbus tbuh tcon tcon (Note 9) Start of Conversion to RDY falling BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls. If CONV is held low continuously, conversions occur every 1600 MCLK cycles. If RDY is tied to CONV, conversions will occur every 1602 MCLKs. If CONV is operated asynchronously to MCLK, a conversion may take up to 1604 MCLKs. RDY falls at the end of conversion. 10. RDY will fall when the device is fully operational when coming out of sleep mode. tbus CONVERT RDY Converter Status IDLE CONVERT SDO ACTIVE IDLE 1182 - 1186 MCLKs 1600 - 1604 MCLKs 354 + 64 MCLKs Figure 1. Converter Status (Not to scale) 6 DS806PP2 5/4/09 CS5566 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Serial Port Timing in SSC Mode (SMODE = VL) Symbol t1 t2 Pulse Width (low) Pulse Width (high) t3 t4 t5 Min 100 100 - Typ -2 10 8 Max - Unit MCLKs ns ns ns MCLKs RDY falling to MSB stable Data hold time after SCLK rising Serial Clock (Out) (Note 11, 12) RDY rising after last SCLK rising 11. 12. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resistor. SCLK = MCLK/2. MCLK RDY t1 CS t2 SCLK(o) t3 t4 t5 SDO MSB MSB–1 LSB+1 LSB Figure 2. SSC Mode - Read Timing, CS remaining low (Not to Scale) DS806PP2 7 5/4/09 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Serial Port Timing in SSC Mode (SMODE = VL) CS5566 Symbol t7 Pulse Width (low) Pulse Width (high) t8 t9 t10 t11 t12 t13 t14 Min 100 100 10 - Typ 10 8 10 8 5 Max - Unit ns ns ns MCLKs ns MCLKs ns ns Data hold time after SCLK rising Serial Clock (Out) (Note 13, 14) RDY rising after last SCLK rising CS falling to MSB stable First SCLK rising after CS falling CS hold time (low) after SCLK rising SCLK, SDO tri-state after CS rising 13. SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down resistors. 14. SCLK = MCLK/2. MCLK t10 RDY t13 CS t12 SCLK(o) t11 SDO MSB MSB–1 LSB+1 LSB t7 t8 t9 t14 Figure 3. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale) 8 DS806PP2 5/4/09 CS5566 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Serial Port Timing in SEC Mode (SMODE = VLR) Symbol - Min 30 30 10 10 10 10 - Typ 10 10 10 Max 1 10 SCLK Unit ns ns ns ns ns ns ns ns ns SCLK(in) Pulse Width (High) SCLK(in) Pulse Width (Low) CS hold time (high) after RDY falling CS hold time (high) after SCLK rising CS low to SDO out of Hi-Z Data hold time after SCLK rising Data setup time before SCLK rising CS hold time (low) after SCLK rising RDY rising after SCLK falling 15. t15 t16 (Note 15) t17 t18 t19 t20 t21 - SDO will be high impedance when CS is high. In some systems SDO may require a pull-down resistor. MCLK t21 RDY t15 CS t16 SCLK(i) t17 SDO t18 t19 MSB LSB t20 Figure 4. SEC Mode - Continuous SCLK Read Timing (Not to Scale) DS806PP2 9 5/4/09 CS5566 MCLK t21 RDY t15 CS t20 SCLK(i) t17 SDO t18 t19 MSB LSB Figure 5. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale) DIGITAL CHARACTERISTICS TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V Parameter Input Leakage Current Digital Input Pin Capacitance Digital Output Pin Capacitance Symbol Iin Cin Cout Min Typ 3 3 Max 2 Unit µA pF pF DIGITAL FILTER CHARACTERISTICS TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V Parameter Group Delay 16. Symbol (Note 16) - Min - Typ 160 Max - Unit MCLKs See Figure 4 to understand conversion timing. The 160 MCLK group delay occurs during the 354 MCLK high-power period of a conversion cycle. See Section 3.2 Power Consumption for more detail. 10 DS806PP2 5/4/09 CS5566 GUARANTEED LOGIC LEVELS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF. Guaranteed Limits Parameter Logic Inputs 3.3 Minimum High-level Input Voltage: Sym VL Min Typ Max Unit Conditions 1.9 1.6 1.2 1.1 0.95 0.6 V V VIH 2.5 1.8 3.3 Maximum Low-level Input Voltage: VIL 2.5 1.8 Logic Outputs 3.3 Minimum High-level Output Voltage: 2.9 2.1 1.65 0.36 0.36 0.44 V IOH = -2 mA VOH 2.5 1.8 3.3 V IOH = -2 mA Maximum Low-level Output Voltage: VOL 2.5 1.8 DS806PP2 11 5/4/09 RECOMMENDED OPERATING CONDITIONS (VLR = 0V, see Note 17) CS5566 Parameter Single Analog Supply DC Power Supplies: (Note 17) V1+ V2+ V1V2- Symbol Min Typ Max Unit V1+ V2V1+ V2- 4.75 4.75 - 5.0 5.0 0 0 5.25 5.25 - V V V V Dual Analog Supplies DC Power Supplies: (Note 17) V1+ V2+ V1V2(Note 18) [VREF+] – [VREF-] V1+ V2V1+ V2VREF +2.375 +2.375 -2.375 -2.375 2.4 +2.5 +2.5 -2.5 -2.5 4.096 +2.625 +2.625 -2.625 -2.625 4.2 V V V V V Analog Reference Voltage 17. 18. The logic supply can be any value VL – VLR = +1.71 to +3.465 volts as long as VLR ≥ V2- and VL ≤ 3.465 V. The differential voltage reference magnitude is constrained by the V1+ or V1- supply magnitude. ABSOLUTE MAXIMUM RATINGS (VLR = 0V) Parameter DC Power Supplies: [V1+] – [V1-] (Note 19) VL + [ |V1-| ] (Note 20) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Storage Temperature Notes: 19. V1+ = V2+; V1- = V220. 21. Symbol IIN VINA VIND Tstg Min 0 0 (V1-) – 0.3 VLR – 0.3 -65 Typ - Max 5.5 6.1 ±10 (V1+) + 0.3 VL + 0.3 150 Unit V V mA V V °C (Note 21) (AIN and VREF pins) V1- = V2Transient currents of up to 100 mA will not cause SCR latch-up. WARNING: Recommended Operating Conditions indicate limits to which the device is functionally operational. Absolute Maximum Ratings indicate limits beyond which permanent damage to the device may occur. The Absolute Maximum Ratings are stress ratings only and the device should not be operated at these limits. Operation at conditions beyond the Recommended Operating Conditions may affect device reliability, and functional operation beyond Recommended Operating Conditions is not implied. Performance specifications are intended for the conditions specified for each table in the Characteristics and Specifications section. 12 DS806PP2 5/4/09 CS5566 2. OVERVIEW The CS5566 is a 24-bit analog-to-digital converter capable of 5 kSps conversion rate. The device is capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in one conversion. The converter is a serial output device. The serial port can be configured to function as either a master or a slave. The converter can operate from an analog supply of 5V or from ±2.5V. The digital interface supports standard logic operating from 1.8, 2.5, or 3.3 V. The CS5566 converts at 5 kSps when operating from a 8 MHz input clock. 3. THEORY OF OPERATION The CS5566 converter provides high-performance measurement of DC or AC signals. The converter can be used to perform single conversions or continuous conversions upon command. Each conversion is independent of previous conversions and can settle to full specified accuracy, even with a full-scale input voltage step. This is due to the converter architecture which uses a combination of a high-speed delta-sigma modulator and a low-latency filter architecture. Once power is established to the converter, a reset must be performed. A reset initializes the internal converter logic. If CONV is held low then the converter will convert continuously with RDY falling every 1600 MCLKs. This is equivalent to 5 kSps if MCLK = 8.0 MHz. If CONV is tied to RDY, a conversion will occur every 1602 MCLKs. If CONV is operated asynchronously to MCLK, it may take up to 1604 MCLKs from CONV falling to RDY falling. Multiple converters can operate synchronously if they are driven by the same MCLK source and CONV to each converter falls on the same MCLK falling edge. Alternately, CONV can be held low and all devices are reset with RST rising on the same falling edge of MCLK. The output coding of the conversion word is a function of the BP/UP pin. The active-low SLEEP signal causes the device to enter a low-power state. When exiting sleep, the converter will take 3083 MCLK cycles before conversions can be performed. RST should remain inactive (high) when SLEEP is asserted (low). DS806PP2 13 5/4/09 3.1 Converter Operation The converter should be reset after the power supplies and voltage reference are stable. CS5566 The CS5566 converts at 5 kSps when synchronously operated (CONV = VLR) from a 8.0 MHz master clock. Conversion is initiated by taking CONV low. A conversion lasts 1600 master clock cycles, but if CONV is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to when a conversion actually begins. This may extend the throughput to 1604 MCLKs When the conversion is completed, the output word is placed into the serial port and RDY goes low. To convert continuously, CONV should be held low. In continuous conversion mode with CONV held low, a conversion is performed in 1600 MCLK cycles. Alternately RDY can be tied to CONV and a conversion will occur every 1602 MCLK cycles. To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY falls. Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data is put into the port register. See Section 3.11 Serial Port for information about reading conversion data. Conversion performance can be affected by several factors. These include the choice of clock source for the chip, the timing of CONV, and the choice of the serial port mode. The converter can be operated from an internal oscillator. This clock source has greater jitter than an external crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-frequency AC signals, but can become an issue for higher frequency AC signals. For maximum performance when digitizing AC signals, a low-jitter MCLK should be used. To maximize performance, the CONV pin should be held low in the continuous conversion state to perform multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK falls. If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause interference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interference due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a conversion is not in progress. 14 DS806PP2 5/4/09 CS5566 3.2 Power Consumption The power consumption of the CS5566 converter is a function of the conversion rate. Figure 6 illustrates the typical power consumption of the converter when operating from either MCLK = 8 MHz or MCLK = 4 MHz. The rate at which conversions are performed directly affects the power consumption. When the converter is powered but not converting, it is in an idle state where its power consumption is about 11 mW. When the CONV signal goes low to start a conversion, the converter delays the actual start of conversion for 1182 to 1186 MCLK cycles, depending upon how CONV is controlled. The timing for the conversion sequence is shown in Figure 1 on page 6. After the 1182 - 1186 MCLK delay from when CONV goes low, the converter enters a higher-power state for 354 MCLK cycles and then returns to a lower-power state for 64 MCLK cycles, after which the RDY signal falls to indicate the completion of a conversion. Since the peak operating current for the converter occurs during the 354 MCLK, higher-power state, it is recommended that a large capacitor be used on the supply to the converter (as shown in Figures 9 and 10). This capacitor filters the peak current demand from the power supply. The average power consumption for the converter will depend upon the frequency of MCLK and the rate at which conversions are performed as illustrated in Figure 1 on page 6. Power Consumption (mW) 20 17.5 15 12.5 10 7.5 0 500 1k 1.5 2k 2.5k 3k 3.5k 4k 4.5k 5k Word Rate (Sps) MCLK = 4MHz MCLK = 8MHz Figure 6. Power Consumption vs. Conversion Rate DS806PP2 15 5/4/09 3.3 Clock CS5566 The CS5566 can be operated from its internal oscillator or from an external master clock. The state of MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and be used as the clock source for the converter. If an external CMOS-compatible clock is input into MCLK the converter will power down the internal oscillator and use the external clock. If the MCLK pin is held high, the internal oscillator will be held in the stopped state. The MCLK input can be held high to delete clock cycles to aid in operating multiple converters in different phase relationships. The internal oscillator can be used if the signals to be measured are essentially DC. The internal oscillator exhibits jitter at about 500 picoseconds rms. If the CS5566 is used to digitize AC signals, an external low-jitter clock source should be used. If the internal oscillator is used as the clock for the CS5566, the maximum conversion rate will be dictated by the oscillator frequency. If driven from an external MCLK source, the fast rise and fall times of the MCLK signal can result in clock coupling from the internal bond wire of the IC to the analog input. Adding a 50 ohm resistor on the external MCLK source significantly reduces this effect. 3.4 Voltage Reference The voltage reference for the CS5566 can range from 2.4 volts to 4.2 volts. A 4.096 volt reference is required to achieve the specified performance. Figure 8 and Figure 9 illustrate the connection of the voltage reference with either a single +5 V analog supply or with ±2.5 V. For optimum performance, the voltage reference device should be one that provides a capacitor connection to provide a means of noise filtering, or the output should include some type of bandwidth-limiting filter. Some 4.096 volt reference devices need only 5 volts total supply for operation and can be connected as shown in Figure 8 or Figure 9. The reference should have a local bypass capacitor and an appropriate output capacitor. Some older 4.096 voltage reference designs require more headroom and must operate from an input voltage of 5.5 to 6.5 volts. If this type of voltage reference is used ensure that when power is applied to the system, the voltage reference rise time is slower than the rise time of the V1+ and V1- power supply voltage to the converter. An example circuit to slow the output startup time of the reference is illustrated in Figure 7. 5.5 to 15 V 2k 10 μF VIN VOUT GND Refer to V1- and VREF1 pins. Figure 7. Voltage Reference Circuit 4.096 V 16 DS806PP2 5/4/09 CS5566 3.5 Analog Input The analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input. Therefore, the differential, peak-to-peak input is 8.192 volts. This is illustrated in Figure 8 and Figure 9. These diagrams also illustrate a differential buffer amplifier configuration for driving the CS5566. The capacitors at the outputs of the amplifiers provide a charge reservoir for the dynamic current from the A/D inputs while the resistors isolate the dynamic current from the amplifier. The amplifiers can be powered from higher supplies than those used by the A/D but precautions should be taken to ensure that the opamp output voltage remains within the power supply limits of the A/D, especially under start-up conditions. 3.6 Output Coding Format The reference voltage directly defines the input voltage range in both the unipolar and bipolar configurations. In the unipolar configuration (BP/UP low), the first code transition occurs 0.5 LSB above zero, and the final code transition occurs 1.5 LSBs below VREF. In the bipolar configuration (BP/UP high), the first code transition occurs 0.5 LSB above -VREF and the last transition occurs 1.5 LSBs below +VREF. See Table 1 for the output coding of the converter. Table 1. Output Coding, Two’s Complement Bipolar Input Voltage >(VREF-1.5 LSB) VREF-1.5 LSB 7F FF FE 00 00 00 -0.5 LSB FF FF FF 80 00 01 -VREF+0.5 LSB 80 00 00 (VREF-1.5 LSB) VREF-1.5 LSB FF FF FE 80 00 00 (VREF/2)-0.5 LSB 7F FF FF 00 00 01 +0.5 LSB 00 00 00