CS6420-CS

CS6420 Full-Duplex Speakerphone Chip Features General Description Most modern speakerphones use half-duplex operation, which switches transmission between the far-end talker and the speakerphone user. This is done because the acoustic coupling between the speaker and microphone is much higher in speakerphones than in handsets where the coupling is mechanically suppressed. The CS6420 enables full-duplex conversation with a single-chip solution. The CS6420 can easily replace existing half-duplex speakerphone ICs with a huge increase in conversation quality. The CS6420 consists of telephone & audio interfaces, two codecs and an echo-cancelling DSP. ORDERING INFORMATION CS6420-CS CDB6420 20-pin SOIC Evaluation Board l Single-chip full-duplex hands-free operation l Automatic gain control l Optional 34 dB microphone preamplifier l Integrated mute and volume control l Integrated 80 dB IDR dual codec l Speech-trained Network and Acoustic Echo Cancellers l Powerdown mode l Microcontroller Interface DGND NC4 NC3 NC2 NC1 Rx Suppression Half Duplex AGND Mute/Volume Control AVDD High Pass Filter NI 0,6,9.5,12 dB DAC ADC + - Σ RxAGC AO Pre-Emphasis Filter Network Echo Canceller Acoustic Echo Canceller - Pre-Emphasis Filter Clock Generation CLKI CLKO Mute/Volume Control Tx Suppression Half Duplex Hgih Pass Filter TxAGC DAC NO Σ ADC 1 kΩ 0,6,9.5,12 dB + 34 dB API 2.12 V BANDGAP 3.5 V Microcontroller Interface DVDD DATA STROBE DRDY RST AVDD APO MB Preliminary Product Information Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 1997 (All Rights Reserved) JUN ‘97 DS205PP2 1 CS6420 TABLE OF CONTENTS Absolute Maximum Ratings ..............................................................................................4 Recommended Operating Conditions..............................................................................4 Power Consumption ..........................................................................................................4 Analog Characteristics ........................................................................................................4 Analog Transmission Characteristics..............................................................................5 Microphone Amplifier ........................................................................................................5 Digital Characteristics .......................................................................................................5 Overview ............................................................................................................................8 Functional Description .....................................................................................................8 Analog Interface .......................................................................................................8 Acoustic Interface ..............................................................................................9 Network Interface ............................................................................................10 Microcontroller Interface .........................................................................................10 Description ......................................................................................................10 Register Definitions .........................................................................................11 Register 0..................................................................................................12 Mic - Microphone Preamplifier Enable ...............................................12 TSD - Transmit Suppression Disable.................................................12 GB - Graded Beta ..............................................................................12 ACC - Acoustic Coefficient Control ....................................................13 RVol - Receive Volume Control .........................................................13 TGain - Transmit Analog Gain ...........................................................13 Register 1..................................................................................................14 HD - Half-Duplex Disable...................................................................14 RSD - Receive Suppression Disable .................................................14 Taps - AEC/NEC Tap Allocation ........................................................15 NCC - Network Coefficient Control ....................................................15 TVol - Transmit Volume Control.........................................................15 RGain - Receive Analog Gain............................................................15 Register 2..................................................................................................16 NErle - Network ERLE Threshold ......................................................16 NFNse - Network Full-Duplex Noise Threshold .................................16 RHDet - Receive Half-Duplex Detection Threshold ...........................17 HDly - Half-Duplex Holdover Delay....................................................17 NseRmp - Background Noise Power Estimator Ramp Rate..............17 RSThd - Receive Suppression Threshold..........................................17 PCSen- Path Change Sensitivity .......................................................17 Register 3..................................................................................................18 AErle - Acoustic ERLE Threshold ......................................................18 AFNse - Acoustic Full-Duplex Noise Threshold.................................18 THDet - Transmit Half-Duplex Detection Threshold ..........................18 TSAtt - Transmit Suppression Attenuation.........................................19 TSBias - Transmit Suppression Bias .................................................19 TSThd - Transmit Suppression Threshold .........................................19 HHold - Hold in Half-Duplex on Howl.................................................19 Reset ...............................................................................................................19 Clocking ..................................................................................................................19 Power Supply .........................................................................................................20 Power Down Mode ..........................................................................................20 Noise and Grounding ......................................................................................21 Design Considerations ...................................................................................................22 Algorithmic Considerations .....................................................................................22 Full-Duplex Mode ............................................................................................22 Theory of Operation ..................................................................................22 Adaptive Filter ...........................................................................................23 Pre-Emphasis ....................................................................................23 Graded Beta.......................................................................................23 Update Control ..........................................................................................24 2 DS205PP2 CS6420 Speech Detection ..................................................................................... 24 Half-Duplex Mode ........................................................................................... 24 AGC ................................................................................................................ 25 Suppression .................................................................................................... 25 Transmit Suppression............................................................................... 26 Receive Suppression ................................................................................ 27 Circuit Design ......................................................................................................... 27 Interface Considerations ................................................................................. 27 Analog Interface........................................................................................ 27 Microcontroller Interface ........................................................................... 27 Grounding Considerations .............................................................................. 28 Layout Considerations .................................................................................... 28 System Design ....................................................................................................... 28 Gain Structure ................................................................................................. 28 Testing Issues ................................................................................................. 29 ERLE ........................................................................................................ 29 Convergence Time ................................................................................... 30 Half-Duplex Switching............................................................................... 30 Pin Descriptions .............................................................................................................. 31 Analog Interface .............................................................................................. 31 Microcontroller Interface ................................................................................. 32 Clock ............................................................................................................... 32 Power Supply .................................................................................................. 32 Miscellaneous ................................................................................................. 33 Glossary ........................................................................................................................... 34 Package Dimensions ...................................................................................................... 37 DS205PP2 3 CS6420 ABSOLUTE MAXIMUM RATINGS Parameter DC Supply (AVDD, DVDD) Input Current (Except supply pins) Input Voltage Ambient Operating Temperature Storage Temperature Analog Digital Iin Vina Vind TA Tstg Symbol Min -0.3 -10 -0.3 -0.3 -40 -65 Max 6.0 +10 AVDD+0.3 DVDD+0.3 85 150 Units V mA V °C °C WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS Parameter DC Supply (AVDD, DVDD) Ambient Operating Temperature TAOp Symbol Min 4.5 0 Typ 5.0 25 Max 5.5 70 Units V °C POWER CONSUMPTION (TA = 25°C, DVDD = AVDD = 5V, fXTAL = 20.480 MHz) (Note 1) Parameter Power Supply Current, Analog (RST=0) Power Supply Current, Analog (RST=1) Power Supply Current, Digital (RST=0) Power Supply Current, Digital (RST=1) Notes: 1. AO and NO outputs are not loaded. Symbol PDA0 PDA PDD0 PDD 50 10 Min Typ Max 1 20 1 60 Units mA mA mA mA ANALOG CHARACTERISTICS Parameter Input Offset Voltage (APO, NI) Output Offset Voltage (AO, NO) Transmit Group Delay Receive Group Delay Settling Time from RST rising MB Output Voltage MB Drive Capability Input Impedance (APO, NI) Load Impedance (AO, NO) Power Supply Rejection (1 kHz) (TA = 25°C, DVDD = AVDD = 5V, fXTAL = 20.480 MHz) Symbol Min Typ 2.12 2.12 (Note 2) (Note 2) 104 3.5 10 (Note 2) (Note 2) Zin Zload 10 40 300 6 6 Max Units V V ms ms ms V µA kΩ kΩ dB Notes: 2. These parameters are guaranteed by design or by characterization. 4 DS205PP2 CS6420 ANALOG TRANSMISSION CHARACTERISTICS (TA = 25°C, DVDD = AVDD = 5V, fXTAL = 20.480 MHz, RVol=TVol=RGain=TGain= 0 dB, HD=TSD=RSD=1, analog inputs and ouputs loaded with resistors and capacitors as shown in the typical connection diagram, Figure 2) Parameter Idle Channel Noise (Inputs grounded through a capacitor) Signal-to-Noise Ratio (Full Scale, 1 kHz sine wave input) Programmable Gain A-weighted (0-20 kHz) C-Message weighted (0-4 kHz) Psophometrically weighted (0-4 kHz) A-weighted (0-20 kHz) C-Message weighted (0-4 kHz) Psophometrically weighted (0-4 kHz) C-Message Weighted (0-4 kHz) RGain/TGain = 00 RGain/TGain = 01 RGain/TGain = 10 RGain/TGain = 11 0.9 SNR 69 17 -67 THD 0 6 9.5 12 3 1.0 1.0 1.1 -80 -85 0.1 Symbol Min Typ 17 -67 Max -69 Units dBV dBrnC0 dBm0p dB dBrnC0 dBm0p % dB Total Harmonic Distortion Volume Control Stepsize (TVol/RVol) ADC Full-scale Voltage Input DAC Full-scale Voltage Output ADC Noise Floor C-Message Weighted (0-4 kHz) DAC Noise Floor, DAC muted C-Message Weighted (0-4 kHz) dB Vrms Vrms dBV dBV MICROPHONE AMPLIFIER (TA = 25°C, DVDD = AVDD = 5V,fXTAL = 20.480 MHz) Parameter Gain (Zsource = 50Ω) Signal-to-Noise Ratio Input Impedance Input Offset Voltage A-weighted (0-20 kHz) Symbol Amic SNRm Zinm Voffm Min Typ 34 63 5 2.12 Max Units dB dB kΩ V DIGITAL CHARACTERISTICS (TA = 25°C, DVDD = AVDD = 5V,fXTAL = 20.480 MHz) Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Symbol VIH VIL Ileak CIN 5 Min DVDD-1.0 1.0 10 Typ Max Units V V µA pF DS205PP2 5 CS6420 SWITCHING CHARACTERISTICS Parameter Input rise time RST low time CLKI frequency CLKI duty cycle DRDY frequency STROBE frequency DRDY to STROBE setup time DATA to STROBE setup time STROBE to DATA hold time STROBE to DRDY hold time Symbol trise tRSTL fXTAL tLCLKI fDRDY fSTROBE tsDRDY tsDATA thDATA thDRDY 1.0 18.432 40 DC DC 30 30 30 30 20.480 50 22.528 60 fXTAL/ 2560 9.0 Min Typ Max 1.0 Units µs µs MHz % kHz MHz ns ns ns ns DRDY t sDRDY t hDRDY STROBE t sDATA t hDATA DATA Bit15 Bit14 Bit0 Figure 1. Microcontroller Interface Switching Characteristics 6 DS205PP2 CS6420 ferrite bead +5V Analog 0.1 µF 16 DVDD 15 DGND AVDD AGND MB 12.1 kΩ Telephone Line Out 3300 pF 0.47 µF Telephone Line In 1 0.1 µF + 2 19 1 µF + 1 µF +5V Analog 1.5 kΩ 0.1 µF +10 µF 4 NO APO 18 0.022 µF 10 kΩ 6.04 kΩ 3300 pF 17 NI API 20 0.47 µF 8 From Microprocessor 7 6 5 DATA STROBE AO 12.1 kΩ 3 3300pF DRDY RST NC4 NC3 NC2 NC1 12 11 10 9 CLKI CLKO 14 13 20.480 MHz 22pF 22pF Figure 2. Typical Connection Diagram (Microphone Preamplifier Enabled) ferrite bead +5V Analog 0.1 µ F 16 DVDD 15 DGND AVDD AGND API 12.1 kΩ Telephone Line Out 3300 pF 0.47 µF Telephone Line In 1 0.1 µF + 2 20 0.47 µF 1 µF 1 µF + 4 NO APO 18 6.04 kΩ 0.47 µF near-end input 3300 pF 6.04 k Ω 3300 pF 17 NI MB 19 0.1 µF +10 µF From Microprocessor 8 7 6 5 DATA STROBE DRDY RST NC4 NC3 NC2 NC1 12 11 10 AO 12.1 kΩ 3 3300pF CLKI CLKO 9 14 13 20.480 MHz 22pF 22pF Figure 3. Typical Connection Diagram (Microphone Preamplifier Disabled) DS205PP2 7 CS6420 OVERVIEW The CS6420 is a full-duplex speakerphone chip for use in hands-free communications with telephony quality audio. Common applications include speakerphones, inexpensive video-conferencing, and cellular phone car kits. The CS6420 requires very few external components and allows system control through a microcontroller interface. Hands-free communication through a microphone and speaker typically results in acoustic feedback or howling because the loop gain of the system exceeds unity by the time audio amplitudes are adjusted to a reasonable level. The solution to the howling problem has typically been half-duplex, where either the transmit or the receive channel is active, never both at the same time. This prevents the howling, but diminishes the overall communication quality by clipping words and forcing the talker at each end to wait for the talker at the other end to stop speaking. Full-duplex conversation, where both transmit and receive channels are active simultaneously, is the conversation quality we enjoy when using handsets. Full-duplex for hands-free communications is achieved in the CS6420 using a digital signal processing technique called “Echo Cancellation.” The end result is a more natural conversation than halfduplex, with no awkward breaks and pauses, as if both parties were speaking to each other directly. Echo Cancellation reduces overall loop gain and the acoustic coupling between speaker and microphone. This coupling reduction prevents the annoying effect of hearing one’s own delayed speech, the effect being worse when there is delay in the system, such as vocoder delay in digital cellular phones. The CS6420 is a complete system implementation of a Digital Signal Processor with RAM and program ROM, running Echo Cancellation algorithms developed at Crystal Semiconductor using customer input, integrated with two delta-sigma codecs. 8 The CS6420 is intended to provide a full-duplex speakerphone solution with a minimum of design effort while displacing existing half-duplex speakerphone chips. FUNCTIONAL DESCRIPTION The CS6420 is roughly divided into four external interface blocks. The analog interfaces connect the chip to the transmit and receive paths. Certain control functions are accessible through the microcontroller interface. Two pins accommodate either a crystal or an externally applied digital clock signal. Analog and digital power and ground are provided through four pins. Analog Interface In a speakerphone application, one input of the CS6420 connects to the signal from the microphone, sometimes called the near-end input or transmit input, and one output connects to the speaker. The output that leads to the speaker is sometimes called the near-end output or receive output. Together, the input and output that connect to the microphone and speaker are referred to as the Acoustic Interface. The signal received at the near-end input is then passed to the far-end output or transmit output after acoustic echo cancellation. This signal is sent to the telephone line. The signal from the telephone line is received at the far-end input, also called the receive input, and this signal is passed to the receive output after network echo cancellation. Together, the far-end input and output form the Network Interface. The analog interfaces are physically implemented using delta sigma converters running at an output word rate of 8 kHz, resulting in a passband from DC to 4 kHz. Because the inputs are analog to digital converters (ADCs), certain design considerations must be kept in mind: specifically, antialiasing and full-scale input voltage. The ADCs expect a single-pole RC filter with a corner at 8 kHz, DS205PP2 CS6420 NI PGA 17 0,6,9.5,12 dB NO DAC 4 0,6,9.5,12 dB D S P ADC DAC AO 3 API ADC PGA 1kΩ 2.12V BANDGAP 3.5V 18 APO 19 MB 34 dB 20 Receive Path FAR-END NEAR-END Transmit Path Figure 4. Analog Interface and they are post-compensated internally to prevent any resultant passband droop. The ADCs also expect a maximum of 1 Vrms (2.8 Vpp) at their inputs (which are biased around 2.12 VDC). A signal of higher amplitude will clip the ADC input and may result in poor echo canceller performance. See the Design Considerations section for more details. The outputs are delta-sigma digital to analog converters (DACs) and have similar requirements to the ADCs. The DACs are pre-compensated to expect a single-pole RC filter with a corner frequency at 4 kHz. The full scale voltage output from a DAC is 1 Vrms (2.8 Vpp) swinging around a DC bias of 2.12 V. Acoustic Interface The pins API (pin 20), APO (pin 18), MB (pin 19), and AO (pin 3) make up the Acoustic Interface. A block diagram of the Acoustic Interface is shown in Figure 4. API and APO are, respectively, the input and output of the built-in analog pre-amplifier. The preamplifier is an inverting amplifier with a fixed gain of 34 dB biased around an input offset voltage (Voff) of 2.12 V. APO is the output of the pre-amplifier after a 1 kΩ resistor. The circuitry connected to the amplifier input must present low source impedance (