CTSLV353QG

CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 FEATURES BLOCK DIAGRAM LVPECL Outputs Optimized for Very Low Phase Noise (-165dBc/Hz)  Up to 800MHz Bandwidth  Selectable ÷1, ÷2 Output  Selectable Enable Logic  3.0V to 3.6V Operation  RoHS Compliant Pb Free Packages  DESCRIPTION The CTSLV353 is a sine wave/CMOS to LVPECL buffer/translator optimized for very low phase noise (165dBc/Hz). It is particularly useful in converting crystal or SAW based oscillators into LVPECL outputs for up 800MHz of bandwidth. For greater bandwidth, refer to the CTSLV363. The CTSLV353 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as active high enable or active low enable to oscillator designers. Refer to Table 1 for the comparison of parts within the CTSLV35x and CTSLV363 family. ENGINEERING NOTES Functionality Table 1 details the differences between the family parts to assist designers in selecting the optimal part for their design. Table 2 lists the specific CTSLV353 functional operation. Figure 1 plots the S-parameters of the D input. Table 1 Part Number Divide Ratio EN Logic EN Pull-Up / Pull-Down Bandwidth CTSLV351 ÷1 active HIGH Pull-up > 800MHz CTSLV353 Selectable ÷1 or ÷2 selectable selectable > 800MHz CTSLV363 Selectable ÷1 or ÷2 selectable selectable ≥ 1GHz North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 1 Rev B0215 CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 Table 2 - CTSLV353 Functional Operation, ÷1 mode Part Number EN_SEL High, NC Inputs EN Low, NC High CTSLV353 Low High, NC Low Outputs `Q D Q Low Low High High High Low X Z Z Low Low High High High Low X Z Z DIV_SEL Divide Ratio Low, NC ÷1 High ÷2 Figure 1 - S11, Parameters, D Input North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 2 Rev B0215 CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 Input Termination The D input bias is VDD/2 fed through an internal 10k resistor. For clock applications, an input signal of at least 750mVPP ensures the CTSLV353 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation. Figure 2 - Input Termination Output Termination Techniques The LVPECL compatible output stage of the CTSLV353 uses a current drive topology to maximize switching speed as illustrated below in Figure 3. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the output pin. The associated output voltage swings match LVPECL levels when external 50 resistors terminate the outputs. Both Q and Q ¯ should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. This rule should be followed even if only one output is in use. VDD (+3.3 V) Output Stage Vbp External Circuitry M2 M1 21.1mA 21.1mA Q Q M4 M3 D Vbn M5 16mA 21.1mA - High 5.1mA - Low 50Ω 50Ω VTT = VDD - 2.0V Figure 3 - Typical Output Termination North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 3 Rev B0215 CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 Dual Supply LVPECL Output Termination The standard LVPECL loads are a pair of 50 resistors connected between the outputs and VDD-2.0V (Figure 3). The resistors provide both the DC and the AC loads, assuming 50 interconnect. If an additional supply is available within the application, a four resistor termination configuration is possible (Figure 4). Figure 4 - Dual Supply Output Termination Three Resistor Termination Another termination variant eliminates the need for the additional supply (Figure 5). Alternately three resistors and one capacitor accomplish the same termination and reduce power consumption. Figure 5 - Three Resistor Termination North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 4 Rev B0215 CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 Evaluation Board (EBP53) CTS’s evaluation board, EBP53, provides the most convenient way to test and prototype CTSLV353 series circuits. Built for the CTSLV353QG 1.5x1.0mm package, it is designed to support both dual and single supply operation. Dual supply operation (VDD=+2.0V, VSS=-1.3V) enables direct coupling to 50 time domain test equipment (Figure 6). Figure 6 - Split Supply LVPECL Output Termination AC Termination Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. Figure 7 below shows the AC coupling technique. The 200 resistors form the required DC loads, and the 50 resistors provide the AC termination. The parallel combination of the 200 and 50 resistors results in a net 40 AC load termination. In many cases this will work well. If necessary, the 50 resistors can be increased to about 56. Alternately, bias tees combined with current setting resistors will eliminate the lowered AC load impedance. The 50 resistors are typically connected to ground but can be connected to the bias level needed by the succeeding stage. Figure 7 - AC Termination North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 5 Rev B0215 CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol Characteristic Rating Unit VDD Power Supply 0 to +5.5 V VI Input Voltage -0.5 to VDD + 0.5 V TA Operating Temperature Range -40 to +85 °C TSTG Storage Temperature Range -65 to +150 °C ESDHBM Human Body Model 2500 V ESDMM Machine Model 200 V ESDCDM Charged Device Model 2500 V DC Characteristics DC Characteristics (VDD = 3.0V to 3.6V unless otherwise specified, TA = -40°C to +85°C) Symbol Characteristic Conditions VOH Output HIGH Voltage1 -40°C VOL Output LOW Voltage 1 2.415 2.48 +85°C 2.05 2.54 -40°C 1.365 1.615 1.43 1.68 1.49 1.74 -10 10 +25°C VDD = 3.3V Output Leakage Current, Tri-state2 VIH High Level Input Voltage VIL Low Level Input Voltage EN IPU Pull-up Current EN_SEL IPD Pull-down Current IP Pull-up / Pull-down Current RBIAS Bias Resistor IDD Power Supply Current 1 Outputs Tri-state Max 2.05 VDD = 3.3V IZ Power Supply Current – Typ 2.05 +25°C +85°C IDDZ Min EN=Disable EN_SEL DIV_SEL 2 Unit V V μA V 0.8 V 2.2 μA DIV_SEL -2.2 μA EN ±2.2 μA D Input to Internal VDD/2 Reference 10k Ω 22 D Input ≤ VIL EN=Disable 1 Specified with outputs terminated through 50Ω resistors to VDD -2V or Thevenin equivalent. 2 Measured at Q / Q pins. 35 mA 8 mA North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 6 Rev B0215 CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 AC Characteristics AC Characteristics (VDD = 3.0V to 3.6V, TA = -40°C to +85°C) AC Specifications guaranteed by design Symbol Max Unit 250 ps ÷1 800 MHz ÷2 1300 VINMAX Maximum Recommended Input Signal VDD VINMIN Minimum Recommended Input Signal 0.2 tPLH Propagation Delay 938 1614 ps tPHL Propagation Delay RMS Jitter: 12kHz - 20MHz, 155MHz Center Freq Phase Noise1, 2 - 1MHz offset 938 1614 ps tr / tf Characteristic Output Rise/Fall Min Typ 1, 2 (20% - 80%) 80 Maximum Input Frequency - Sine wave2 fMAX jRMS nP 1 2 VPP VPP 36 fs -165 dBc/Hz Specified with outputs terminated through 50W resistors to VCC -2V or Thevenin equivalent. 1.5 VP-P sine wave input, AC coupled to D pin. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 7 Rev B0215 CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 Pin Description and Configuration Pin Assignments Pin Name Type Function 1 Q Output LVPECL Output 2 Q Output LVPECL Output 3 EN Input Enable 4 GND Power Negative Supply 5 D Input Sine or CMOS Input 6 EN_SEL Input Enable Select 7 DIV_SEL Input Divide Select 8 VDD Power Positive Supply SON8 Pin Configuration QFN8 Pin Configuration PART ORDERING INFORMATION Part Number Package Marking CTSLV353QG QFN8 D3 / YW CTSLV353PG SON8 D YW North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 8 Rev B0215 CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 PACKAGE DIMENSIONS North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 9 Rev B0215 CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 10 Rev B0215