CTSLV310TG

CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 FEATURES BLOCK DIAGRAM 2.5V-3.3V Operation Ultra-Low Phase Noise Floor o LVPECL -167dBc/Hz o LVDS -165dBc/Hz  Configurable o LVPECL or LVDS Output o ÷1 or ÷2 o Enable Active High or Low  1GHz+ Bandwidth  RoHS Compliant Pb Free Packages   DESCRIPTION  The CTSLV310 is a configurable LVPECL, LVDS buffer & translator IC that is optimized for ultra-low phase noise and 2.5V-3.3V nominal supply voltage. It is particularly useful in converting crystal or SAW based oscillators into LVPECL and LVDS outputs for up to 1GHz of bandwidth. For a design that includes gain in the signal path, refer to the CTSLV315.  A configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active high or active low enable selection. See Table 1 for details of the configurations options that provide designers with a single IC buffer/translator solution that is extremely compact, flexible and high performance.  8 configurations which are determined by the static voltage levels of b-0 and b-1. Table 1 details the configurations. Table 1 - Possible IC Configuration Configuration Bits b-0 Open Open Open Low Low Low High High High b-1 Open Low High Open Low High Open Low High Functional Configuration Output Type LVPECL LVPECL LVPECL LVPECL LVDS LVDS LVDS LVDS Not Used Enable Polarity Active High Active High Active Low Active Low Active High Active High Active Low Active Low Not Used Division ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 Not Used North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 1 RevA0215 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 Input Termination The D input bias is VDD/2 fed through an internal 10k resistor. For clock applications, an input signal of at least 750m VPP ensures the CTSLV10 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation. LVPECL Output Termination Techniques DC Coupling The LVPECL compatible output stage of the CTSLV310 uses a current drive topology to maximize switching speed as illustrated below. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the output pin. The associated output voltage swings match LVPECL levels when external 50 resistors terminate the outputs. Both Q and QN should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. This rule should be followed even if only one output is in use. VDD Output Stage Vbp External Circuitry M2 M1 21.1mA 21.1mA Q QN M4 M3 D Vbn M5 21.1mA - High 5.1mA - Low 16mA 50Ω 50Ω VTT = VDD - 2.0V Typical Output Termination North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 2 RevA0215 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 AC Coupling Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. The illustration below shows the AC coupling technique. The 200 resistors form the required DC loads, and the 50 resistors provide the AC termination. The parallel combination of the 200 and 50 resistors results in a net 40 AC load termination. In many cases this will work well. If necessary, the 50 resistors can be increased to about 56. Alternately, bias tees combined with current setting resistors will eliminate the lowered AC load impedance. The 50 resistors are typically connected to ground but can be connected to the bias level needed by the succeeding stage. VDD Output Stage Vbp 21.1mA 21.1mA M4 M3 D Vbn External Circuitry M2 M1 M5 Q 0.01µF QN 0.01µF 21.1mA - High 5.1mA - Low 200Ω 200Ω 50Ω 50Ω GND or VT 16mA AC Termination LVDS Output Termination Technique The following LVDS termination is compliant to the LVDS specification TIA/EIA-644A. LVDS Termination North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 3 RevA0215 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 ELECTRICAL SPECIFICATIONS Absolute Maximum Rating Symbol Characteristic VDD Supply Voltage VABSOLUTE Absolute Max Power Supply TOP TSTORAGE VI_MAX Ib0,b1 Vtb0,b1 IEN VtEN ESD Conditions b-0, b-1 Input High Current b-0, b-1 Input Low Current b-0, b-1 Input High Voltage Threshold b-0, b-1 Input Low Voltage Threshold EN Input Current EN Input High Voltage Threshold EN Input Low Voltage Threshold ESD Ratings Typ 2.5 3.3 Continuous t ≤ 1s Operating Temperature Range Storage Temperature Range Maximum Input Voltages Min 2.375 D EN b0 b1 b-0, b-1 = VDD b-0, b-1 = GND Human Body Model Machine Model Charged Device Model Max 3.6 3.6 5.5 Unit V V -40 85 °C -65 -0.5 -0.5 -0.5 -0.5 150 VDD +0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5 11 °C -11 VDD -0.5 VDD 0 0.5 -4 3 VDD -0.5 VDD 0 0.5 2000 200 V uA V uA V V 2000 North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 4 RevA0215 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 LVPECL Performance Specifications Symbol Characteristic Conditions Min fMAX Max Input Frequency ÷1 mode ÷2 mode 1000 1600 RL RBIAS Output Loading Input Bias Resistor VIN_SWING Input Voltage Swing VOUT Voltage Output Levels D input to VDD/2 ref minimum1 recommended1 VDD = 2.5V, HIGH VDD = 2.5V, LOW VDD = 3.3V, HIGH VDD = 3.3V, LOW Output Rise/Fall Time Phase Noise Floor Integrated Jitter: 12kHz-20MHz Enable Time2 Disable Time2 Propagation Delay3 JINTEG TENABLE TDISABLE TPROP Power Supply Current 1 2 3 4 5 Ω Ω 5.47 0.74 0.93 3.49 5.47 80%-20% 1MHz Offset 100 -167 205 155MHz Carrier 26 VPP 15 0.5 2.2 0.9 EN = active EN = disabled5 V V V V VPP, Q/QN dBm, Q/QN VPP, Q/QN dBm, Q/QN ps dBc/Hz ƒs EN = active EN = disabled 4 IDD 50 10k 0.75 VDD = 3.3V Unit MHz VDD -0.88 VDD -1.66 VDD -0.88 VDD -1.75 0.93 Differential Output Voltage tR / tF PN Max 0.2 0.6 VDD -1.25 VDD -1.86 VDD -1.15 VDD -1.86 0.54 VDD = 2.5V VOD Typ 28.5 5 us us ns mA Phase noise floor performance is dependent upon input voltage swing. Voltage swing values below recommended values may result in degraded phase noise values. Into and out of tri-state condition. Time from D crossing VDD/2 to Q=QN. VDD =3.3V, FIN @ 200MHz. D = 0V. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 5 RevA0215 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 LVDS Performance Specifications Symbol Characteristic Conditions Min fMAX Max Input Frequency ÷1 mode ÷2 mode 1000 1600 RL RBIAS Output Loading Input Bias Resistor VIN_SWING Input Voltage Swing VOUT Voltage Output Levels VOD D input to VDD/2 ref minimum1 recommended1 VDD = 2.5V VDD = 3.3V Differential Output Voltage Common Mode Output Voltage Delta in Common Mode Output Voltage2 Peak-to-Peak Common Mode Output Voltage VOC ∆VOC VOC,PP tR / tF PN Output Rise/Fall Time Phase Noise Floor Integrated Jitter: 12kHz - 20MHz Enable Time3 Disable Time3 Propagation Delay4 JINTEG TENABLE TDISABLE TPROP Power Supply Current 1 2 3 4 5 6 Unit MHz Ω Ω 0.2 0.6 290 290 -50 454 454 50 mV 1.125 1.375 V -50 50 mV 100 mV 220 ps dBc/Hz 120 -165 155MHz Carrier 36 VPP mV ƒs EN = active EN = disabled 4 0.5 1.7 0.8 EN = active EN = disabled6 Max 100 10k 80%-20% 1MHz Offset 5 IDD Typ 12.9 5 us us ns mA Phase noise floor performance is dependent upon input voltage swing. Voltage swing values below recommended values may result in degraded phase noise values. Between logics states. Into and out of tri-state condition. Time from D crossing VDD/2 to Q=QN. VDD =3.3V, Fin @ 200MHz. D = 0V. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 6 RevA0215 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 Pin Description and Configuration Pin Assignments Pin Name I/O/P Function Properties 1 2 3 4 5 6 7 8 EN Q QN GND D B0 B1 VDD I O O P I I I P Enable Output Signal Output Signal Negative Supply Input Signal Configuration Bit Configuration Bit Positive Supply Configurable functionality Configurable (LVPECL, LVDS) Configurable (LVPECL, LVDS) 0V SON8 Tertiary Levels Tertiary Levels 2.375V - 3.6V MSOP8 PART ORDERING INFORMATION Part Number Package Marking CTSLV310QG SON8 SYW CTSLV310TG MSOP8 BE0G / YYWW North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 7 RevA0215 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 PACKAGE DIMENSIONS North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 8 RevA0215 CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 9 RevA0215