CTSLV394NG

CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8 FEATURES          BLOCK DIAGRAM Selectable Divide Ratio Selectable Enable Priority and Threshold (CMOS or PECL) Tristate Compatible Outputs Input Buffer Powers Down when Disabled High BW [1.5GHz (÷1), 3.0GHz (÷2)] 3V to 5.5V Power Supply -145dBc/Hz (÷1) Typ Noise Floor -151dBc/Hz (÷2) Typ Noise Floor RoHS Compliant Pb Free Packages DESCRIPTION The CTSLV394 is a ÷1 or ÷2 clock generation part specifically designed to accommodate Colpitts or Pierce based oscillators. The tri-state compatible outputs allow for on-the-fly switching of multiple oscillators on a common bus. Other features are incorporated to reduce board components. A voltage reference and input biasing allows for easy oscillator interface. The CTSLV394 provides a ÷ 2 mode of operation for more frequency options and is selectable with a single connection. A selectable enable is also provided which doubles as a reset when the CTSLV394 is in ÷2 mode. With a single connection, the enable can be selected to operate as active high or active low. ENGINEERING NOTES The CTSLV394 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the CTSLV394 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider. Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20k ± 20% resistor. Leaving EN-SEL open or connecting it to VEE allows the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75k pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75k pull-down resistor is selected which disables the outputs whenever EN is left open. Connecting the EN-SEL to VEE with a 20k resistor will allow the EN pin/pad to function as an active low PECL/ECL enable with an internal 75k pull-down resistor. In this mode, outputs are enabled when EN is left open (NC). The default logic condition can be overridden by connecting the EN to VCC with an external resistor of 20k. If the enable signal is CMOS (rail-to-rail) and the logic sense is active low (EN-SEL connected to VEE with a 20k resistor), the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for details. When the CTSLV394 is disabled, the Q and Q ¯ outputs are forced LOW and the input buffer is powered down to minimize feed through. This feature allows tri-state compatible parallel output connections. Multiple CTSLV394 chip outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled CTSLV394 can drive the output lines without interference from the unselected units. In addition, the CTSLV394 can be used in parallel connection with PECL/ECL parts whose outputs are high impedance when disabled. The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when the outputs are disabled. The CTSLV394 provides a VBB with an 1880 internal bias resistor from D to VBB. This feature allows AC coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be bypassed to ground or VCC with a 0.01 F capacitor. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice 1 RevA1113 CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol Characteristic Condition Rating Unit VCC PECL Power Supply VEE = 0V 0 to + 6.0 V VI_PECL PECL Input Voltage VEE = 0V 0 to + 6.0 V VEE ECL Power Supply VCC = 0V -6.0 to 0 V VI_ECL ECL Input Supply VCC = 0V -6.0 to 0 V IHGOUT Output Current Continuous 50 Surge 100 Operating Temperature Range - -40 to +85 °C Storage Temperature Range - -65 to +150 °C ESDHBM Human Body Model Electro Static Discharge - 2500 V ESDMM Machine Model Electro Static Discharge - 200 V ESDCDM Charged Device Model Electro Static Discharge - 2000 V TA TSTG mA 100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND) Symbol Characteristic VOH VOL -40°C VIL Unit Min Max Min Max Min Max Output HIGH Voltage1 -1085 -880 -1025 -880 -1025 -880 -1025 -880 mV 1 -1900 -1555 -1900 -1620 -1900 -1620 -1900 -1620 mV -1165 -740 -1165 -740 -1165 -740 -1165 -740 mV VEE +2000 VCC VEE +2000 VCC VEE +2000 VCC VEE +2000 VCC mV -1900 -1475 -1900 -1475 -1900 -1475 -1900 -1475 mV VEE VEE +800 VEE VEE +800 VEE VEE +800 VEE VEE +800 mV -1390 -1250 -1390 -1250 -1390 -1250 -1390 -1250 mV 150 µA Reference Voltage IIH Input HIGH Current EN Input LOW Current EN (ECL)2 Input LOW Current EN (CMOS)3 Power Supply Current1 IEE 85°C Max VBB IIL 25°C Min Output LOW Voltage Input HIGH Voltage D,EN (ECL)2 Input HIGH Voltage EN (CMOS)3 Input LOW Voltage D,EN (ECL)2 Input LOW Voltage EN (CMOS)3 VIH 0°C 150 150 150 0.5 0.5 0.5 0.5 -150 -150 -150 -150 34 34 1 Specified with each output terminated through 50Ω resistors to VCC -2V. 2 EN-SEL connected to VEE through a 20kΩ resistor. 3 EN-SEL connected to VEE or left open (NC). 34 µA 37 mA North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice 2 RevA1113 CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8 100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) Output HIGH Voltage1,2 -40°C Min Max 2215 2420 0°C Min Max 2275 2420 25°C Min Max 2275 2420 85°C Min Max 2275 2420 Output LOW Voltage1,2 1400 1745 1400 1680 1400 1680 1400 1680 mV 3 2135 2560 2135 2560 2135 2560 2135 2560 mV 4 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV 3 1400 1825 1400 1825 1400 1825 1400 1825 mV Symbol Characteristic VOH VOL Input HIGH Voltage D,EN (ECL) VIH Input HIGH Voltage EN (CMOS) Input LOW Voltage D,EN (ECL) VIL Input LOW Voltage EN (CMOS) 4 Reference Voltage1 Input HIGH Current EN Input LOW Current EN (ECL)3 VBB IIH IIL Input LOW Current EN (CMOS) Power Supply Current2 IEE 1 2 3 4 mV GND 800 GND 800 GND 800 GND 800 mV 1910 2050 150 1910 2050 150 1910 2050 150 1910 2050 150 mV µA µA 37 mA 0.5 4 Unit 0.5 -150 0.5 -150 34 0.5 -150 34 -150 34 For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value. Specified with each output terminated through 50Ω resistors to VCC -2V. EN-SEL connected to VEE through a 20kΩ resistor. EN-SEL connected to VEE or left open (NC). 100K PECL DC Characteristics (VEE = GND, VCC = +5.0V) Symbol Characteristic VOH VOL Output HIGH Voltage1,2 Output LOW Voltage1,2 Input HIGH Voltage D,EN (ECL)3 Input HIGH Voltage EN (CMOS)4 Input LOW Voltage D,EN (ECL)3 Input LOW Voltage EN (CMOS)4 Reference Voltage1 Input HIGH Current EN Input LOW Current EN (ECL)3 Input LOW Current EN (CMOS)4 Power Supply Current2 VIH VIL VBB IIH IIL IEE 1 2 3 4 -40°C Min Max 3915 4120 3100 3445 3835 4260 2000 VCC 3100 3525 GND 800 3610 3750 150 0.5 -150 34 0°C Min Max 3975 4120 3100 3380 3835 4260 2000 VCC 3100 3525 GND 800 3610 3750 150 0.5 -150 34 25°C Min Max 3975 4120 3100 3380 3835 4260 2000 VCC 3100 3525 GND 800 3610 3750 150 0.5 -150 34 85°C Min Max 3975 4120 3100 3380 3835 4260 2000 VCC 3100 3525 GND 800 3610 3750 150 0.5 -150 37 Unit mV mV mV mV mV mV mV µA µA mA For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value. Specified with each output terminated through 50Ω resistors to VCC -2V. EN-SEL connected to VEE through a 20kΩ resistor. EN-SEL connected to VEE or left open (NC). North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice 3 RevA1113 CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8 AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V) Symbol Characteristic -40°C Min 0°C Typ Max D to Q/Q ¯1 tPLH/tPHL VPP (AC) EN to QHG/QbHG1,2 Duty Cycle Skew3 Input Swing4 tR/tF Output Rise/Fall1 (20% - 80%) tSKEW 1 2 Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit 450 450 450 450 ps 3000 3000 3000 3000 ps 20 ps 5 20 5 20 5 20 5 150 1000 150 1000 150 1000 150 1000 mV 100 240 100 240 100 240 100 240 ps Specified with each output terminated through 50Ω resistors to VCC -2V. Specified from 50% EN input edge to VOH min to VOL max of the Q/Q ¯ outputs. 3 Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 4 VPP is the peak-to-peak differential input swing for which AC parameters are guaranteed. Tri-state Compatible Operation The outputs of the CTSLV394 are emitter followers as shown in the left side of Figure 1. When a part is disabled, both outputs are set in the LOW state. This allows a HIGH output from an enabled part to override a disabled output and pull the combined line HIGH as seen in the right hand side of Figure 1. When the enabled part output is LOW, the combined line remains LOW. If all connected CTS94 parts are disabled, both output lines will be in the LOW state. As another feature, while disabled, the input buffer is powered down to minimize feed through. CTSLV394 Transistor Output Stage Figure 1: Typical Tri-state Operation North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice 4 RevA1113 CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8 Divide Truth Table 1 DIV-SEL ÷Ratio NC ÷1 VEE1 ÷2 DIV-SEL connection must be ≤1W. Enable Truth Table EN-SEL NC VEE 20kΩ to VEE EN Q Q ¯ CMOS Low or VEE Low Low CMOS High, VCC or NC Data Data CMOS Low, VEE or NC Low Low CMOS High or VCC Data Data PECL Low, VEE or NC Low Low PECL High or VCC Data Data Figure 2 illustrates the timing sequences for the CTSLV394 in the ÷1 mode which is determined by leaving the DIV-SEL open (NC). It also illustrates the enable in the active High mode being controlled by a CMOS signal. This mode is determined by leaving the EN-SEL open (NC). Figure 2 Figure 3 illustrates the timing sequences for the CTSLV394 in the ÷2 mode which is determined by connecting the DIV-SEL to VEE. It also illustrates the enable in the active Low mode being controlled by a PECL signal. This mode is determined by connecting the EN-SEL to VEE via 20kΩ resistor. Figure 3 North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice 5 RevA1113 CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8 VOUTPP (mV) ÷2 ÷1 Input Frequency (MHz) Typical Large Signal Output Swing Measured with 750mV D input, Q/Q ¯ each terminated to VCC-2V via 50Ω resistors. Pin Description and Configuration Pin Assignments Pin Name Type Function 1 EN-SEL Input Enable Polarity Select 2 D Input Data Input 3 VBB Input Reference Voltage 4 EN Input Output Enable 5 DIV-SEL Input Divide Select 6 Q ¯ Output Inverted PECL Output 7 Q Output PECL Output 8 VCC Power Positive Supply 9 VEE Power Negative Supply PART ORDERING INFORMATION Part Number Package Marking CTSLV394NG MLP8 J4G / YWW North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice 6 RevA1113