CTSLV399TG

CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable Not recommended for new designs MLP8, MSOP8 FEATURES     BLOCK DIAGRAM Minimizes External Components Selectable Enable Polarity and Threshold (CMOS or PECL) 3V to 5.5V Power Supply Similar Operation as CTS100LVEL16VT Except with LVDS Outputs DESCRIPTION The CTSLV399 is a specialized oscillator gain stage with an LVDS output buffer including an enable. The selectable enable input allows continuous oscillator operation by only controlling the QHG /Q ¯ HG outputs. The CTSLV399 provides adjustable internal pull-down current sources for the Q/Q ¯ outputs. Internal input biasing further reduces the number of needed external components ENGINEERING NOTES The CTSLV399 is a specialized oscillator gain stage with LVDS output buffer including an enable. The enable input (EN) allows continuous oscillator operation by only controlling the QHG /Q ¯ HG outputs. The CTSLV399 also provides a VBB and 470 internal bias resistors from D to VBB and D ¯ to VBB. The VBB pin can support 1.5 mA sink/source current. Bypassing VBB to ground with a 0.01 F capacitor is recommended. Functionality MLP8 Package (CTSLV399NG) The MLP8, NG options of the CTSLV399, provide a PECL/ECL level enable input (¯¯¯). EN When the ¯¯¯ EN input is LOW, the Q ¯ and QHG/Q ¯ HG outputs pass data from the inputs. When ¯¯¯ EN is HIGH, the Q ¯ output continues to pass data while the QHG output is forced high and the Q ¯ HG output is forced low. Only the Q ¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current source). The CTSLV399NB and CTSLV399ND versions operate with a single ended data input (D). The D ¯ input is internally bonded directly to the VBB pin bypassing the 470 bias resistor. Functionality MLP8 Package (CTSLV399N) & MSOP8 Package (CTSLV399T) The MSOP8 (T) and MLP8 (N) versions of the CTSLV399 provide a CMOS/TTL level enable input (EN). When the EN input is HIGH, the Q ¯ and QHG/Q ¯ HG outputs pass data from the inputs. When EN is LOW, the ¯ HG output is forced low. Q ¯ output continues to pass data while the QHG output is forced high and the Q Only the Q ¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current source). The MSOP8 (T) and MLP8 (N) CTSLV399 operates with a single ended data input (D). The D ¯ input is internally bonded directly to the VBB pin bypassing the 470 bias resistor. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 1 RevA0215 CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable Not recommended for new designs MLP8, MSOP8 Enable Truth Table EN-SEL NC VEE1 EN/ EN Q/Q ¯ QHG Q ¯ HG PECL Low, VEE or NC Data Data Data PECL High or VCC Data High Low CMOS/TTL Low, VEE or NC Data High Low CMOS/TTL High or VCC2 Data Data Data 1 EN-SEL connections must be less than 1Ω. 2 An external ≤ 20kΩ pull-up resistor between EN and VCC ensures a High when the EN pin is not driven. Timing Diagram Current Source Truth Table CS-SEL Q Q ¯ NC 4mA typ 4mA typ VEE1 8mA typ 8mA typ 0 4mA typ VCC 1 1 Connection must be less than 1Ω. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 2 RevA0215 CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MSOP8 Not recommended for new designs Application Circuit for CMOS inputs Recommended Component Values for CMOS Single Ended Inputs R11 Value Input Type AC Coupled (C2 in DC Coupled (C2 circuit) shorted) 3.3 V CMOS 1.1 kΩ 2.0 kΩ 5.0 V CMOS 1.6 kΩ 3.3 kΩ R1 should be chosen so that the input swing on the D input with respect to D ¯ is in the range of ±80 to ±1000 mV, per the AC Characteristics table and the D input is < ±750 mV with respect to VBB. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 3 RevA0215 CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MSOP8 Not recommended for new designs S11, 50Ω AC load S12, 50Ω AC load North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 4 RevA0215 CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MSOP8 Not recommended for new designs S21, 50Ω AC load S22, 50Ω AC load North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 5 RevA0215 CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable Not recommended for new designs MLP8, MSOP8 Electrical Specifications Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol Characteristic Condition Rating Unit VCC PECL Power Supply VEE = 0V 0 to + 6.0 V VI PECL Input Voltage 0 to + 6.0 V VD/ D/D ¯ Input Voltage VEE = 0V Referenced to VBB Continuous Q/Q ¯ ±0.75 V Surge Q/Q ¯ 50 Continuous QHG/Q ¯ HG 5 Surge QHG/Q ¯ HG 10 IOUT Output Current 25 mA TA Operating Temperature Range - -40 to +85 °C TSTG Storage Temperature Range - -65 to +150 °C ESDHBM Human Body Model Electro Static Discharge - 2500 V ESDMM Machine Model Electro Static Discharge - 200 V ESDCDM Charged Device Model Electro Static Discharge - 2000 V 100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) Symbol Characteristic VOH VOL VIL VBB IIH 85°C Unit Min Max Min Max Min Max Output HIGH Voltage1,2 2255 2465 2275 2465 2275 2465 2275 2465 mV 1,2 1375 1745 1400 1680 1400 1680 1400 1680 mV Input HIGH Voltage D,EN (EN-SEL open)1 2135 2560 2135 2560 2135 2560 2135 2560 mV Input HIGH Voltage EN (EN-SEL tied to VEE)1 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV Input LOW Voltage D,EN (EN-SEL open)1 1400 1825 1400 1825 1400 1825 1400 1825 mV Input LOW Voltage EN (EN-SEL tied to VEE)1 GND 800 GND 800 GND 800 GND 800 mV Reference Voltage1 1910 2050 1910 2050 1910 2050 1910 2050 mV 150 µA Input LOW Current EN 3 3 2 IEE 25°C Max Input HIGH Current EN IIL 0°C Min Output LOW Voltage VIH -40°C Power Supply Current 1 Voltage levels vary 1:1 with VCC. 2 Specified with CS-SEL open. 3 Specified with EN-SEL open. 150 0.5 150 0.5 48 150 0.5 48 0.5 48 µA 48 mA North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 6 RevA0215 CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable Not recommended for new designs MLP8, MSOP8 100K PECL DC Characteristics (VEE = GND, VCC = +5.0V) Symbol Characteristic VOH VOL VIL VBB IIH 85°C Unit Min Max Min Max Min Max Output HIGH Voltage1,2 3955 4165 3975 4165 3975 4165 3975 4165 mV 1,2 3075 3445 3100 3380 3100 3380 3100 3380 mV Input HIGH Voltage D,EN (EN-SEL open)1 3835 4260 3835 4260 3835 4260 3835 4260 mV Input HIGH Voltage EN (EN-SEL tied to VEE)1 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV Input LOW Voltage D,EN (EN-SEL open)1 3100 3525 3100 3525 3100 3525 3100 3525 mV Input LOW Voltage EN (EN-SEL tied to VEE)1 GND 800 GND 800 GND 800 GND 800 mV Reference Voltage1 3610 3750 3610 3750 3610 3750 3610 3750 mV 150 µA Input LOW Current EN 3 150 3 0.5 150 Power Supply Current 0.5 48 1 Voltage levels vary 1:1 with VCC. 2 Specified with CS-SEL open. 3 Specified with EN-SEL open. 150 0.5 2 IEE 25°C Max Input HIGH Current EN IIL 0°C Min Output LOW Voltage VIH -40°C 48 0.5 µA 48 52 mA ¯ HG Outputs1 (VEE = GND, VCC = +3.0V to +5.5V) LVDS DC Characteristics for QHG/Q Symbol Characteristic VOH Output HIGH Voltage VOL Output LOW Voltage VOC Output Common Mode Voltage -40 C Min Max 0 C Min 1600 900 2 25 C Max Min 1600 900 85 C Max Min 1600 900 Max 1600 900 Unit mV mV 1125 1375 1125 1375 1125 1375 1125 1375 mV Change in Common Mode Voltage3 -50 50 -50 50 -50 50 -50 50 mV VOUT Single-Ended Output Swing 250 450 250 450 250 450 250 450 mV VDIFF_OUT Differential Output Swing 500 900 500 900 500 900 500 900 mV VOC 1 ¯ HG together. Specified with 100Ω resistor connecting QHG and Q 2 Common mode voltage is the center voltage between QHG and Q ¯ HG during a steady state. 3 Change in common mode voltage is the difference between common mode voltages at opposite binary states. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 7 RevA0215 CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable Not recommended for new designs MLP8, MSOP8 AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V) Symbol Characteristic tPLH/tPHL Propagation Delay D to Q/Q ¯1 D to tSKEW -40°C Min QHG/Q ¯ HG2 Duty Cycle Skew VPP (AC) Typ Input Swing 3 4 5 0°C Max Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit 400 400 400 430 ps 550 550 550 630 ps 20 ps mV 20 5 20 5 20 5 80 1000 80 1000 80 1000 80 1000 100 260 100 260 100 260 100 260 180 280 180 280 180 280 180 280 1 Output Rise/Fall (20% - 80%) - Q Output Rise/Fall1 (20% - 80%) QHG tr/tf 1 2 3 4 ps Specified with CS-SEL connected to VEE and Q/Q ¯ with AC coupled 50Ω loads. ¯ HG together. Specified with 100Ω resistor connecting QHG and Q Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. The peak-to-peak differential input swing is the range for which AC parameters guaranteed. VD and V must remain within the range of ±750 mV with respect to VBB. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 8 RevA0215 CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MSOP8 Not recommended for new designs PACKAGE DIMENSIONS North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 9 RevA0215 CTSLV399 LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable Not recommended for new designs MLP8, MSOP8 Pin Description and Configuration Pin Assignments for CTSLV399NG Pin Name Type Function 1 Q ¯ Output Inverting PECL Output 2 D Input Data Input 3 VBB Output Reference Voltage 4 EN Input Output Enable 5 VEE Power Negative Supply 6 Q ¯ HG Output Inverting LVDS Output 7 QHG Output LVDS Output 8 VCC Power Positive Supply Pin Assignments for CTSLV399TG Pin Name Type Function 1 Q ¯ Output Inverting PECL Output 2 D Input Data Input 3 VBB Output Reference Voltage 4 EN Input Output Enable 5 VEE Power Negative Supply 6 Q ¯ HG Output Inverting LVDS Output 7 QHG Output LVDS Output 8 VCC Power Positive Supply PART ORDERING INFORMATION Part Number Package Marking CTSLV399NG MLP8 V1G / YWW CTSLV399TG MSOP8 HV99G / YYWW North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 10 RevA0215