CTSLV392NG

CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 FEATURES        BLOCK DIAGRAM Selectable Divide Ratio Selectable Enable Priority and Threshold (CMOS or PECL) 3.0V to 5.5V Power Supply -145dBc/Hz (÷1) Typical Noise Floor -151dBc/Hz (÷2) Typical Noise Floor High BW [1.5GHz (÷1), 3.0GHz (÷2)] ROHS compliant Pb Free Packages DESCRIPTION The CTSLV392 is a ÷1 or ÷2 clock generation part specifically designed to accommodate Colpitts or Pierce based oscillators. Features are incorporated to reduce board components. A voltage reference and input biasing allows for easy oscillator interface. The CTSLV392 provides a ÷ 2 mode of operation for more frequency options and is selectable with a single connection. A selectable enable is also provided which doubles as a reset when the CTSLV392 is in ÷2 mode. With a single connection, the enable can be selected to operate as active high or active low. ENGINEERING NOTES The CTSLV392 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the CTSLV392 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider. A selectable enable is provided which also functions as a reset when the ÷2 mode is selected. Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20kΩ resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pull-down resistor is selected which disables the outputs whenever EN is left open. Connecting the EN-SEL to VEE with a 20kΩ resistor will select the EN pin/pad to function as an active low PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open (NC). This default logic condition can be overridden by connecting the EN to VCC with an external resistor of ≤20kΩ. Refer to the enable truth table on the next page for detailed operation. The CTSLV392 provides a VBB with an 1880Ω internal bias resistor from D to VBB. This feature allows AC coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be bypassed to ground or VCC with a 0.01 μF capacitor. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 1 RevA1113 CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 Divide Truth Table 1 DIV-SEL ÷Ratio NC ÷1 VEE1 ÷2 DIV-SEL connection must be ≤1Ω. Enable Truth Table EN-SEL NC VEE 20kΩ to VEE EN Q Q ¯ CMOS Low or VEE Low Low CMOS High, VCC or NC Data Data CMOS Low, VEE or NC Low Low CMOS High or VCC Data Data PECL Low, VEE or NC Low Low PECL High or VCC Data Data Figure 1 illustrates the timing sequences for the CTSLV392 in the ÷1 mode which is determined by leaving the DIV-SEL open (NC). It also illustrates the enable in the active High mode being controlled by a CMOS signal. This mode is determined by leaving the EN-SEL open (NC). Figure 1 Figure 2 illustrates the timing sequences for the CTSLV392 in the ÷2 mode which is determined by connecting the DIV-SEL to VEE. It also illustrates the enable in the active Low mode being controlled by a PECL signal. This mode is determined by connecting the EN-SEL to VEE via 20kΩ resistor. Figure 2 North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 2 RevA1113 CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol Characteristic Condition Rating Unit VCC PECL Power Supply VEE = 0V 0 to + 6.0 V VI_PECL PECL Input Voltage VEE = 0V 0 to + 6.0 V VEE ECL Power Supply VCC = 0V -6.0 to 0 V VI_ECL ECL Input Supply VCC = 0V -6.0 to 0 V IHGOUT Output Current Continuous 50 Surge 100 Operating Temperature Range - -40 to +85 °C Storage Temperature Range - -65 to +150 °C ESDHBM Human Body Model Electro Static Discharge - 2500 V ESDMM Machine Model Electro Static Discharge - 200 V ESDCDM Charged Device Model Electro Static Discharge - 2000 V TA TSTG mA 100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)  Symbol VOH VOL VIH VIL VBB IIH IIL IEE 1 2 3 4 Characteristic -40°C Min 0°C Max Min 25°C Max Min 85°C Max Min Max Output HIGH -1085 -880 -1025 -880 -1025 -880 -1025 -880 Voltage1 Output LOW -1900 -1555 -1900 -1620 -1900 -1620 -1900 -1620 Voltage1 Input HIGH Voltage D, -1165 -390 -1165 -390 -1165 -390 -1165 -390 EN (ECL)2 Input HIGH Voltage VEE +2000 VCC VEE +2000 VCC VEE +2000 VCC VEE +2000 VCC EN (CMOS)3 Input LOW Voltage D, -2250 -1475 -2250 -1475 -2250 -1475 -2250 -1475 EN (ECL)2 Input LOW Voltage VEE VEE +800 VEE VEE +800 VEE VEE +800 VEE VEE +800 EN (CMOS)3 Reference Voltage -1390 -1250 -1390 -1250 -1390 -1250 -1390 -1250 Input HIGH Current 150 150 150 150 EN Input LOW Current 0.5 0.5 0.5 0.5 EN (ECL)2 Input LOW Current -150 -150 -150 -150 EN (CMOS)3 Power Supply 31 31 31 34 Current4 Specified with each output terminated through 50Ω resistors to VCC -2V. EN-SEL connected to VEE through a 20kΩ resistor. EN-SEL connected to VEE or left open (NC). DIV-SEL left open (NC) Unit mV mV mV mV mV mV mV µA µA mA North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 3 RevA1113 CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) Symbol Characteristic VOH Output HIGH Voltage1,2 VOL 1,2 Output LOW Voltage Input HIGH Voltage D,EN (ECL)3 Input HIGH Voltage EN (CMOS)4 Input LOW Voltage D,EN (ECL)3 Input LOW Voltage EN (CMOS)4 Reference Voltage1 Input HIGH Current EN Input LOW Current EN (ECL)3 Input LOW Current EN (CMOS)4 Power Supply Current5 VIH VIL VBB IIH IIL IEE 1 -40°C Min Max 2215 2420 0°C Min 2275 Max 2420 25°C Min 2275 Max 2420 85°C Min 2275 Max 2420 1400 1745 1400 1680 1400 1680 1400 1680 mV 2135 2910 2135 2910 2135 2910 2135 2910 mV 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV 1050 1825 1050 1825 1050 1825 1050 1825 mV GND 800 GND 800 GND 800 GND 800 mV 1910 2050 150 1910 2050 150 1910 2050 150 1910 2050 150 mV µA 0.5 0.5 0.5 0.5 -150 -150 -150 -150 31 31 Unit mV µA 31 34 mA For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value. Specified with each output terminated through 50Ω resistors to VCC -2V. EN-SEL connected to VEE through a 20kΩ resistor. EN-SEL connected to VEE or left open (NC) DIV-SEL left open (NC) 2 3 4 5 Symbol VOH VOL VIH VIL VBB IIH IIL IEE 100K PECL DC Characteristics (VEE = GND, VCC = +5.0V) -40°C 0°C 25°C Characteristic Min Max Min Max Min Max Output HIGH Voltage1,2 3915 4120 3975 4120 3975 4120 Output LOW Voltage1,2 3100 3445 3100 3380 3100 3380 Input HIGH Voltage D,EN (ECL)3 3835 4610 3835 4610 3835 4610 4 Input HIGH Voltage EN (CMOS) 2000 VCC 2000 VCC 2000 VCC 3 Input LOW Voltage D,EN (ECL) 2750 3525 2750 3525 2750 3525 4 Input LOW Voltage EN (CMOS) GND 800 GND 800 GND 800 Reference Voltage1 3610 3750 3610 3750 3610 3750 Input HIGH Current EN 150 150 150 3 Input LOW Current EN (ECL) 0.5 0.5 0.5 Input LOW Current EN (CMOS)4 -150 -150 -150 Power Supply Current5 31 31 31 85°C Min Max 3975 4120 3100 3380 3835 4610 2000 VCC 2750 3525 GND 800 3610 3750 150 0.5 -150 34 1 For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value. 2 Specified with each output terminated through 50Ω resistors to VCC -2V. 3 EN-SEL connected to VEE through a 20kΩ resistor. 4 EN-SEL connected to VEE or left open (NC). 5 DIV-SEL left open (NC).                                                 Unit mV mV mV mV mV mV mV µA µA mA           North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 4 RevA1113 CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V) Symbol tPLH/tPHL tSKEW VPP (AC) tR/tF 1 2 Characteristic -40°C Min Typ 0°C Max Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit D to Q/Qb1 450 450 450 450 ps D to QHG/QbHG1 600 600 600 600 ps 20 ps Duty Cycle Skew2 Input Swing3 Differential Input Swing3 Single Ended Output Rise/Fall1 (20% - 80%) 5 20 5 20 5 20 5 150 1000 150 1000 150 1000 150 1000 300 2000 300 2000 300 2000 300 2000 80 200 80 200 80 200 200 mV 80 ps Specified with each output terminated through 50Ω resistors to VCC -2V.  Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.  3 VPP is the peak-to-peak differential input swing for which AC parameters are guaranteed. 4 Range valid for AC coupled signals only. VOUTPP (mV) ÷2 ÷1 Input Frequency (MHz) Typical Large Signal Output Swing Measured with 750mV D input, Q/Q ¯ each terminated to VCC-2V via 50Ω resistors. North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 5 RevA1113 CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 Pin Description and Configuration Pin Assignments Pin Name Type Function 1 EN-SEL Input Enable Polarity Select 2 D Input Data Input 3 VBB Input Reference Voltage 4 EN Input Output Enable 5 DIV-SEL Input Divide Select 6 Q ¯ Output Inverted PECL Output 7 Q Output PECL Output 8 VCC Power Positive Supply 9 VEE Power Negative Supply PART ORDERING INFORMATION Part Number Package Marking CTSLV392NG MLP8 P1G / YWW North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors Specifications are subject to change without notice. 6 RevA1113