CY22150FZXI

CY22150 One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Integrated phase-locked loop (PLL) Commercial and industrial operation Flash programmable Field programmable Two-wire I C interface Low skew, low jitter, high accuracy outputs 3.3 V operation with 2.5 V output option 16-pin TSSOP ■ ■ Nonvolatile reprogrammable technology allows easy customization, quick turnaround on design changes and product performance enhancements, and better inventory control. Parts can be reprogrammed up to 100 times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. The CY22150 can be programmed at the package level. In-house programming of samples and prototype quantities is available using the CY3672 Development Kit. Production quantities are available through Cypress’s value added distribution partners or by using third party programmers from BP Microsystems™, HiLo Systems™, and others. The CY22150 provides an industry standard interface for volatile, system level customization of unique frequencies and options. Serial programming and reprogramming allows quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. High performance suited for commercial, industrial, networking, telecom, and other general purpose applications. Application compatibility in standard and low power systems. Industry standard packaging saves on board space. Output Frequency Range Specifications Field programmable Serially programmable Commercial temperature Field programmable Serially programmable Industrial temperature 2 Benefits ■ Internal PLL to generate six outputs up to 200 MHz. Able to generate custom frequencies from an external crystal or a driven source. Performance guaranteed for applications that require an extended temperature range. ■ ■ ■ ■ Part Number CY22150KFZXC Outputs 6 Input Frequency Range 8 MHz to 30 MHz (external crystal) 1 MHz to 133 MHz (driven clock) 8 MHz to 30 MHz (external crystal) 1 MHz to 133 MHz (driven clock) 80 kHz to 200 MHz (3.3 V) 80 KHz to 166.6 MHz (2.5 V) 80 kHz to 166.6 MHz (3.3 V) 80 KHz to 150 MHz (2.5 V) CY22150KFZXI 6 Logic Block Diagram LCLK1 Divider Bank 1 XIN XOUT P LCLK2 Crosspoint Switch Matrix LCLK3 LCKL4 OSC. Q Φ VCO PLL Divider Bank 2 CLK5 CLK6 SDAT I2C Interface SCLK IC Control VDD VSS AVDD AVSS VDDL VSSL 2 Cypress Semiconductor Corporation Document #: 38-07104 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 30, 2011 [+] Feedback CY22150 Contents Pin Configuration ............................................................. 3 Frequency Calculation and Register Definitions ........... 4 Default Startup Condition for the CY22150 .................... 5 Frequency Calculations and Register Definitions using the I2C Interface ................................. 5 Reference Frequency .................................................. 5 PLL Frequency, Q Counter [42H(6..0)] ....................... 6 PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7) ..................................................... 6 PLL Post Divider Options [0CH(7..0)], [47H(7..0)] ....... 7 Charge Pump Settings [40H(2..0)] .............................. 7 Clock Output Settings: CLKSRC – Clock Output Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)] ............................. 8 Test, Reserved, and Blank Registers .......................... 8 I2C Interface Timing ......................................................... 9 Data Valid .................................................................... 9 Data Frame ................................................................. 9 Acknowledge Pulse ..................................................... 9 Applications .................................................................... 11 Controlling Jitter ........................................................ 11 Absolute Maximum Conditions ..................................... 12 Recommended Operating Conditions .......................... 12 DC Electrical Characteristics ........................................ 12 AC Electrical Characteristics ........................................ 13 Device Characteristics ................................................... 13 Ordering Information ...................................................... 14 Possible Configurations ............................................. 14 Ordering Code Definitions ......................................... 15 Package Diagram ............................................................ 15 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 Document #: 38-07104 Rev. *K Page 2 of 18 [+] Feedback CY22150 Pin Configuration Figure 1. 16-Pin TSSOP XIN VDD AVDD SDAT AVSS VSSL LCLK1 LCLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT CLK6 CLK5 VSS LCLK4 VDDL SCLK LCLK3 Table 1. Pin Definitions Name XIN Number 1 Description Reference Input. Driven by a crystal (8 MHz to 30 MHz) or external clock (1 MHz to 133 MHz). Programmable input load capacitors allow for maximum flexibility in selecting a crystal, regardless of manufacturer, process, performance, or quality 3.3 V Voltage Supply 3.3 V Analog Voltage Supply I2C Serial Data Input Analog Ground LCLK Ground Configurable Clock Output 1 at VDDL level (3.3 V or 2.5 V) Configurable Clock Output 2 at VDDL level (3.3 V or 2.5 V) Configurable Clock Output 3 at VDDL level (3.3 V or 2.5 V) I2C Serial Clock Output LCLK Voltage Supply (2.5 V or 3.3 V) Configurable Clock Output 4 at VDDL level (3.3 V or 2.5 V) Ground Configurable Clock Output 5 (3.3 V) Configurable Clock Output 6 (3.3 V) Reference Output VDD AVDD SDAT AVSS VSSL LCLK1 LCLK2 LCLK3 SCLK VDDL LCLK4 VSS CLK5 CLK6 XOUT[1] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note 1. Float XOUT if XIN is driven by an external clock source. Document #: 38-07104 Rev. *K Page 3 of 18 [+] Feedback CY22150 Frequency Calculation and Register Definitions The CY22150 is an extremely flexible clock generator with four basic variables that are used to determine the final output frequency. They are the input reference frequency (REF), the internally calculated P and Q dividers, and the post divider, which can be a fixed or calculated value. There are three formulas to determine the final output frequency of a CY22150 based design: ■ ■ ■ CLK = ((REF * P)/Q)/Post Divider CLK = REF/Post Divider CLK = REF. The basic PLL block diagram is shown in Figure 2. Each of the six clock outputs on the CY22150 has a total of seven output options available to it. There are six post divider options available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N and DIV2N are independently calculated and are applied to individual output groups. The post divider options can be applied to the calculated VCO frequency ((REF*P)/Q) or to the REF directly. In addition to the six post divider output options, the seventh option bypasses the PLL and passes the REF directly to the crosspoint switch matrix. Figure 2. Basic Block Diagram of CY22150 PLL DIV1N [OCH] DIV1SRC [OCH] 1 Qtotal DIV1CLK REF (Q+2) [42H] Ptotal (2(PB+4)+PO) [40H], [41H], [42H] 1 DIV2CLK PFD VCO 0 /DIV1N /2 CLKSRC Crosspoint Switch Matrix [44H] [44H] [44H,45H] /3 Divider Bank 1 Divider Bank 2 /4 /2 /DIV2N [45H] [45H,46H] [45H] LCLK1 LCLK2 LCLK3 LCLK4 0 CLK5 CLK6 DIV2SRC [47H] DIV2N [47H] CLKOE [09H] Document #: 38-07104 Rev. *K Page 4 of 18 [+] Feedback CY22150 Default Startup Condition for the CY22150 The default (programmed) condition of the device is generally set by the distributor who programs the device using a customer specific JEDEC file produced by CyClocksRT™. Parts shipped from the factory are blank and unprogrammed. In this condition, all bits are set to 0, all outputs are three-stated, and the crystal oscillator circuit is active. While you can develop your own subroutine to program any or all of the individual registers described in the following pages, it may be easier to use CyClocksRT to produce the required register setting file. The serial interface address of the CY22150 is 69H. If there is a conflict with any other devices in your system, then this can also be changed using CyClocksRT. Table 2 lists the I2C registers and their definitions. Specific register definitions and their allowable values are listed below. Reference Frequency The REF can be a crystal or a driven frequency. For crystals, the frequency range must be between 8 MHz and 30 MHz. For a driven frequency, the frequency range must be between 1 MHz and 133 MHz. Using a Crystal as the Reference Input The input crystal oscillator of the CY22150 is an important feature because of the flexibility it allows the user in selecting a crystal as a REF source. The input oscillator has programmable gain, allowing maximum compatibility with a reference crystal, regardless of manufacturer, process, performance, and quality. Programmable Crystal Input Oscillator Gain Settings The Input crystal oscillator gain (XDRV) is controlled by two bits in register 12H and are set according to Table 3 on page 6. The parameters controlling the gain are the crystal frequency, the internal crystal parasitic resistance (ESR, available from the manufacturer), and the CapLoad setting during crystal startup. Bits 3 and 4 of register 12H control the input crystal oscillator gain setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The setting is programmed according to Table 3 on page 6. All other bits in the register are reserved and should be programmed as shown in Table 4 on page 6. Using an External Clock as the Reference Input The CY22150 also accepts an external clock as reference, with speeds up to 133 MHz. With an external clock, the XDRV (register 12H) bits must be set according to Table 5 on page 6. Frequency Calculations and Register Definitions using the I2C Interface The CY22150 provides an industry standard serial interface for volatile, in-system programming of unique frequencies and options. Serial programming and reprogramming allows for quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. The I2C Interface provides volatile programming. This means when the target system is powered down, the CY22150 reverts to its pre-I2C state, as defined above (programmed or unprogrammed). When the system is powered back up again, the I2C registers must be reconfigured again. All programmable registers in the CY22150 are addressed with eight bits and contain eight bits of data. The CY22150 is a slave device with an address of 1101001 (69H). Table 2. Summary Table – CY22150 Programmable Registers Register 09H OCH 12H 13H 40H 41H 42H 44H 45H 46H 47H DIV2SRC mux and DIV2N divider Description CLKOE control DIV1SRC mux and DIV1N divider Input crystal oscillator drive control Input load capacitor control Charge pump and PB counter PO counter, Q counter Crosspoint switch matrix control D7 0 DIV1SRC 0 CapLoad (7) 1 PB(7) PO D6 0 DIV1N(6) 0 CapLoad (6) 1 PB(6) Q(6) D5 D4 CLK5 DIV1N(4) XDRV(1) CapLoad (4) Pump(2) PB(4) Q(4) D3 LCLK4 DIV1N(3) XDRV(0) CapLoad (3) Pump(1) PB(3) Q(3) D2 LCLK3 DIV1N(2) 0 CapLoad (2) Pump(0) PB(2) Q(2) D1 LCLK2 DIV1N(1) 0 CapLoad (1) PB(9) PB(1) Q(1) D0 LCLK1 DIV1N(0) 0 CapLoad (0) PB(8) PB(0) Q(0) CLK6 DIV1N(5) 1 CapLoad (5) 0 PB(5) Q(5) CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 for LCLK1 for LCLK1 for LCLK1 for LCLK2 for LCLK2 for LCLK2 for LCLK3 for LCLK3 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 for LCLK3 for LCLK4 for LCLK4 for LCLK4 for CLK5 for CLK5 for CLK5 for CLK6 CLKSRC1 CLKSRC0 for CLK6 for CLK6 DIV2SRC DIV2N(6) 1 DIV2N(5) 1 DIV2N(4) 1 DIV2N(3) 1 DIV2N(2) 1 DIV2N(1) 1 DIV2N(0) Document #: 38-07104 Rev. *K Page 5 of 18 [+] Feedback CY22150 Table 3. Programmable Crystal Input Oscillator Gain Settings Cap Register Settings Effective Load Capacitance (CapLoad) Crystal ESR Crystal Input Frequency 8 to 15 MHz 15 to 20 MHz 20 to 25 MHz 25 to 30 MHz 00H – 80H 6 pF to 12 pF 30Ω 00 01 01 10 60Ω 01 10 10 10 80H – C0H 12 pF to 18 pF 30Ω 01 01 10 10 60Ω 10 10 10 11 C0H – FFH 18 pF to 30 pF 30Ω 01 10 10 11 60Ω 10 10 11 N/A Table 4. Crystal Oscillator Gain Bit Locations and Values Address 12H D7 0 D6 0 D5 1 D4 XDRV(1) D3 XDRV(0) D2 0 D1 0 D0 0 Table 5. Programmable External Reference Input Oscillator Drive Settings Reference Frequency Drive Setting Input Load Capacitors Input load capacitors allow the user to set the load capacitance of the CY22150 to match the input load capacitance from a crystal. The value of the input load capacitors is determined by 8 bits in a programmable register [13H]. Total load capacitance is determined by the formula: CapLoad = (CL– CBRD – CCHIP)/0.09375 pF where: ■ ■ 1 to 25 MHz 00 25 to 50 MHz 01 50 to 90 MHz 10 90 to 133 MHz 11 PLL Frequency, Q Counter [42H(6..0)] The first counter is known as the Q counter. The Q counter divides REF by its calculated value. Q is a 7 bit divider with a maximum value of 127 and minimum value of 0. The primary value of Q is determined by 7 bits in register 42H (6..0), but 2 is added to this register value to achieve the total Q, or Qtotal. Qtotal is defined by the formula: Qtotal = Q + 2 The minimum value of Qtotal is 2. The maximum value of Qtotal is 129. Register 42H is defined in the table. Stable operation of the CY22150 cannot be guaranteed if REF/Qtotal falls below 250 kHz. Qtotal bit locations and values are defined in Table 7 on page 7. CL = specified load capacitance of your crystal. CBRD = the total board capacitance, due to external capacitors and board trace capacitance. In CyClocksRT, this value defaults to 2 pF. CCHIP = 6 pF. 0.09375 pF = the step resolution available due to the 8-bit register. ■ ■ PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7) The next counter definition is the P (product) counter. The P counter is multiplied with the (REF/Qtotal) value to achieve the VCO frequency. The product counter, defined as Ptotal, is made up of two internal variables, PB and PO. The formula for calculating Ptotal is: Ptotal = (2(PB + 4) + PO) PB is a 10-bit variable, defined by registers 40H(1:0) and 41H(7:0). The 2 LSBs of register 40H are the two MSBs of variable PB. Bits 4..2 of register 40H are used to determine the charge pump settings. The 3 MSBs of register 40H are preset and reserved and cannot be changed. PO is a single bit variable, defined in register 42H(7). This allows for odd numbers in Ptotal. The remaining seven bits of 42H are used to define the Q counter, as shown in Table 7. The minimum value of Ptotal is 8. The maximum value of Ptotal is 2055. To achieve the minimum value of Ptotal, PB and PO should both be programmed to 0. To achieve the maximum value of Ptotal, PB should be programmed to 1023, and PO should be programmed to 1. Page 6 of 18 In CyclocksRT, only the crystal capacitance (CL) is specified. CCHIP is set to 6 pF and CBRD defaults to 2 pF. If your board capacitance is higher or lower than 2 pF, the formula given earlier is used to calculate a new CapLoad value and programmed into register 13H. In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22150. Through the SDAT and SCLK pins, the value can be adjusted up or down if your board capacitance is greater or less than 2 pF. For an external clock source, CapLoad defaults to 0. See Table 6 on page 7 for CapLoad bit locations and values. The input load capacitors are placed on the CY22150 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when nonlinear load capacitance is affected by load, bias, supply, and temperature changes. Document #: 38-07104 Rev. *K [+] Feedback CY22150 Stable operation of the CY22150 cannot be guaranteed if the value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below 100 MHz. of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to work properly. DIV1SRC is a single bit variable, controlled by register 0CH. The remaining seven bits of register 0CH determine the value of post divider DIV1N. DIV2SRC is a single bit variable, controlled by register 47H. The remaining seven bits of register 47H determine the value of post divider DIV2N. Register 0CH and 47H are defined in Table 8. PLL Post Divider Options [0CH(7..0)], [47H(7..0)] The output of the VCO is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. The mux determines if the clock signal feeding into the divider banks is the calculated VCO frequency or REF. There are two select muxes (DIV1SRC and DIV2SRC) and two divider banks (Divider Bank 1 and Divider Bank 2) used to determine this clock signal. The clock signal passing through DIV1SRC and DIV2SRC is referred to as DIV1CLK and DIV2CLK, respectively. The divider banks have four unique divider options available: /2, /3, /4, and /DIVxN. DIVxN is a variable that can be independently programmed (DIV1N and DIV2N) for each of the two divider banks. The minimum value of DIVxN is 4. The maximum value Table 6. Input Load Capacitor Register Bit Settings Address 13H D7 CapLoad(7) D6 CapLoad(6) D5 CapLoad(5) D4 Charge Pump Settings [40H(2..0)] The correct pump setting is important for PLL stability. Charge pump settings are controlled by bits (4..2) of register 40H, and are dependent on internal variable PB (see “PLL Frequency, P Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 9 on page 7 summarizes the proper charge pump settings, based on Ptotal. See Table 10 on page 7 for register 40H bit locations and values. D3 CapLoad(3) D2 CapLoad(2) D1 CapLoad(1) D0 CapLoad(0) CapLoad(4) Table 7. P Counter and Q Counter Register Definition Address 40H 41H 42H D7 1 PB(7) PO D6 1 PB(6) Q(6) D5 0 PB(5) Q(5) D4 Pump(2) PB(4) Q(4) D3 Pump(1) PB(3) Q(3) D2 Pump(0) PB(2) Q(2) D1 PB(9) PB(1) Q(1) D0 PB(8) PB(0) Q(0) Table 8. PLL Post Divider Options Address 0CH 47H D7 DIV1SRC DIV2SRC D6 DIV1N(6) DIV2N(6) D5 DIV1N(5) DIV2N(5) D4 DIV1N(4) DIV2N(4) D3 DIV1N(3) DIV2N(3) D2 DIV1N(2) DIV2N(2) D1 DIV1N(1) DIV2N(1) D0 DIV1N(0) DIV2N(0) Table 9. Charge Pump Settings Charge Pump Setting – Pump(2..0) 000 001 010 011 100 101, 110, 111 Table 10. Register 40H Change Pump Bit Settings Address 40H D7 1 D6 1 D5 0 D4 Pump(2) D3 Pump(1) D2 Pump(0) D1 PB(9) D0 PB(8) Calculated Ptotal 16 – 44 45 – 479 480 – 639 640 – 799 800 – 1023 Do not use – device will be unstable Although using the above table guarantees stability, it is recommended to use the Print Preview function in CyClocksRT to determine the correct charge pump settings for optimal jitter performance. PLL stability cannot be guaranteed for values below 16 and above 1023. If values above 1023 are needed, use CyClocksRT to determine the best charge pump setting. Document #: 38-07104 Rev. *K Page 7 of 18 [+] Feedback CY22150 Clock Output Settings: CLKSRC – Clock Output Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)] Every clock output can be defined to come from one of seven unique frequency sources. The CLKSRC(2..0) crosspoint switch matrix defines which source is attached to each individual clock output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H. The remainder of register 46H(5:0) must be written with the values stated in the register table when writing register values 46H(7:6). When DIV1N is divisible by four, then CLKSRC(0,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is guaranteed to be rising edge phase-aligned with CLKSRC(0,0,1). When DIV2N is divisible by four, then CLKSRC(1,0,1) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). When DIV2N is divisible by eight, then Table 11. Clock Output Setting CLKSRC2 0 0 0 0 1 1 1 1 CLKSRC1 0 0 1 1 0 0 1 1 CLKSRC0 0 1 0 1 0 1 0 1 Reference input. CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). CLKOE – Clock Output Enable Control [09H(5..0)] Each clock output has its own output enable, controlled by register 09H(5..0). To enable an output, set the corresponding CLKOE bit to 1. CLKOE settings are in Table 13 on page 8. The output swing of LCLK1 through LCLK4 is set by VDDL. The output swing of CLK5 and CLK6 is set by VDD. Test, Reserved, and Blank Registers Writing to any of the following registers causes the part to exhibit abnormal behavior, as follows. [00H to 08H] [0AH to 0BH] [0DH to 11H] [14H to 3FH] [43H] [48H to FFH] – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved. Definition and Notes DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8. DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4. DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6. DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4. DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8. Reserved – do not use. Table 12. Clock Output Register Setting Address 44H 45H 46H D7 D6 D5 D4 D3 D2 D1 D0 CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKSRC1 for LCLK1 LCLK1 LCLK1 LCLK2 LCLK2 LCLK2 LCLK3 LCLK3 CLKSRC0 for CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for LCLK3 LCLK4 LCLK4 LCLK4 CLK5 CLK5 CLK5 CLK6 CLKSRC1 for CLKSRC0 for CLK6 CLK6 1 1 1 1 1 1 Table 13. CLKOE Bit Setting Address 09H D7 0 D6 0 D5 CLK6 D4 CLK5 D3 LCLK4 D2 LCLK3 D1 LCLK2 D0 LCLK1 Document #: 38-07104 Rev. *K Page 8 of 18 [+] Feedback CY22150 I2C Interface Timing The CY22150 uses a two-wire I2C-interface that operates up to 400 kbits/second in Read or Write mode. The basic Write serial format is as follows. Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); eight-bit Memory Address (MA); ACK; eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK; eight-bit data in MA+2; ACK; and so on until STOP bit.The basic serial format is illustrated in Figure 4 on page 9. Start Sequence – Start frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a Start signal is given, the next eight-bit data must be the device address (seven bits) and a R/W bit, followed by register address (eight bits) and register data (eight bits). Stop Sequence – Stop frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop frame frees the bus for writing to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write mode, the CY22150 responds with an ACK pulse after every eight bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle, as illustrated in Figure 6 on page 10. (N = the number of eight-bit segments transmitted.) During Read mode, the ACK pulse after the data packet is sent is generated by the master Data Valid Data is valid when the Clock is HIGH, and may only be transitioned when the clock is LOW, as illustrated in Figure 3. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 5 on page 10. . Figure 3. Data Valid and Data Transition Periods Data valid SDAT Transition to next bit CLKHIGH VIH SCLK VIL tDH tSU CLKLOW Figure 4. Data Frame Architecture SDAT Write Multiple Contiguous Registers Start Signal 1-bit 1-bit 1-bit 1-bit 1-bit Slave Slave Slave Slave ACK ACK R/W = 0 ACK ACK 7-bit 8-bit 8-bit 8-bit 8-bit Device Register Register Register Register Data Address Address Data Data (XXH) (XXH) (XXH+1) (XXH+2) 1-bit Slave ACK 1-bit Slave ACK 1-bit Slave ACK 1-bit Slave ACK 8-bit Register Data (FFH) 8-bit Register Data (00H) Stop Signal SDAT Read Multiple Contiguous Registers Start Signal 1-bit 1-bit 1-bit 1-bit Slave Slave 1-bit Master R/W = 1 ACK R/W = 0 ACK ACK 7-bit 8-bit 8-bit 8-bit Device Register 7-Bit Register Register Address Address Device Data Data (XXH) Address (XXH) (XXH+1) 1-bit Master ACK 1-bit Master ACK 1-bit Master ACK 1-bit Master ACK 8-bit Register Data (FFH) 8-bit Register Data (00H) Stop Signal Document #: 38-07104 Rev. *K Page 9 of 18 [+] Feedback CY22150 Figure 5. Start and Stop Frame SDAT SCLK STOP START Transition to next bit Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data SDAT + START DA6 SCLK DA5DA0 + R/W ACK RA7 + RA6RA1 + RA0 ACK D7 D6 + + D1 D0 ACK STOP Parameter fSCLK CLKLOW CLKHIGH tSU tDH Frequency of SCLK Description Start mode time from SDA LOW to SCL LOW SCLK LOW period SCLK HIGH period Data transition to SCLK HIGH Data hold (SCLK LOW to data transition) Rise time of SCLK and SDAT Fall time of SCLK and SDAT Stop mode time from SCLK HIGH to SDAT HIGH Stop mode to Start mode Min – 0.6 1.3 0.6 100 100 – – 0.6 1.3 Max 400 – – – – – 300 300 – – Unit kHz μs μs μs ns ns ns ns μs μs Document #: 38-07104 Rev. *K Page 10 of 18 [+] Feedback CY22150 Applications Controlling Jitter Jitter is defined in many ways including: phase noise, long term jitter, cycle to cycle jitter, period jitter, absolute jitter, and deterministic. These jitter terms are usually given in terms of rms, peak to peak, or in the case of phase noise dBC/Hz with respect to the fundamental frequency. Power supply noise and clock output loading are two major system sources of clock jitter. Power supply noise is mitigated by proper power supply decoupling (0.1 μF ceramic cap 0.25”) of the clock and ensuring a low impedance ground to the chip. Reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. Reducing the total number of active outputs also reduce jitter in a linear fashion. However, it is better to use two outputs to drive two loads than one output to drive two loads. The rate and magnitude that the PLL corrects the VCO frequency is directly related to jitter performance. If the rate is too slow, then long term jitter and phase noise is poor. Therefore, to improve long term jitter and phase noise, reducing Q to a minimum is advisable. This technique increases the speed of the Phase Frequency Detector which in turn drive the input voltage of the VCO. In a similar manner increasing P till the VCO is near its maximum rated speed also decreases long term jitter and phase noise. For example: Input Reference of 12 MHz; desired output frequency of 33.3 MHz. The following solution is possible: Set Q = 3, P = 25, Post Div = 3. However, the best jitter results is Q = 2, P = 50, Post Div = 9. For more information, contact your local Cypress field applications engineer. Figure 7. Test Circuit VDD 0.1 mF OUTPUTS CLK out C LOAD AVDD 0.1 mF GND Figure 8. Duty Cycle Definition; DC = t2/t1 t3 80% t4 VDDL 0.1 μ F Figure 9. Rise and Fall Time Definitions t1 t2 CLK 50% 50% CLK 20% Figure 10. Peak-to-Peak Jitter t6 Document #: 38-07104 Rev. *K Page 11 of 18 [+] Feedback CY22150 Absolute Maximum Conditions Parameter VDD VDDL TS TJ Supply Voltage I/O Supply Voltage Storage Temperature[2] Junction Temperature Package Power Dissipation – Commercial Temp Package Power Dissipation – Industrial Temp Digital Inputs Digital Outputs Referred to VDD Digital Outputs Referred to VDDL ESD Static Discharge Voltage per MIL-STD-833, Method 3015 Description Min –0.5 –0.5 –65 – – – AVSS – 0.3 VSS – 0.3 VSS – 0.3 – Max 7.0 7.0 125 125 450 380 AVDD + 0.3 VDD + 0.3 VDDL +0.3 2000 Unit V V °C °C mW mW V V V V Recommended Operating Conditions Parameter VDD VDDLHI[3] VDDLLO[3] TAC TAI CLOAD CLOAD fREFD fREFC tPU Operating Voltage Operating Voltage Operating Voltage Ambient Commercial Temp Ambient Industrial Temp Max. Load Capacitance, VDD/VDDL = 3.3 V Max. Load Capacitance, VDDL = 2.5 V Driven REF Crystal REF Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.135 3.135 2.375 0 –40 – – 1 8 0.05 Typ. 3.3 3.3 2.5 – – – – – – – Max 3.465 3.465 2.625 70 85 15 15 133 30 500 Unit V V V °C °C pF pF MHz MHz ms DC Electrical Characteristics Parameter[4] IOH3.3 IOL3.3 IOH2.5 IOL2.5 VIH VIL CIN IIZ VHYS IVDD[5,6] IVDDL3.3 [5,6] Name Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Input Capacitance Input Leakage Current Hysteresis of Schmitt triggered inputs Supply Current Supply Current Supply Current Description VOH = VDD – 0.5, VDD/VDDL = 3.3 V (sink) VOL = 0.5, VDD/VDDL = 3.3 V (source) VOH = VDDL – 0.5, VDDL = 2.5 V (source) VOL = 0.5, VDDL = 2.5 V (sink) CMOS levels, 70% of VDD CMOS levels, 30% of VDD SCLK and SDAT Pins SCLK and SDAT Pins SCLK and SDAT Pins AVDD/VDD Current VDDL Current (VDDL = 3.465 V) VDDL Current (VDDL = 2.625 V) Min 12 12 8 8 0.7 – – – 0.05 – – – Typ. 24 24 16 16 – – – 5 – 45 25 17 Max – – – – – 0.3 7 – – – – – Unit mA mA mA mA VDD VDD pF μA VDD mA mA mA IVDDL2.5[5,6] Notes 2. Rated for 10 years. 3. VDDLis only specified and characterized at 3.3 V ± 5% and 2.5 V ± 5%. VDDLmay be powered at any value between 3.465 V and 2.375 V. 4. Not 100% tested. 5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz. 6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations. Document #: 38-07104 Rev. *K Page 12 of 18 [+] Feedback CY22150 AC Electrical Characteristics Parameter[7] t1 Name Output Frequency, Commercial Temp Output Frequency, Industrial Temp Description Clock output limit, 3.3 V Clock output limit, 2.5 V Clock output limit, 3.3 V Clock output limit, 2.5 V Duty cycle is defined in Figure 8 on page 11; t1/t2 fOUT < 166 MHz, 50% of VDD Duty cycle is defined in Figure 8; t1/t2 fOUT > 166 MHz, 50% of VDD Output clock rise time, 20% to 80% of VDDL. Defined in Figure 9 Output dlock fall time, 80% to 20% of VDDL. Defined in Figure 9 Output dlock rise time, 20% to 80% of VDD/VDDL. Defined in Figure 9 Output dlock fall time, 80% to 20% of VDD/VDDL. Defined in Figure 9 Output-output skew between related outputs Peak-to-peak period jitter Min 0.08 (80 kHz) 0.08 (80 kHz) 0.08 (80 kHz) 0.08 (80 kHz) 45 Typ. – – – – 50 Max 200 166.6 166.6 150 55 Unit MHz MHz MHz MHz % t2LO Output Duty Cycle t2HI t3LO t4LO t3HI t4HI t5[8] t6[9] t10 Output Duty Cycle Rising Edge Slew Rate (VDDL = 2.5 V) Falling Edge Slew Rate (VDDL = 2.5 V) Rising Edge Slew Rate (VDDL = 3.3 V) Falling Edge Slew Rate (VDDL = 3.3 V) Skew Clock Jitter PLL Lock Time 40 0.6 0.6 0.8 0.8 – – – 50 1.2 1.2 1.4 1.4 – 250 0.30 60 – – – – 250 – 3 % V/ns V/ns V/ns V/ns ps ps ms Device Characteristics Parameter θJA Complexity Name Theta JA Transistor Count Value 115 74,600 Unit °C/W Transistors 7. Not 100% tested, guaranteed by design. 8. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram on page 1 for more information. 9. Jitter measurements vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL, (2.5 V or 3.3 V jitter). Document #: 38-07104 Rev. *K Page 13 of 18 [+] Feedback CY22150 Ordering Information Ordering Code CY22150KFI Pb-Free CY22150FZXC[11] CY22150FZXCT CY22150FZXIT [11] Package Type 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel 16-Pin TSSOP 16-Pin TSSOP - Tape and Reel Programmer with USB interface CY22150 Adapter Socket for CY3672-USB Operating Range Industrial (–40 to 85°C) Commercial (0 to 70°C) Commercial (0 to 70°C) Industrial (–40 to 85°C) Industrial (–40 to 85°C) Commercial (0 to 70°C) Commercial (0 to 70°C) Industrial (–40 to 85°C) Industrial (–40 to 85°C) Operating Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V CY22150FZXI[11] [11] CY22150KFZXC CY22150KFZXCT CY22150KFZXI CY22150KFZXIT Programmer CY3672-USB CY3695 Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales Representative for more information. Possible Configurations Ordering Code CY22150ZXC-xxx[10, 11] CY22150ZXC-xxxT[10, 11] CY22150ZXI-xxx[10, 11] CY22150ZXI-xxxT[10, 11] CY22150ZI-xxxT[10, 11] CY22150KZI-xxx[10] CY22150KZI-xxxT[10] CY22150KZXI-xxxT[10] Package Type 16-Pin TSSOP 16-Pin TSSOP- Tape and Reel 16-Pin TSSOP 16-Pin TSSOP- Tape and Reel 16-Pin TSSOP- Tape and Reel 16-Pin TSSOP 16-Pin TSSOP- Tape and Reel 16-Pin TSSOP- Tape and Reel Operating Range Commercial (0 to 70°C) Commercial (0 to 70°C) Industrial (–40 to 85°C) Industrial (–40 to 85°C) Industrial (–40 to 85°C) Industrial (–40 to 85°C) Industrial (–40 to 85°C) Industrial (–40 to 85°C) Operating Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Notes 10. The CY22150ZC-xxx and CY22150ZI-xxx are factory programmed configurations. Factory programming is available for high volume design opportunities of 100 Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative. 11. Not recommended for new designs. Document #: 38-07104 Rev. *K Page 14 of 18 [+] Feedback CY22150 Ordering Code Definitions CY 22150 K F Z X C - XXX T Tape and reel Dash code. For factoryprogrammed devices only Temperature range: C = Commercial; I = Industrial Lead-free 16-pin TSSOP package Field programmable device Indicates foundry manufacturing Base part number Company Code: CY = Cypress Package Diagram Figure 11. 16-Pin TSSOP 4.40 mm Body Z16.173 51-85091 *C Document #: 38-07104 Rev. *K Page 15 of 18 [+] Feedback CY22150 Acronyms Table 14. Acronyms Used in this Documnent Acronym ACK BSC CLKOE CMOS DA ESD ESR FAE I/O I2C JEDEC Description acknowledge basic spacing between centers clock output enable complementary metal oxide semiconductor device address electrostatic discharge equivalent series resistance field applications engineer input / output inter integrated circuit joint electron device engineering council Acronym LSB MA MSB PFD PLL SCLK SDAT TSSOP USB VCO Description least significant bit memory address most significant bit phase frequency detector phase locked loop serial interface clock serial interface data thin shrunk small outline package universal serial bus voltage-controlled oscillator Document Conventions Units of Measure Table 15. Units of Measure Symbol °C dB dBc/Hz fC fF Hz KB Kbit kHz kΩ MHz MΩ µA µF µH µs µV Unit of Measure degrees Celsius decibels decibels relative to the carrier per Hertz femto Coulomb femto Farads hertz 1024 bytes 1024 bits kilohertz kilohms megahertz megaohms microamperes microfarads microhenrys microseconds microvolts Symbol µVrms µW mA mm ms mV nA ns nV Ω pA pF pp ppm ps sps σ Unit of Measure microvolts root-mean-square microwatts milliamperes millimeters milliseconds millivolts nanoamperes nanoseconds nanovolts ohms picoamperes pico Farads peak-to-peak parts per million picoseconds samples per second sigma: one standard deviation Document #: 38-07104 Rev. *K Page 16 of 18 [+] Feedback CY22150 Document History Page Document Title: CY22150 One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator Document Number: 38-07104 Revision ** *A *B ECN 107498 110043 113514 Submission Date 08/08/01 02/06/02 05/01/02 Orig. of Change CKN CKN CKN Description of Change New Data Sheet Preliminary to Final Removed overline on Figure 6 Register Address Register Data Changed CLKHIGH unit from ns to μs in parameter description table Added (sink) to rows 1 and 4 and added (source) to rows 2 and 3 in the DC Electrical Characteristics table (Figure ) Power up requirements added to Operating Conditions Information Changed 0 to 1 under 12H/D5 of Table 2 and Table 4. Reworded and reformatted Programmable Crystal Input Oscillator Gain Settings text. Minor Change: Fixed the broken line in the block diagram Corrected Table 2 specs. Added Pb-Free Devices Updated template. Added Note “Not recommended for new designs.” Added part number CY22150KFC, CY22150KFCT, CY22150KFI, CY22150KFZXC, CY22150KFZXCT, CY22150KFZXI, CY22150KFZXIT, CY22150KZXI-xxxT, and CY22150KZI-xxxT in ordering information table. Replaced Lead Free with Pb-Free. *C *D 121868 125453 12/14/02 05/19/03 RBI CKN *E *F *G *H 242808 252352 296084 2440846 See ECN See ECN See ECN See ECN RGL RGL RGL AESA *I 2649578 01/29/09 KVM/PYRS Removed reference to note “Not recommended for new designs” for the following parts: CY22150KFC, CY22150KFCT, CY22150KFI Added CY22150KZI-xxx to the Ordering Information Table Removed CY22150ZC-xxx, CY22150ZC-xxxT and CY22150ZI-xxx from the Ordering Information Table Changed CY3672 to CY3672-USB, and moved to the bottom of the table KVM Changed title from "One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator" to "One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator" Updated table on page 1. Changed references to Serial Programming Interface (SPI) to I2C Interface in Features and Logic Block Diagram. Removed inactive parts from Ordering Information. Added Possible Configurations table for “xxx” parts. Changed tDH min spec from 0 ns to 100 ns. Updated package diagram. Added ordering code defintions, Acronyms and units of measure. *J 2900690 03/29/2010 *K 3210225 03/30/2011 CXQ Document #: 38-07104 Rev. *K Page 17 of 18 [+] Feedback CY22150 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07104 Rev. *K Revised March 30, 2011 Page 18 of 18 BP Microsystems is a trademark of BP Microsystems. HiLo Systems is a trademark of Hi-Lo Systems, Inc. CyClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback