CY2292FZXI

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Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY2292 Three-PLL General-Purpose EPROM-Programmable Clock Generator Three-PLL General-Purpose EPROM-Programmable Clock Generator Features Benefits ■ Three integrated phase locked loops (PLLs) ■ ■ Erasable programmable read only memory (EPROM) programmability Generates up to three custom frequencies from one external source ■ Easy customization and fast turnaround ■ Programming support available for all opportunities ■ Supports low power applications ■ Eight user selectable frequencies on CPU PLL ■ Allows downstream PLLs to stay locked on CPUCLK output ■ Industry standard packaging saves on board space ■ Factory programmable (CY2292) or field programmable (CY2292F) device options ■ Low-skew, low-jitter, high accuracy outputs ■ Power management options (shutdown, OE, suspend) ■ Frequency select option ■ Smooth slewing on CPUCLK ■ Configurable 3.3 V or 5 V operation ■ 16-pin small-outline integrated circuit (SOIC) package (CY2292F also in TSSOP) Functional Description For a complete list of related documentation, click here. Selector Guide Part Number Input Frequency Range Output Frequency Range CY2292SC, SL, SXC, SXL 10 MHz to 25 MHz (external crystal) 76.923 kHz to 100 MHz (5 V) 1 MHz to 30 MHz (reference clock) 76.923 kHz to 80 MHz (3.3 V) Specifics Factory programmable Commercial temperature CY2292SI, SXI 10 MHz to 25 MHz (external crystal) 76.923 kHz to 90 MHz (5 V) Factory programmable 1 MHz to 30 MHz (reference clock) 76.923 kHz to 66.6 MHz (3.3 V) Industrial temperature CY2292F, FXC, FZX 10 MHz to 25 MHz (external crystal) 76.923 kHz to 90 MHz (5 V) Field programmable 1 MHz to 30 MHz (reference clock) 76.923 kHz to 66.6 MHz (3.3 V) Commercial temperature CY2292FXI, FZXI 10 MHz to 25 MHz (external crystal) 76.923 kHz to 80 MHz (5 V) Field programmable 1 MHz to 30 MHz (reference clock) 76.923 kHz to 60.0 MHz (3.3 V) Industrial temperature Logic Block Diagram XTALIN XBUF OSC. XTALOUT CPLL ( 8 BIT) /1,2,4 CPUCLK S0 CLKA S1 S2 / SUSPEND /1,2,4,8 SPLL ( 8 BIT) /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96, 104 CLKB CLKC CLKD CONFIG EPROM SHUTDOWN / OE Cypress Semiconductor Corporation Document Number: 38-07449 Rev. *M MUX UPLL ( 10 BIT) • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 7, 2017 CY2292 Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Operation ........................................................................... 4 Output Configuration ................................................... 4 Power Saving Features ............................................... 4 CyClocks Software ........................................................... 4 Cypress FTG Programmer ............................................... 4 Custom Configuration Request Procedure .................... 4 Maximum Ratings ............................................................. 5 Operating Conditions ....................................................... 5 Electrical Characteristics ................................................. 6 Electrical Characteristics ................................................. 6 Electrical Characteristics ................................................. 7 Electrical Characteristics ................................................. 7 Test Circuit ........................................................................ 8 Switching Characteristics ................................................ 9 Switching Characteristics .............................................. 10 Switching Characteristics .............................................. 11 Document Number: 38-07449 Rev. *M Switching Characteristics .............................................. 12 Switching Waveforms .................................................... 13 Ordering Information ...................................................... 14 Possible Configurations ............................................. 14 Ordering Code Definitions ......................................... 14 Package Characteristics ................................................ 15 Package Diagrams .......................................................... 15 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC® Solutions ...................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 2 of 19 CY2292 Pinouts Figure 1. 16-pin SOIC / TSSOP pinout CLKC 1 16 SHUTDOWN/OE VDD GND 2 15 S2/SUSPEND 3 14 XTALIN 4 13 VDD S1 XTALOUT XBUF 5 12 6 11 S0 GND CLKD 7 10 CLKA CPUCLK 8 9 CLKB Pin Definitions Name CLKC Pin Number 1 Description Configurable clock output C. VDD 2, 14 Voltage supply. GND 3, 11 Ground. [1] XTALIN [1, 2] XTALOUT 4 Reference crystal input or external reference clock input. 5 Reference crystal feedback. XBUF 6 Buffered reference clock output. CLKD 7 Configurable clock output D. CPUCLK 8 CPU frequency clock output. CLKB 9 Configurable clock output B. CLKA 10 Configurable clock output A. S0 12 CPU clock select input, bit 0. S1 13 CPU clock select input, bit 1. S2/SUSPEND 15 CPU clock select input, bit 2. Optionally enables suspend feature when LOW. SHUTDOWN/OE 16 Places outputs in tristate[3] condition and shuts down chip when LOW. Optionally, only places outputs in tristate[3] condition and does not shut down chip when LOW. Notes 1. For best accuracy, use a parallel-resonant crystal, CLOAD  17 pF or 18 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). 3. The CY2292 has weak pull downs on all outputs. Hence, when a tristate condition is forced on the outputs, the output pins are pulled low. Document Number: 38-07449 Rev. *M Page 3 of 19 CY2292 Operation The CY2292 is a third-generation family of clock generators. The CY2292 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems. All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable clock outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related frequencies have low (less than 500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The CY2292 can be configured for either 5 V or 3.3 V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator is designed for 10 MHz to 25 MHz crystals, providing additional flexibility. No external components are required with this crystal. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. Output Configuration The CY2292 has four independent frequency sources on-chip. These are the reference oscillator and three PLLs. Each PLL has a specific function. The system PLL (SPLL) provides fixed output frequencies on the configurable outputs. The SPLL offers the most output frequency divider options. The CPU PLL (CPLL) is controlled by the select inputs (S0–S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The utility PLL (UPLL) provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources. All configurations are EPROM programmable, providing short sample and production lead times. Power Saving Features The SHUTDOWN/OE input tristates the outputs when pulled LOW. If system shutdown is enabled, a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins is less than 50 µA (for commercial temperature or 100 µA for industrial temperature). After leaving shutdown mode, the PLLs have to relock. All outputs have a weak pull down so that the outputs do not float when tristated.[4] The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a tristate condition. The CPUCLK can slew (transition) smoothly between 20 MHz and the maximum output frequency (100 MHz at 5 V / 80 MHz at 3.3 V for commercial temperature parts or 90 MHz at 5 V / 66.6 MHz at 3.3 V for industrial temperature and for field-programmed parts). This feature is extremely useful in green applications, where reducing the frequency of operation can result in considerable power savings. CyClocks Software CyClocks is an easy-to-use application that allows you to configure any one of the EPROM-programmable clocks offered by Cypress. Specify the input frequency, PLL and output frequencies, and different functional options. Note the output frequency ranges in this datasheet when specifying them in CyClocks to ensure that you stay within the limits. CyClocks also has a power calculation feature that allows you to see the power consumption of your specific configuration. CyClocks is a sub application located within the CyberClocks software. You can download a copy of CyberClocks for free on the Cypress web site at http://www.cypress.com. Cypress FTG Programmer The Cypress frequency timing generator (FTG) programmer is a portable programmer designed to custom program our family of EPROM field programmable clock devices. The FTG programmer connects to a PC serial port and allow users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670. An adapter, the CY3095, connects to the CY3670 and is required for programming the CY2292F. Custom Configuration Request Procedure The CY229x are EPROM-programmable devices that may be configured in the factory or in the field by a Cypress field application engineer (FAE). The output frequencies requested is matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submitted to your local Cypress FAE or sales representative. The method to use to request custom configurations is: Use CyClocks software. This software automatically calculates the output frequencies that can be generated by the CY229x devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. When the custom request is processed, you receive a part number with a 3-digit extension (for example, CY2292SC-128) specific to the frequencies and pinout of your device. This is the part number used for samples requests and production orders. Note 4. The CY2292 has weak pull downs on all outputs. Hence, when a tristate condition is forced on the outputs, the output pins are pulled low. Document Number: 38-07449 Rev. *M Page 4 of 19 CY2292 Storage temperature ................................ –65 C to +150 C Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Maximum soldering temperature (10 sec) ................. 260 C Junction temperature ................................................. 150 C Supply voltage .............................................–0.5 V to +7.0 V Package power dissipation ...................................... 750 mW DC input voltage ..........................................–0.5 V to +7.0 V Static discharge voltage (per MIL-STD-883, method 3015) 2000 V Operating Conditions Parameter [5] Description Part Numbers Min Max Unit VDD Supply voltage, 5.0 V operation All 4.5 5.5 V VDD Supply voltage, 3.3 V operation All 3.0 3.6 V TA Commercial operating temperature, ambient CY2292 / CY2292F 0 70 C 40 85 C Industrial operating temperature, CY2292I / CY2292FI ambient CLOAD Maximum load capacitance 5.0 V All operation – 25 pF CLOAD Maximum load capacitance 3.3 V All operation – 15 pF fREF External reference crystal All 10.0 25.0 MHz External reference clock [6, 7, 8] All 1 30 MHz Notes 5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD / 2. 7. Refer to white paper “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock. 8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended that a 150  pull up resistor to VDD be connected to the Xout pin. Document Number: 38-07449 Rev. *M Page 5 of 19 CY2292 Electrical Characteristics Commercial, 5.0 V Min Typ Max Unit VOH Parameter High level output voltage Description IOH = 4.0 mA Conditions 2.4 – – V VOL Low level output voltage IOL = 4.0 mA – – 0.4 V High level input voltage [9] Except crystal pins 2.0 – – V VIL Low level input voltage [9] Except crystal pins – – 0.8 V IIH Input high current VIN = VDD – 0.5 V – 50 MHz) – < 250 350 ps t10A Lock time for CPLL Lock time from power-up – < 25 50 ms t10B Lock time for UPLL and Lock time from power-up SPLL – < 0.25 1 ms Slew limits CY2292SI, SXI 20 – 66.6 MHz CY2292FXI, FZXI 20 – 60 MHz CPU PLL slew limits Notes 25. XBUF duty cycle depends on XTALIN duty cycle. 26. Measured at 1.4 V. 27. Measured between 0.4 V and 2.4 V. 28. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. Document Number: 38-07449 Rev. *M Page 12 of 19 CY2292 Switching Waveforms Figure 3. All Outputs, Duty Cycle and Rise / Fall Time t1 t2 Output t3 t4 Figure 4. Output Tristate Timing [29] OE t5 t6 All Tristate Outputs Figure 5. CLK Outputs Jitter and Skew t9A CLK Output t7 Related CLK Figure 6. CPU Frequency Change Select Old Select Fold New Select Stable t8 & t 10 Fnew CPU Note 29. The CY2292 has weak pull downs on all outputs. Hence, when a tristate condition is forced on the outputs, the output pins are pulled low. Document Number: 38-07449 Rev. *M Page 13 of 19 CY2292 Ordering Information Ordering Code Package Type Operating Range Operating Voltage Pb-free CY2292FXC 16-pin SOIC Commercial, 0 C to 70 C 3.3 V or 5.0 V CY2292FXCT 16-pin SOIC – Tape and Reel Commercial, 0 C to 70 C 3.3 V or 5.0 V CY2292FXI 16-pin SOIC Industrial, –40 C to 85 C 3.3 V or 5.0 V CY2292FXIT 16-pin SOIC – Tape and Reel Industrial, –40 C to 85 C 3.3 V or 5.0 V CY2292FZX 16-pin TSSOP Commercial, 0 C to 70 C 3.3 V or 5.0 V CY2292FZXT 16-pin TSSOP – Tape and Reel Commercial, 0 C to 70 C 3.3 V or 5.0 V CY2292FZXI 16-pin TSSOP Industrial, –40 C to 85 C 3.3 V or 5.0 V CY2292FZXIT 16-pin TSSOP – Tape and Reel Industrial, –40 C to 85 C 3.3 V or 5.0 V Programmer CY3670 FTG Clock Programmer CY3095 Adapter for programming the CY2292F on the CY3670 Possible Configurations Some product offerings are factory programmed customer specific devices with customized part numbers. This table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales Representative for more information. Ordering Code Package Type Operating Range Operating Voltage Pb-free CY2292SXC-xxx 16-pin SOIC Commercial, 0 C to 70 C 5.0 V CY2292SXC-xxxT 16-pin SOIC – Tape and Reel Commercial, 0 C to 70 C 5.0 V CY2292SXL-xxx 16-pin SOIC Commercial, 0 C to 70 C 3.3 V CY2292SXI-xxx 16-pin SOIC Industrial, –40 C to 85 C 3.3 V or 5.0 V CY2292SXI-xxxT 16-pin SOIC – Tape and Reel Industrial, –40 C to 85 C 3.3 V or 5.0 V Ordering Code Definitions CY 2292 X X X X - xxx X X = blank or T blank = Tube; T = Tape and Reel Custom configuration code (factory programmed device only) Temperature Range: X = C or L or I C or L = Commercial; I = industrial X = Pb-free package Package Type: X = blank or Z or S Z = 16-pin TSSOP; S or blank = 16-pin SOIC Programming: X = F or blank F = field programmable; blank = factory programmed Device part number Company ID: CY = Cypress Document Number: 38-07449 Rev. *M Page 14 of 19 CY2292 Package Characteristics JA (C/W) JC (C/W) Transistor Count 16-pin SOIC 83 19 9271 16-pin TSSOP 103 32 Package Package Diagrams Figure 7. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068 51-85068 *E Figure 8. 16-pin TSSOP 4.40 mm Body Z16.173/ZZ16.173 Package Outline, 51-85091 51-85091 *E Document Number: 38-07449 Rev. *M Page 15 of 19 CY2292 Acronyms Acronym Document Conventions Description Units of Measure CPU Central Processing Unit CMOS Complementary Metal Oxide Semiconductor °C degree Celsius DC Direct Current k kilohm EPROM Erasable Programmable Read Only Memory MHz megahertz FAE Field Application Engineer µA microampere FTG Frequency Timing Group mA milliampere OE Output Enable ms millisecond OSC Oscillator mW milliwatt PD Power Down ns nanosecond PLL Phase Locked Loop  ohm ROM Read Only Memory % percent SOIC Small Outline Integrated Circuit pF picofarad TSSOP Thin Shrunk Small Outline Package ppm parts per million Document Number: 38-07449 Rev. *M Symbol Unit of Measure ps picosecond V volt Page 16 of 19 CY2292 Document History Page Document Title: CY2292, Three-PLL General-Purpose EPROM-Programmable Clock Generator Document Number: 38-07449 Revision ECN Orig. of Change Submission Date ** 116993 DSG 07/01/02 Changed from Spec number: 38-00946 to 38-07449 *A 119639 CKN 12/05/02 Updated Operation: Updated Power Saving Features: Replaced 8 MHz with 20 MHz. *B 277130 RGL 10/26/04 Updated Ordering Information: Updated part numbers. *C 395808 RGL 09/07/05 Updated Ordering Information: No change in part numbers. Minor Change: Fixed typo in the “Package Type” column. *D 2565316 AESA / KVM 09/16/08 Updated CyClocks Software: Updated description. Updated Ordering Information: Updated part numbers. Replaced “Lead-Free” with “Pb-Free”. Added Note “Not recommended for new designs.” and referred in non Pb-free part numbers. Updated to new template. *E 2761988 KVM 09/10/09 Updated Selector Guide: Updated details in “Part Number” column. Removed the column “Outputs”. Consolidated two rows. Updated Switching Characteristics: Updated details in “Description” column (Updated part number suffixes). Updated Switching Characteristics: Updated details in “Description” column (Updated part number suffixes). Updated Switching Characteristics: Updated details in “Description” column (Updated part number suffixes). Updated Switching Characteristics: Updated details in “Description” column (Updated part number suffixes). Updated Ordering Information: No change in part numbers. Included Temperature Range values in “Operating Range” column. Minor Change: Fixed typo in the “Operating Range” column corresponding to part numbers CY2292FZXI and CY2292FZXIT. *F 2897775 KVM 03/23/10 Updated Ordering Information: Updated part numbers. Added Possible Configurations. Moved xxx parts from ordering information table to possible configurations table. Updated Package Diagrams. *G 2948137 KVM 06/09/10 Updated Pinouts: Updated Figure 1 (Updated title only (to include both SOIC and TSSOP)). Added Acronyms. *H 3010397 KVM 08/18/2010 Document Number: 38-07449 Rev. *M Description of Change Removed CY2071F related information in all instances across the document as CY2071F is obsolete. Updated Cypress FTG Programmer: Updated description. Updated Ordering Information: Updated part numbers. Added Ordering Code Definitions. Page 17 of 19 CY2292 Document History Page (continued) Document Title: CY2292, Three-PLL General-Purpose EPROM-Programmable Clock Generator Document Number: 38-07449 Revision ECN Orig. of Change Submission Date Description of Change *I 3849272 PURU 12/21/2012 Removed “Understanding the CY2291 and CY2292” application note related information in all instances across the document. Updated Package Diagrams: spec 51-85068 – Changed revision from *C to *E. spec 51-85091 – Changed revision from *C to *D. *J 4161799 CINM 10/18/2013 Updated Package Characteristics: Added JA and JC values for 16-pin TSSOP package. Updated to new template. Completing Sunset Review. *K 4576237 AJU 11/21/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Package Diagrams. *L 5495659 XHT 10/26/2016 Updated to new template. Completing Sunset Review. *M 5986795 AESATP12 12/07/2017 Updated logo and copyright. Document Number: 38-07449 Rev. *M Page 18 of 19 CY2292 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2002-2017. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-07449 Rev. *M Revised December 7, 2017 Page 19 of 19