CY25701FJXCT

CY25701JXC/FJXC Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO) and No-Spread Spectrum (XO) Option Features • Crystal Oscillator with Spread Spectrum Clock (SSXO) • No-Spread Spectrum (XO) Option • Wide operating output clock frequency range of 10–166 MHz • Programmable spread spectrum with nominal 31.5-kHz modulation frequency • Center spread: ±0.25% to ±2.0% • Down spread: –0.5% to –4.0% • No spread: ± 0.0% • Integrated phase-locked loop (PLL) • 85 ps typical cycle-to-cycle Jitter with SSCLK = 133MHz • 3.3V operation • Output Enable function • Package available in 4-pin Plastic JE • Pb-free package Benefits • Provides wide range of spread percentages for maximum electromagnetic interference (EMI) reduction, to meet regulatory agency electromagnetic compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. • This versatile programming feature enables the users to switch between SSXO (with Spread) and XO (without Spread) functions with ease. • Internal PLL to generate up to 166-MHz output. • Suitable for most PC, consumer, and networking applications • Application compatibility in standard and low-power systems • In-house programming of samples and prototype quantities is available using the CY3672 programming kit and CY3613 (JEC package) socket adapters. Production quantities are available through Cypress’ value-added distribution partners or by using third-party programmers from BP Microsystems, HiLo Systems, and others. Logic Block Diagram Pin Configuration CY25701JXC/FJXC 4-pin Plastic JE RFB PLL with MODULATION CONTROL C XIN PROGRAMMABLE CONFIGURATION C XOUT OUTPUT DIVIDERS and MUX 1 OE VDD 4 SSCLK 3 3 SSCLK 2 VSS 1 OE 4 VDD 2 VSS Cypress Semiconductor Corporation Document #: 38-07684 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 27, 2006 [+] [+] Feedback CY25701JXC/FJXC Pin Definition Pin 1 2 3 4 OE VSS SSCLK VDD Name Power supply ground. Spread spectrum clock output (with or without spread). 3.3V power supply. Description Output Enable pin: Active HIGH. If OE = 1, SSCLK is enabled. Functional Description The CY25701JXC/FJXC is a Spread Spectrum Crystal Oscillator (SSXO) IC used for the purpose of reducing EMI found in today’s high-speed digital electronic systems. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the embedded input crystal. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency (EMC) requirements and improve time-to-market without degrading system performance. The CY25701JXC/FJXC uses a programmable configuration memory array to synthesize output frequency and spread%. The spread% is programmed to either center spread or down spread with various spread percentages. The range for center spread is from ±0.25% to ±2.00%. The range for down spread is from –0.5% to –4.0%. Contact the factory for smaller or larger spread% amounts if required. Refer to Table 2 for spread selection and no-spread values. The frequency modulated SSCLK output can be programmed from 10–166 MHz. The CY25701JXC/FJXC is available in a 4-pin plastic package with operating temperature range of –20 to 70°C. Programming Description Field/Factory-Programmable CY25701JXC/FJXC Field/Factory programming is available for samples and manufacturing by Cypress and its distributors. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. Additional information on the CY25701JXC/FJXC can be obtained from the Cypress web site at www.cypress.com. Output Frequency, SSCLK Output (SSCLK, pin 3) The modulated frequency at the SSCLK output is produced by synthesizing from the embedded crystal oscillator frequency input. The range of synthesized clock is from 10–166 MHz. Spread Percentage (SSCLK, pin 3) The SSCLK spread can be programmed to various spread percentage values from ±0.25% to ±2.0% for Center Spread and from –0.5% to –4.0% for Down Spread. Refer to Table 2 for available spread options. Enter ±0.0% (No spread) for XO (Crystal Oscillator) without spread option. Frequency Modulation (SSCLK, pin 3) The frequency modulation is programmed at 31.5 kHz for all SSCLK frequencies from 10 to 166 MHz. Contact the factory if a higher-modulation frequency is required. Table 1. Programming Data Requirement Pin Function Pin Name Pin# Units Program Value Output Frequency SSCLK 3 MHz ENTER DATA Spread Percent Code[1] SSCLK 3 % ENTER DATA Frequency Modulation SSCLK 3 kHz 31.5 Table 2. Spread Percent Selection Center Spread Down Spread Code Percentage Code Percentage Note: 1. ±0.0% or Code “Z” for XO (No-Spread) option. A ±0.25% G –0.5% B ±0.5% H –1.0% C ±0.75% J –1.5% D ±1.0% K –2.0% E ±1.5% L –3.0% F ±2.0% M –4.0% Z ±0.0% Z ±0.0% Document #: 38-07684 Rev. *E Page 2 of 7 [+] [+] Feedback CY25701JXC/FJXC Absolute Maximum Rating Supply Voltage (VDD) .................................... –0.5V to +7.0V DC Input Voltage....................................–0.5V to VDD + 0.5V Storage Temperature (Non-condensing) .... –55°C to +100°C Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj = 125°C................................> 10 years Package Power Dissipation...................................... 350 mW Operating Conditions Parameter VDD TA CLOAD FSSCLK FMOD TPU Supply Voltage Ambient Temperature Max. Load Capacitance @ pin 3 SSCLK output frequency, CLOAD = 15 pF Spread Spectrum Modulation Frequency Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic) Description Min. 3.00 –20 – 10 30.0 0.05 Typ. 3.30 – – – 31.5 – Max. 3.60 70 15 166 33.0 500 Unit V °C pF MHz kHz ms DC Electrical Characteristics Parameter IOH IOL VIH VIL IIH IIL IOZ CIN[2] IVDD ∆f Description Output High Current (pin 3) Output Low Current (pin 3) Input High Voltage (pin 1) Input Low Voltage (pin 1) Input High Current (pin 1) Input Low Current (pin 1) Input Capacitance (pin 1) Supply Current Aging Condition VOH = VDD – 0.5, VDD = 3.3V (source) VOL = 0.5, VDD= 3.3V (sink) CMOS levels, 70% of VDD CMOS levels, 30% of VDD Vin = VDD Vin = VSS Pin 1, or OE VDD = 3.3V, SSCLK = 10 to 166 MHz, CLOAD = 0, OE = VDD TA = 25°C, First year Min. 10 10 0.7VDD VSS – – –10 – – –5 Typ. 12 12 – – – – – 5 – – Max. – – VDD 0.3VDD 10 10 10 7 50 5 Unit mA mA V V µA µA µA pF mA ppm Output Leakage Current (pin 3) Three-state output, OE = 0 AC Electrical Characteristics[2] Parameter DC tR tF TCCJ1[3] Description Output Duty Cycle Output Rise Time Output Fall Time Cycle-to-Cycle Jitter SSCLK (Pin 3) Condition SSCLK, Measured at VDD/2 20%–80% of VDD, CL = 15 pF 20%–80% of VDD, CL = 15 pF SSCLK ≥133 MHz, Measured at VDD/2 25 MHz ≤ SSCLK