CY25701LXCZZZT

CY25701 Programmable High Frequency Crystal Oscillator with Spread Spectrum (SSXO) and No Spread Spectrum (XO) Option Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Benefits ■ Crystal Oscillator with Spread Spectrum Clock (SSXO) No Spread Spectrum (XO) Option Wide operating output clock frequency range of 10 –166 MHz Programmable spread spectrum with nominal 31.5 kHz modulation frequency Center spread: ±0.25% to ±2.0% Down spread: –0.5% to –4.0% No spread: ± 0.0% Integrated phase-locked loop (PLL) 85 ps typical cycle-to-cycle jitter with SSCLK = 133 MHz 3.3V operation Output enable function Package available in 4-Pin ceramic LCC SMD Pb-free package Industrial temperature from –40°C to 85°C Provides a wide range of spread percentages for maximum electromagnetic interference (EMI) reduction to meet regulatory agency electromagnetic compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. This versatile programming feature enables the user to switch between SSXO (with Spread) and XO (without Spread) functions with ease. Internal PLL to generate up to 166 MHz output. Suitable for most PC, consumer, and networking applications Application compatibility in standard and low-power systems In house programming of samples and prototype quantities is available using CY3672 programming kit and CY3724 socket adapters. Production quantities are available through Cypress’ value added distribution partners or by using third party programmers from BP Microsystems, and HiLo Systems, and others. ■ ■ ■ ■ ■ Logic Block Diagram Pin Configuration CY25701 RFB 4-pin Ceramic SMD PLL with MODULATION CONTROL 4 VDD 3 SSCLK C XIN PROGRAMMABLE CONFIGURATION C XOUT OUTPUT DIVIDERS and MUX 3 SSCLK OE 1 VSS 2 1 OE 4 VDD 2 VSS Cypress Semiconductor Corporation Document Number: 001-07313 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 24, 2007 CY25701 Pin Definition Pin 1 2 3 4 OE VSS SSCLK VDD Name Power supply ground Spread spectrum clock output (with or without spread) 3.3V power supply Description Output Enable pin: Active HIGH. If OE = 1, SSCLK is enabled Functional Description The CY25701 is a Spread Spectrum Crystal Oscillator (SSXO) IC used to reduce the EMI found in today’s high speed digital electronic systems. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the embedded input crystal. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency (EMC) requirements and improve time-to-market without degrading system performance. The CY25701 uses a programmable configuration memory array to synthesize output frequency and spread%. The spread percentage is programmed to either center spread or down spread with various spread percentages. The range for center spread is from ±0.25% to ±2.00%. The range for down spread is from –0.5% to –4.0%. Contact the factory for smaller or larger spread percentage amounts if required. Refer to Table 2 for spread selection and no spread values. The frequency modulated SSCLK output is programmable from 10 to 166 MHz. The CY25701 is available in a 4-pin ceramic SMD package with an operating temperature range of –40 to 85°C. Programming Description Factory and Field Programmable CY25701 Factory and field programming is available for samples and manufacturing by Cypress and its distributors. Submit your request to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request is processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample request and the production orders. Contact your local Cypress FAE or sales representative for details. Additional information on the CY25701 is available at the Cypress web site www.cypress.com. Output Frequency, SSCLK Output (SSCLK, pin 3) The modulated frequency at the SSCLK output is produced by synthesizing from the embedded crystal oscillator frequency input. The range of synthesized clock is from 10 to 166 MHz. Spread Percentage (SSCLK, pin 3) The SSCLK spread is programmable to various spread percentage values from ±0.25% to ±2.0% for center spread and from –0.5% to –4.0% for down spread. Refer to Table 2 for available spread options. Enter ±0.0% (No spread) for XO (crystal oscillator) without spread option. Frequency Modulation (SSCLK, pin 3) The default frequency modulation is programmed at 31.5 kHz for all SSCLK frequencies from 10 to 166 MHz. Alternate frequency modulations at 30.1 kHz or 32.9 kHz are selectable using CyberClocksOnline™ software. Contact the factory for other alternate modulation frequencies if required. Table 1. Programming Data Requirement Pin Function Pin Name Pin# Units Program Value Output Frequency SSCLK 3 MHz ENTER DATA Spread Percent Code[1] SSCLK 3 % ENTER DATA Frequency Modulation SSCLK 3 kHz ENTER DATA 31.5 Note 1. ±0.0% or Code “Z” for XO (No-Spread) option. Document Number: 001-07313 Rev. *B Page 2 of 8 CY25701 Table 2. Spread Percent Selection Center Spread Down Spread Code Percentage Code Percentage A ±0.25% G –0.5% B ±0.5% H –1.0% C ±0.75% J –1.5% D ±1.0% K –2.0% E ±1.5% L –3.0% F ±2.0% M –4.0% Z ±0.0% Z ±0.0% Absolute Maximum Ratings Supply Voltage (VDD).....................................–0.5V to +7.0V DC Input Voltage ................................... –0.5V to VDD + 0.5V Storage Temperature (Non-condensing) .... –55°C to +100°C Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj = 125°C.................................>10 years Package Power Dissipation...................................... 350 mW Operating Conditions Parameter VDD TA TA CLOAD FSSCLK FMOD TPU Supply voltage Ambient temperature (commercial) Ambient temperature (industrial) Max. load capacitance @ pin 3 SSCLK output frequency, CLOAD = 15 pF Spread Spectrum Modulation Frequency Power up time for VDD to reach minimum specified voltage (power ramp must be monotonic) Description Min 3.00 –20 –40 – 10 30.0 0.05 Typ 3.30 – – – – 31.5 – Max 3.60 70 85 15 166 33.0 500 Unit V °C °C pF MHz kHz ms DC Electrical Characteristics Parameter IOH IOL VIH VIL IIH IIL IOZ CIN [2] Description Output high current (pin 3) Output low current (pin 3) Input high voltage (pin 1) Input low voltage (pin 1) Input high current (pin 1) Input low current (pin 1) Output leakage current (pin 3) Input capacitance (pin 1) Supply current Initial accuracy at room temp. Freq. stability over temp. range Aging Condition VOH = VDD – 0.5, VDD = 3.3V (source) VOL = 0.5, VDD= 3.3V (sink) CMOS levels, 70% of VDD CMOS levels, 30% of VDD Vin = VDD Vin = VSS Three-state output, OE = 0 Pin 1, or OE VDD = 3.3V, SSCLK = 10 to 166 MHz, CLOAD = 0, OE = VDD TA = 25°C, 3.3V TA = –20°C to 70°C, 3.3V TA = 25°C, First year Min 10 10 0.7VDD – – – –10 – – –25 –25 –12 –5 Typ 12 12 – – – – – 5 – – – – – Max – – VDD 0.3VDD 10 10 10 7 50 25 25 12 5 Unit mA mA V V μA μA μA pF mA ppm ppm ppm ppm IVDD Δf/f Freq. stability over voltage range 3.0 to 3.6V Document Number: 001-07313 Rev. *B Page 3 of 8 CY25701 AC Electrical Characteristics[2] Parameter DC tR tF TCCJ1[3] Description Output Duty Cycle Output Rise Time Output Fall Time Condition SSCLK, Measured at VDD/2 20%–80% of VDD, CL = 15 pF 20%–80% of VDD, CL = 15 pF 25 MHz ≤ SSCLK