S6E2HG6G0AGB3000A

The following document contains information on Cypress products. The document has the ordering part numbering with the prefix “S”. Cypress will offer these products to new and existing customers with the updated ordering part number (updated last digit). How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. S6E2H Series 32-bit ARM® Cortex®-M4F FM4 Microcontroller Devices in the S6E2H Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (CAN, UART, CSIO, I2C, LIN). The products that are described in this data sheet are placed into TYPE6-M4 product categories in the "FM4 Family Peripheral Manual Main Part (002-04856)". Features  Five clock sources (2 external oscillators, 2 internal CR  32-bit ARM Cortex-M4F Core  Up oscillator, and Main PLL) that are dynamically selectable.  Main clock: 4 MHz to 48 MHz  Sub Clock: 32.768 kHz  High-speed internal CR Clock: 4 MHz  Low-speed internal CR Clock: 100 kHz  Main PLL Clock to 160 MHz Frequency Operation  On-chip Memories  MainFlash  WorkFlash memory - Up to 512 Kbytes memory - 32 Kbytes  SRAM • SRAM0: Up to 32 Kbytes • SRAM1: Up to 16 Kbytes • SRAM2: Up to 16 Kbytes  Resets  Reset requests from INITX pin on reset  Software reset  Watchdog timers reset  Low voltage detector reset  Clock supervisor reset  Power  External Bus Interface  CAN Interface (Max 2 channels)  Multi-function Serial Interface (Max 8 channels)  Universal Asynchronous Receiver/Transmitter (UART) Synchronous Serial Interface (CSIO (SPI))  Local Interconnect Network (LIN) 2  Inter-integrated Circuit (I C)  Clock  DMA Controller (8 channels)  Clock SuperVisor (CSV)  Low-Voltage Detector (LVD)  Low-power Consumption Modes  Sleep  Timer  DSTC (Descriptor System data Transfer Controller) (256  RTC channels)  Stop  A/D Converter (Max 24 channels)  Deep standby RTC (selectable from with/without RAM retention)  Deep standby stop (selectable from with/without RAM retention) [12-bit A/D Converter]  DA Converter (Max 2 channels)  Base Timer (Max 8 channels)  Up to 100 high-speed general-purpose I/O ports @ 120 pin Package  VBAT  Debug  Serial Wire JTAG Debug Port (SWJ-DP) Trace Macrocells (ETM) provide comprehensive debug and trace facilities.  Multi-function Timer (Max 3 units)  Embedded  Real-time Clock (RTC)  Quadrature Position/Revolution Counter (QPRC) (Max 3 channels)  Unique value of the device (41-bit) is set.  Power Supplies  Wide  Dual Timer (32-/16-bit Down Counter) range voltage: supply for VBAT:  Power  Watch Counter VCC VBAT = 2.7 V to 5.5 V = 2.7 V to 5.5 V  External Interrupt Controller Unit  Watchdog Timer (2 channels)  CRC (Cyclic Redundancy Check) Accelerator  SD Card Interface Cypress Semiconductor Corporation Document Number: 001-98943 Rev.*F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 8, 2017 S6E2H Series Ecosystem for Cypress FM4 MCUs Cypress provides a wealth of data at www.cypress.com to help you to select the right MCU for your design, and to help you to quickly and effectively integrate the device into your design. Following is an abbreviated list for FM4 MCUs:  Overview: Product Portfolio, Product Roadmap  Product Selectors: FM4 MCUs  Application notes: Cypress offers a large number of FM4 application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with FM4 family of MCUs are:  AN204468 - FM4 I2S USB MP3 Player Application 32-Bit Microcontroller FM4 Family: This application note describes the general structure of the I²S USB MP3Player software example, its single modules in detail and how it is used.  AN204471 - FM4 S6E2CC Series External Memory Programmer: This document describes use of the MCU Universal Programmer as an off-line programmer for Quad SPI flash memory programming on the S6E2CC Series SK.  AN203277 - FM 32-Bit Microcontroller Family Hardware Design Considerations: This application note reviews several topics for designing a hardware system around FM0+, FM3, and FM4 family MCUs. Subjects include power system, reset, crystal, and other pin connections, and programming and debugging interfaces.  AN202488 - FM4 MB9BF56x and S6E2HG Series MCU Servo Motor Speed Control: This document covers servo motor speed control solution on FM4 MCU - MB9BF56x and S6E2H. Document Number: 001-98943 Rev.*F  AN99235 - FM4 S6E2HG Series MCU - 16-Bit PWM Using a Base Timer: Cypress FM4 Family of 32-bit ARM® Cortex®-M4 Microcontrollers FM4 S6E2H Series Motor Control ARM® Cortex®-M4 MCU  AN202487 - Differences Among FM0+, FM3, and FM4 32-Bit Microcontrollers: Highlights the peripheral differences in Cypress’s FM family MCUs. It provides dedicated sections for each peripheral and contains lists, tables, and descriptions of peripheral feature and register differences.  AN204438 - How to Setup Flash Security for FM0+, FM3 and FM4 Families: This application note describes how to setup the Flash Security for FM0+, FM3, and FM4 devices  Development kits:  FM4-U120-9B560 - ARM® Cortex®-M4 MCU Starter Kit with USB and CMSIS-DAP  FM4-216-ETHERNET ARM® Cortex®-M4 MCU Development Kit with Ethernet, CAN and USB Host  FM4-176L-S6E2CC-ETH - ARM® Cortex®-M4 MCU Starter Kit with Ethernet and USB Host  FM4-176L-S6E2GM - ARM® Cortex®-M4 MCU Pioneer Kit with Ethernet and USB Host  Peripheral Manuals Page 2 of 164 S6E2H Series Contents 1. S6E2H Series Block Diagram ................................ 4 2. Product Lineup ....................................................... 5 3. Package-Dependent Features ............................... 7 4. Detailed Product Features ..................................... 8 5. Pin Assignment .................................................... 12 6. Pin Description ..................................................... 16 6.1 List of Pin Numbers ............................................. 16 7. I/O Circuit Type ..................................................... 45 8. Handling Precautions .......................................... 52 8.1 Precautions for Product Design ........................... 52 8.2 Precautions for Package Mounting ...................... 53 8.3 Precautions for Use Environment ........................ 55 9. Handling Devices ................................................. 56 10. Memory Size ......................................................... 59 11. Memory Map ......................................................... 59 12. Pin Status in Each CPU State .............................. 62 13. Electrical Characteristics .................................... 69 13.1 Absolute Maximum Ratings ................................. 69 13.2 Recommended Operating Conditions ................. 70 13.3 DC Characteristics .............................................. 74 13.3.1 Current Rating ...................................................... 74 13.3.2 Pin Characteristics ............................................... 82 13.4 AC Characteristics ............................................... 84 13.4.1 Main Clock Input Characteristics .......................... 84 13.4.2 Sub Clock Input Characteristics ........................... 85 13.4.3 Built-in CR Oscillation Characteristics .................. 85 13.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) ............. 86 13.4.5 Operating Conditions of Main PLL (In the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) ......................................................... 86 Document Number: 001-98943 Rev.*F 13.4.6 Reset Input Characteristics .................................. 86 13.4.7 Power-on Reset Timing ........................................ 87 13.4.8 GPIO Output Characteristics ................................ 88 13.4.9 External Bus Timing ............................................. 89 13.4.10 Base Timer Input Timing ................................. 101 13.4.11 CSIO Timing ................................................... 102 13.4.12 External Input Timing ...................................... 135 13.4.13 Quadrature Position/Revolution Counter Timing................................................................. 136 13.4.14 I2C Timing ....................................................... 138 13.4.15 SD Card Interface Timing ............................... 141 13.4.16 ETM Timing..................................................... 144 13.4.17 JTAG Timing ................................................... 145 13.5 12-bit A/D Converter .......................................... 146 13.6 12-bit D/A Converter .......................................... 150 13.7 Low-Voltage Detection Characteristics .............. 151 13.7.1 Low-Voltage Detection Reset ............................. 151 13.7.2 Interrupt of Low-Voltage Detection ..................... 151 13.8 MainFlash Memory Write/Erase Characteristics .................................................... 152 13.9 WorkFlash Memory Write/Erase Characteristics .................................................... 152 13.10 Standby Recovery Time..................................... 153 13.10.1 Recovery Cause: Interrupt/WKUP .................. 153 13.10.2 Recovery Cause: Reset .................................. 155 14. Ordering Information .......................................... 157 15. Package Dimensions .......................................... 158 Worldwide Sales and Design Support....................... 164 Products ...................................................................... 164 PSoC® Solutions ......................................................... 164 Cypress Developer Community ................................. 164 Technical Support ....................................................... 164 Page 3 of 164 S6E2H Series 1. S6E2H Series Block Diagram Document Number: 001-98943 Rev.*F Page 4 of 164 S6E2H Series 2. Product Lineup Memory Size S6E2HG4 S6E2HE4 S6E2H44 S6E2H14 S6E2HG6 S6E2HE6 S6E2H46 S6E2H16 MainFlash memory 256 Kbytes 512 Kbytes WorkFlash memory 32 Kbytes 32 Kbytes On-chip SRAM 32 Kbytes 64 Kbytes SRAM0 16 Kbytes 32 Kbytes SRAM1 8 Kbytes 16 Kbytes SRAM2 8 Kbytes 16 Kbytes Product name Function Availability by Part Product Name Description S6E2HG6 S6E2HG4 S6E2HE6 S6E2HE4 S6E2H46 S6E2H44 S6E2H16 S6E2H14 Cortex-M4F, MPU, NVIC 128ch. CPU Freq. 160 MHz Power supply voltage range 2.7 V to 5.5 V CAN 2ch. (Max) N/A 2ch. (Max) DMAC 8ch. DSTC 256ch. 8ch. (Max) Base Timer (PWC/Reload timer/PWM/PPG) 8ch. (Max) MF Timer Multi-function Serial Interface (UART/CSIO/LIN/I2C) A/D activation compare 6ch. Input capture 4ch. Free-run timer 3ch. Output compare 6ch. Waveform generator 3ch. PPG 3ch. SD Card Interface QPRC 3 units (Max) 1 unit N/A 3ch. (Max) Dual Timer 1 unit Real-Time Clock 1 unit Watch Counter 1 unit Document Number: 001-98943 Rev.*F N/A Page 5 of 164 S6E2H Series Product Name Description S6E2HG6 S6E2HG4 S6E2HE6 S6E2HE4 S6E2H46 S6E2H44 CRC Accelerator Yes Watchdog Timer 1ch. (SW) + 1ch. (HW) External Interrupts 12-bit D/A Converter S6E2H16 S6E2H14 16 pins (Max) + NMI × 1 2 units (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. High-speed 4 MHz (±2%) Low-speed 100 kHz (Typ) Built-in CR Debug Function Unique ID SWJ-DP/ETM Yes Notes: − Because of package pin limitations, not all functions within the device can be brought out to external pins. You must carefully work out the pin allocation needed for your design. You must use the port relocate function of the I/O port according to your function use. − See 13.4.3 Built-in CR Oscillation Characteristics for the accuracy of the built-in CR. Document Number: 001-98943 Rev.*F Page 6 of 164 S6E2H Series 3. Package-Dependent Features The S6E2H Series of parts is available in 80-pin, 100-pin, and 120-/121-pin packages. S6E2H Description Pins count 12-bit A/D Converter I/O Ports External Bus Interface Package Suffix E0A F0A G0A 80 100 120/121 16ch. (3 units) 24ch. (3 units) 63 pins (Max) 80 pins (Max) 100 pins (Max) Addr:19-bit (Max), R/W data: 8-bit (Max), CS:5 (Max), SRAM, NOR Flash Addr:25-bit (Max), R/W data: 8-/16-bit (Max), CS:9 (Max), SRAM, NOR Flash, SDRAM Addr:25-bit (Max), R/W data: 8-/16-bit (Max), CS:9 (Max), SRAM, NOR Flash, NAND Flash, SDRAM Notes: − For an explicit list of part numbers and the feature differences among them, see 14 Ordering Information. − See 15 Package Dimensions for detailed information on each package. Document Number: 001-98943 Rev.*F Page 7 of 164 S6E2H Series 4. Detailed Product Features 32-bit ARM Cortex-M4F Core  Supports Address/Data multiplex  Up to 160 MHz Frequency Operation  Supports external RDY function  FPU built-in  Supports scramble function  Support DSP instruction  Memory Protection Unit (MPU): improves the reliability of an embedded system  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories  Flash memory These series are based on two independent on-chip Flash memories.  MainFlash memory • Up to 512 Kbytes • Built-in Flash Accelerator System with 16 Kbytes trace buffer memory • The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System. • Security function for code protection  WorkFlash memory • 32 Kbytes • Read cycle: • 6 wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz • 4 wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz • 2 wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz • 0 wait-cycle: the operation frequency up to 40 MHz • Security function is shared with code protection  SRAM This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core.  SRAM0: Up to 32 Kbytes  SRAM1: Up to 16 Kbytes  SRAM2: Up to 16 Kbytes External Bus Interface  Supports SRAM, NOR, NAND Flash and SDRAM device  Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)  8-/16-bit Data width • Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units. • Possible to set two kinds of the scramble key • Note: It is necessary to prepare the dedicated software library to use the scramble function. CAN Interface (Max 2 channels)  Compatible with CAN Specification 2.0A/B  Maximum transfer rate: 1 Mbps  Built-in 32 message buffer Multi-function Serial Interface (Max 8 channels)  64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.)  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN 2 I C  UART  Full-duplex double buffer with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)  Various error detect functions available (parity errors, framing errors, and overrun errors)  Selection  CSIO  Full-duplex double buffer dedicated baud rate generator  Overrun error detect function available  Serial chip select function (ch.6 and ch.7 only)  Supports high-speed SPI (ch.4 and ch.6 only)  Data length 5 to 16-bit  Built-in  LIN  LIN protocol Rev.2.1 supported double buffer  Master/Slave mode supported  LIN break field generation (can change to 13 to 16-bit length)  LIN break delimiter generation (can change to 1 to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors)  Full-duplex  Up to 25-bit Address bit Document Number: 001-98943 Rev.*F Page 8 of 164 S6E2H Series  I2 C  Standard mode (Max 100 kbps) / High-speed mode (Max 400 kbps) supported  Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and ch.7=ch.B) supported  16-/32-bit PWC timer  Event counter mode ( external clock mode ) General Purpose I/O Port DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously. This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.  8 independently configured and operated channels  Capable of pull-up control per pin  Transfer can be started by software or request from the  Capable of reading pin level directly DMA Controller (8 channels) built-in peripherals  Transfer address area: 32-bit (4 Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: bytes/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536  Built-in the port relocate function  Up to 100 high-speed general-purpose I/O ports @ 120 pin Package  Some pin is 5 V tolerant I/O. See 6. Pin Description and 7. I/O Circuit Type for the corresponding pins. Multi-function Timer (Max 3 units) The Multi-function timer is composed of the following blocks. DSTC (Descriptor System data Transfer Controller) (256 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation. Minimum resolution : 6.25 ns  16-bit free-run timer × 3 ch./unit  Input capture × 4 ch./unit  Output compare × 6 ch./unit  A/D activation compare × 6 ch./unit  Waveform generator × 3 ch./unit It supports the software activation, the hardware activation and the chain activation functions.  16-bit PPG timer × 3 ch./unit A/D Converter (Max 24 channels) [12-bit A/D Converter] The following function can be used to achieve the motor control.  Successive Approximation type  Built-in 3 units  Conversion time: 0.5 μs @ 5 V  Priority conversion available (priority at 2 levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function Real-time Clock (RTC)  R-2R type The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  12-bit resolution  Interrupt function with specifying date and time DA Converter (Max 2 channels) Base Timer (Max 8 channels) (Year/Month/Day/Hour/Minute.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Operation mode is selectable from the followings for each channel.  Timer interrupt function after set time or each set time.  16-bit PWM timer  Capable of rewriting the time with continuing the time count.  16-bit PPG timer  Leap year automatic count is available.  16-/32-bit reload timer Document Number: 001-98943 Rev.*F Page 9 of 164 S6E2H Series Quadrature Position/Revolution Counter (QPRC) (Max 3 channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.  The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Part E1 SDIO Specification version 3.00  Part A2 SD Host Controller Standard Specification version 3.00  1-bit or 4-bit data bus Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable.  Main clock: 4 MHz to 48 MHz  Sub Clock: 32.768 kHz  High-speed internal CR Clock: 4 MHz  Low-speed internal CR Clock: 100 kHz  Main PLL Clock  Free-running [Resets]  Periodic (=Reload)  Reset requests from INITX pin  One-shot  Power on reset Watch Counter The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source. Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz External Interrupt Controller Unit  External interrupt input pin: Max 16 pins  Both edges(Rise edge and Fall edge) detect  Include one non-maskable interrupt (NMI) Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog.  Software reset  Watchdog timers reset  Low voltage detector reset  Clock supervisor reset Clock SuperVisor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.  External OSC clock failure (clock stop) is detected, reset is asserted.  External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset. Hardware watchdog timer is clocked by low-speed internal CR oscillator. Therefore, Hardware watchdog is active in any power saving mode except Stop.  LVD1: error reporting via interrupt CRC (Cyclic Redundancy Check) Accelerator Low-power Consumption Mode The CRC accelerator helps a verify data transmission or storage integrity. Six low-power consumption modes are supported. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  Timer  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 SD Card Interface It is possible to use the SD card that conforms to the following standards.  Part 1 Physical Layer Specification version 3.01 Document Number: 001-98943 Rev.*F  LVD2: auto-reset operation  Sleep  RTC  Stop  Deep standby RTC (selectable from with/without RAM retention)  Deep standby stop (selectable from with/without RAM retention) Page 10 of 164 S6E2H Series VBAT Unique ID The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used. Unique value of the device (41-bit) is set.  RTC  Wide range voltage:  32 kHz oscillation circuit  Power supply for VBAT: VBAT = 2.7 V to 5.5 V Power Supply Two Power Supplies VCC = 2.7 V to 5.5 V  Power-on circuit  Back up register : 32 bytes  Port circuit Debug  Serial Wire JTAG Debug Port (SWJ-DP)  Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. Document Number: 001-98943 Rev.*F Page 11 of 164 S6E2H Series 5. Pin Assignment LQH080 (TOP VIEW) Document Number: 001-98943 Rev.*F Page 12 of 164 S6E2H Series LQI100 (TOP VIEW) Document Number: 001-98943 Rev.*F Page 13 of 164 S6E2H Series LQM120 (TOP VIEW) Document Number: 001-98943 Rev.*F Page 14 of 164 S6E2H Series FDI121 (TOP VIEW) Document Number: 001-98943 Rev.*F Page 15 of 164 S6E2H Series 6. 6.1 Pin Description List of Pin Numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Number Pin Name LQFP120 LQFP100 LQFP80 FBGA121 1 1 1 B1 2 2 2 C1 VCC P50 CTS4_0 AIN0_2 RTO10_0 (PPG10_0) I/O Circuit Type - Pin State Type E K E K E I E I E K - INT00_0 MADATA00_0 P51 RTS4_0 BIN0_2 3 3 3 C2 RTO11_0 (PPG10_0) INT01_0 MADATA01_0 P52 SCK4_0 (SCL4_0) 4 4 4 D1 ZIN0_2 RTO12_0 (PPG12_0) MADATA02_0 P53 TIOA1_2 5 5 5 D2 SOT4_0 (SDA4_0) RTO13_0 (PPG12_0) MADATA03_0 P54 TIOB1_2 SIN4_0 6 6 6 D3 RTO14_0 (PPG14_0) INT02_0 MADATA04_0 Document Number: 001-98943 Rev.*F Page 16 of 164 S6E2H Series Pin Number Pin Name LQFP120 LQFP100 LQFP80 FBGA121 I/O Circuit Type Pin State Type E K E K E I E K E K E I E I P55 ADTG_1 SIN6_0 7 7 7 E2 RTO15_0 (PPG14_0) INT07_2 MADATA05_0 P56 8 8 8 E3 9 - - E4 10 - - F5 11 - - F6 SOT6_0 (SDA6_0) DTTI1X_0 INT08_2 MADATA06_0 P57 SCK6_0 (SCL6_0) MADATA07_0 RTO20_1 P58 SIN4_2 AIN1_0 INT04_2 MADATA08_0 RTO21_1 P59 SOT4_2 (SDA4_2) BIN1_0 INT07_1 MADATA09_0 RTO22_1 RX1_1 P5A SCK4_2 (SCL4_2) 12 - - G5 13 - - G6 Document Number: 001-98943 Rev.*F ZIN1_0 MADATA10_0 RTO23_1 TX1_1 P5B CTS4_2 MADATA11_0 RTO24_1 Page 17 of 164 S6E2H Series Pin Number Pin Name LQFP120 LQFP100 LQFP80 FBGA121 14 9 9 14 15 9 9 10 10 15 16 16 17 17 18 18 19 19 E1 E1 F4 10 10 11 11 - - 12 12 - - 13 - - - 14 - - - Document Number: 001-98943 Rev.*F F4 F3 F3 F2 F2 F1 F1 G1 G1 P30 TIOB0_1 RTS4_2 INT15_2 WKUP1 MADATA07_0 MADATA12_0 RTO25_1 P31 TIOB1_1 SIN3_1 INT09_2 MADATA08_0 MADATA13_0 DTTI2X_1 P32 TIOB2_1 SOT3_1 (SDA3_1) I/O Circuit Type Pin State Type E Q I K N K N K E I E K INT10_1 MADATA09_0 MADATA14_0 P33 ADTG_6 TIOB3_1 SCK3_1 (SCL3_1) INT04_0 MADATA10_0 MADATA15_0 P34 TIOB4_1 FRCK0_0 TX0_1 MADATA11_0 MNALE_0 P35 TIOB5_1 IC03_0 INT08_1 RX0_1 MADATA12_0 MNCLE_0 Page 18 of 164 S6E2H Series Pin Number LQFP120 20 20 21 21 22 LQFP100 LQFP80 15 - - - 16 - - - 17 - - 23 Pin Name FBGA121 G2 G2 G3 G3 G4 - 18 13 H1 - 24 19 14 H2 - 25 20 15 H3 - 26 21 16 H4 - 27 22 17 P36 SIN5_2 IC02_0 INT09_1 MADATA13_0 MNWEX_0 P37 I/O Circuit Type Pin State Type E K E K E K L I G I G I G I G I SOT5_2 (SDA5_2) IC01_0 INT05_2 MADATA14_0 MNREX_0 P38 SCK5_2 (SCL5_2) IC00_0 INT06_2 MADATA15_0 P39 ADTG_2 DTTI0X_0 RTCCO_2 SUBOUT_2 MSDCLK_0 P3A TIOA0_1 AIN0_0 RTO00_0 (PPG00_0) MSDCKE_0 P3B TIOA1_1 BIN0_0 RTO01_0 (PPG00_0) MRASX_0 P3C TIOA2_1 ZIN0_0 RTO02_0 (PPG02_0) MCASX_0 P3D TIOA3_1 J1 RTO03_0 (PPG02_0) MAD00_0 Document Number: 001-98943 Rev.*F Page 19 of 164 S6E2H Series Pin Number LQFP120 LQFP100 LQFP80 Pin Name FBGA121 I/O Circuit Type Pin State Type G I G I - - G K G K G I G I R J R J B C P3E TIOA4_1 28 23 18 J2 RTO04_0 (PPG04_0) MAD01_0 P3F TIOA5_1 29 24 19 K2 30 31 25 26 20 - L1 K1 32 27 - L2 33 28 - J3 RTO05_0 (PPG04_0) MAD02_0 VSS VCC P40 TIOA0_0 RTO10_1 (PPG10_1) INT12_1 P41 TIOA1_0 RTO11_1 (PPG10_1) INT13_1 AIN2_0 P42 TIOA2_0 34 29 - J5 RTO12_1 (PPG12_1) MSDWEX_0 BIN2_0 P43 ADTG_7 TIOA3_0 35 30 - H5 RTO13_1 (PPG12_1) MCSX8_0 ZIN2_0 P44 TIOA4_0 36 31 21 K3 RTO14_1 (PPG14_1) DA0 P45 TIOB0_0 37 38 32 33 22 23 Document Number: 001-98943 Rev.*F J4 L3 RTO15_1 (PPG14_1) DA1 INITX Page 20 of 164 S6E2H Series Pin Number Pin Name LQFP120 LQFP100 LQFP80 FBGA121 39 34 24 L4 40 35 25 K4 41 36 26 K5 42 37 27 K6 43 44 45 46 38 39 40 41 28 29 30 31 L5 L6 L7 K7 47 42 32 J6 48 43 33 J7 P46 X0A P47 X1A P48 VREGCTL P49 VWAKEUP VBAT C VSS VCC P4B TIOB1_0 SCS7_1 MAD03_0 P4C TIOB2_0 SCK7_1 (SCL7_1) I/O Circuit Type Pin State Type P S Q T O U O U - - E I N I N K I Q E I AIN1_2 MAD04_0 P4D TIOB3_0 49 50 44 45 34 35 J8 K8 SOT7_1 (SDA7_1) BIN1_2 INT13_2 MAD05_0 P4E TIOB4_0 SIN7_1 ZIN1_2 FRCK1_1 INT11_1 WKUP2 MAD06_0 P70 TIOA4_2 51 - - H6 AIN0_1 IC13_1 TX0_0 Document Number: 001-98943 Rev.*F Page 21 of 164 S6E2H Series Pin Number LQFP120 LQFP100 LQFP80 Pin Name FBGA121 52 - - H7 53 - - G7 54 - - H8 P71 TIOB4_2 BIN0_1 IC12_1 INT15_1 RX0_0 P72 TIOA6_0 SIN2_0 ZIN0_1 IC11_1 INT14_2 P73 TIOB6_0 SOT2_0 (SDA2_0) I/O Circuit Type Pin State Type E K E K E K E I C E J D A A A B - - F M F L IC10_1 INT03_2 P74 55 - - J9 56 46 36 L8 57 47 37 K9 58 48 38 L9 59 49 39 L10 60 61 50 51 40 - L11 K11 SCK2_0 (SCL2_0) DTTI1X_1 PE0 MD1 MD0 PE2 X0 PE3 X1 VSS VCC P10 AN00 62 52 41 J10 SIN1_1 FRCK0_2 INT02_1 MAD07_0 RX1_2 P11 AN01 SOT1_1 (SDA1_1) 63 53 42 H10 IC00_2 MAD08_0 TX1_2 Document Number: 001-98943 Rev.*F Page 22 of 164 S6E2H Series Pin Number LQFP120 LQFP100 LQFP80 Pin Name FBGA121 I/O Circuit Type Pin State Type F L F M F L F L F M F P - - P12 AN02 64 54 43 H9 65 55 44 G10 66 56 45 G9 SCK1_1 (SCL1_1) IC01_2 RTCCO_1 SUBOUT_1 MAD09_0 P13 AN03 SIN0_1 IC02_2 INT03_1 MAD10_0 P14 AN04 SOT0_1 (SDA0_1) IC03_2 MAD11_0 P15 AN05 67 68 57 58 46 47 G8 F10 69 59 48 F9 70 71 72 73 60 61 62 63 49 50 51 52 J11 H11 G11 F11 Document Number: 001-98943 Rev.*F SCK0_1 (SCL0_1) MAD12_0 ZIN2_2 RTO22_0 P16 AN06 SIN2_2 INT14_1 MAD13_0 BIN2_2 RTO21_0 P17 AN07 SOT2_2 (SDA2_2) WKUP3 MAD14_0 AIN2_2 RTO20_0 AVCC AVSS AVRL AVRH Page 23 of 164 S6E2H Series Pin Number LQFP120 LQFP100 LQFP80 Pin Name FBGA121 I/O Circuit Type Pin State Type P18 AN08 74 64 53 F8 SCK2_2 (SCL2_2) F L F M M L M L F L F L F L E I 75 65 54 E11 MAD15_0 DTTI2X_0 P19 AN09 SIN4_1 IC00_1 INT05_1 MAD16_0 P1A AN10 76 66 55 E10 SOT4_1 (SDA4_1) IC01_1 MAD17_0 P1B AN11 77 67 56 E9 78 68 - E8 79 69 - D10 80 70 - D9 81 - - F7 SCK4_1 (SCL4_1) IC02_1 MAD18_0 P1C AN12 CTS4_1 IC03_1 MAD19_0 P1D AN13 RTS4_1 DTTI0X_1 MAD20_0 P1E AN14 ADTG_5 FRCK0_1 MAD21_0 P1F ADTG_4 TIOB6_2 RTO05_1 (PPG04_1) Document Number: 001-98943 Rev.*F Page 24 of 164 S6E2H Series Pin Number LQFP120 LQFP100 LQFP80 Pin Name FBGA121 I/O Circuit Type Pin State Type E K E I E I E K F L F L F M P27 TIOA6_2 82 - - E7 RTO04_1 (PPG04_1) INT02_2 P26 TIOB5_0 83 - - D8 SCK2_1 (SCL2_1) RTO03_1 (PPG02_1) P25 TIOA5_0 84 - - C9 SOT2_1 (SDA2_1) RTO02_1 (PPG02_1) TX1_0 P24 SIN2_1 85 - - B10 RTO01_1 (PPG00_1) INT01_2 RX1_0 P23 AN15 TIOA7_1 86 71 57 D11 SCK0_0 (SCL0_0) RTO00_1 (PPG00_1) - 58 87 72 C10 58 59 88 73 59 59 Document Number: 001-98943 Rev.*F C11 MAD22_0 P22 CROUT_0 AN16 TIOB7_1 SOT0_0 (SDA0_0) ZIN1_1 RTO23_0 P21 AN17 SIN0_0 BIN1_1 INT06_1 MAD23_0 RTO24_0 Page 25 of 164 S6E2H Series Pin Number LQFP120 LQFP100 LQFP80 Pin Name FBGA121 89 74 - B11 90 91 75 76 60 61 A11 A10 92 77 62 B9 93 78 63 A9 P20 AN18 AIN1_1 INT05_0 MAD24_0 RTO25_0 VSS VCC P0E TIOB5_2 SCS6_1 IC13_0 S_CLK_0 MDQM1_0 P0D TIOA5_2 SCK6_1 (SCL6_1) I/O Circuit Type Pin State Type F M - - L I L I L I L K L K IC12_0 S_CMD_0 MDQM0_0 P0C TIOA6_1 94 95 79 80 64 65 C8 B8 SOT6_1 (SDA6_1) IC11_0 S_DATA1_0 MALE_0 P0B TIOB6_1 SIN6_1 IC10_0 INT00_1 S_DATA0_0 MCSX0_0 P0A SIN1_0 FRCK1_0 96 81 66 A8 INT12_2 S_DATA3_0 MCSX1_0 Document Number: 001-98943 Rev.*F Page 26 of 164 S6E2H Series Pin Number LQFP120 LQFP100 LQFP80 Pin Name FBGA121 82 D7 67 98 99 100 83 84 85 - - - C7 B7 A7 101 86 - D6 102 87 68 B6 103 88 69 C6 Document Number: 001-98943 Rev.*F Pin State Type M N F N M N F N F O E G E G P09 AN19 TRACED0 TIOA3_2 67 97 I/O Circuit Type SOT1_0 (SDA1_0) S_DATA2_0 MCSX5_0 IC23_1 P08 AN20 TRACED1 TIOB3_2 SCK1_0 (SCL1_0) MCSX4_0 IC22_1 P07 AN21 TRACED2 TIOA0_2 SCK7_0 (SCL7_0) MCLKOUT_0 IC21_1 P06 AN22 TRACED3 TIOB0_2 SOT7_0 (SDA7_0) MCSX3_0 IC20_1 P05 AN23 ADTG_0 TRACECLK SIN7_0 INT01_1 MCSX2_0 FRCK2_1 P04 TDO SWO P03 TMS SWDIO Page 27 of 164 S6E2H Series Pin Number Pin Name LQFP120 LQFP100 LQFP80 FBGA121 104 89 70 C5 105 90 71 B5 106 91 72 A5 107 92 - A6 108 - - E6 109 - - E5 110 - - D5 111 - - D4 112 - - C4 P02 TDI MCSX6_0 P01 TCK SWCLK P00 TRSTX MCSX7_0 VSS P68 TIOB7_2 SCK3_0 (SCL3_0) INT00_2 P67 TIOA7_2 SOT3_0 (SDA3_0) P66 ADTG_8 SIN3_0 INT11_2 P65 TIOB7_0 SCK5_1 (SCL5_1) P64 TIOA7_0 SOT5_1 (SDA5_1) I/O Circuit Type Pin State Type E H E G E H - - E K E I E K E I E K E K INT10_2 P63 93 73 CROUT_1 - - 113 SIN5_1 B4 INT03_0 S_CD_0 93 73 MWEX_0 IC23_0 RX0_2 Document Number: 001-98943 Rev.*F Page 28 of 164 S6E2H Series Pin Number LQFP120 114 LQFP100 94 LQFP80 74 Pin Name I/O Circuit Type Pin State Type P62 ADTG_3 SIN5_0 INT04_1 S_WP_0 MOEX_0 IC22_0 TX0_2 I K E I I F - - E *1 I E *1 I - - FBGA121 C3 P61 TIOB2_2 115 95 75 B3 SOT5_0 (SDA5_0) RTCCO_0 SUBOUT_0 ZIN2_1 P60 TIOA2_2 116 96 76 B2 117 97 77 A4 118 98 78 A3 119 99 79 A2 120 100 80 *1 without pullup control register A1 K10 Document Number: 001-98943 Rev.*F SCK5_0 (SCL5_0) NMIX WKUP0 MRDY_0 FRCK2_0 VCC P80 BIN2_1 IC21_0 P81 AIN2_1 IC20_0 VSS VSS Page 29 of 164 S6E2H Series List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Function ADC Base Timer 0 Base Timer 1 Base Timer 2 Pin Name ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 Function Description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Document Number: 001-98943 Rev.*F LQFP 120 101 7 23 114 81 80 17 35 110 62 63 64 65 66 67 68 69 74 75 76 77 78 79 80 86 87 88 89 97 98 99 100 101 32 24 99 37 14 100 33 25 5 47 15 6 34 26 116 48 16 115 Pin No LQFP LQFP 100 80 86 7 7 18 13 94 74 70 12 12 30 52 41 53 42 54 43 55 44 56 45 57 46 58 47 59 48 64 53 65 54 66 55 67 56 68 69 70 71 57 72 58 73 59 74 82 67 83 84 85 86 27 19 14 84 32 22 9 9 85 28 20 15 5 5 42 32 10 10 6 6 29 21 16 96 76 43 33 11 11 95 75 FBGA 121 D6 E2 H1 C3 F7 D9 F2 H5 D5 J10 H10 H9 G10 G9 G8 F10 F9 F8 E11 E10 E9 E8 D10 D9 D11 C10 C11 B11 D7 C7 B7 A7 D6 L2 H2 B7 J4 E1 A7 J3 H3 D2 J6 F4 D3 J5 H4 B2 J7 F3 B3 Page 30 of 164 S6E2H Series Pin Function Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Pin Name TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 TIOA4_2 TIOB4_0 TIOB4_1 TIOB4_2 TIOA5_0 TIOA5_1 TIOA5_2 TIOB5_0 TIOB5_1 TIOB5_2 TIOA6_0 TIOA6_1 TIOA6_2 TIOB6_0 TIOB6_1 TIOB6_2 Function Description Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin TIOA7_0 FBGA 121 H5 J1 D7 J8 F2 C7 K3 J2 H6 K8 F1 H7 C9 K2 A9 D8 G1 B9 G7 C8 E7 H8 B8 F7 - - C4 86 71 57 D11 TIOA7_2 109 - - E5 TIOB7_0 111 - - D4 87 72 58 C10 108 - - E6 105 90 71 B5 103 88 69 C6 102 105 104 102 103 101 97 98 99 100 106 87 90 89 87 88 86 82 83 84 85 91 68 71 70 68 69 72 B6 B5 C5 B6 C6 D6 D7 C7 B7 A7 A5 TIOB7_1 Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin TIOB7_2 SWCLK SWDIO Debugger Pin No LQFP LQFP 100 80 30 22 17 82 67 44 34 12 12 83 31 21 23 18 45 35 13 24 19 78 63 14 77 62 79 64 80 65 - 112 TIOA7_1 Base Timer 7 LQFP 120 35 27 97 49 17 98 36 28 51 50 18 52 84 29 93 83 19 92 53 94 82 54 95 81 SWO TCK TDI TDO TMS TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TRSTX Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin JTAG test clock input pin JTAG test data input pin JTAG debug data output pin JTAG test mode state input/output pin Trace CLK output pin of ETM Trace data output pin of ETM JTAG test reset Input pin Document Number: 001-98943 Rev.*F Page 31 of 164 S6E2H Series Pin Function Pin Name External Bus MAD00_0 MAD01_0 MAD02_0 MAD03_0 MAD04_0 MAD05_0 MAD06_0 MAD07_0 MAD08_0 MAD09_0 MAD10_0 MAD11_0 MAD12_0 MAD13_0 MAD14_0 MAD15_0 MAD16_0 MAD17_0 MAD18_0 MAD19_0 MAD20_0 MAD21_0 MAD22_0 MAD23_0 MAD24_0 Function Description External bus interface address bus Document Number: 001-98943 Rev.*F LQFP 120 27 28 29 47 48 49 50 62 63 64 65 66 67 68 69 74 75 76 77 78 79 80 86 88 89 Pin No LQFP LQFP 100 80 22 17 23 18 24 19 42 32 43 33 44 34 45 35 52 41 53 42 54 43 55 44 56 45 57 46 58 47 59 48 64 53 65 54 66 55 67 56 68 69 70 71 73 74 - FBGA 121 J1 J2 K2 J6 J7 J8 K8 J10 H10 H9 G10 G9 G8 F10 F9 F8 E11 E10 E9 E8 D10 D9 D11 C11 B11 Page 32 of 164 S6E2H Series Pin Function External Bus Pin Name MCSX0_0 MCSX1_0 MCSX2_0 MCSX3_0 MCSX4_0 MCSX5_0 MCSX6_0 MCSX7_0 MCSX8_0 MADATA00_0 MADATA01_0 MADATA02_0 MADATA03_0 MADATA04_0 MADATA05_0 MADATA06_0 MADATA07_0 MADATA08_0 MADATA09_0 MADATA10_0 MADATA11_0 MADATA12_0 MADATA13_0 MADATA14_0 MADATA15_0 MDQM0_0 MDQM1_0 MALE_0 MRDY_0 MCLKOUT_0 MNALE_0 MNCLE_0 MNREX_0 MNWEX_0 MOEX_0 MWEX_0 MSDCLK_0 MSDCKE_0 External Bus MRASX_0 MCASX_0 MSDWEX_0 Function Description External bus interface chip select output pin External bus interface data bus (Address / data multiplex bus) External bus interface byte mask signal output pin External bus interface Address Latch enable output signal for multiplex External bus interface external RDY input signal External bus interface external clock output pin External bus interface ALE signal to control NAND Flash output pin External bus interface CLE signal to control NAND Flash output pin External bus interface read enable signal to control NAND Flash External bus interface write enable signal to control NAND Flash External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM SDRAM interface SDRAM clock output pin SDRAM interface SDRAM clock enable pin SDRAM interface SDRAM row address strobe pin SDRAM interface SDRAM column address strobe pin SDRAM interface SDRAM write enable pin Document Number: 001-98943 Rev.*F LQFP 120 95 96 101 100 98 97 104 106 35 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 93 92 Pin No LQFP LQFP 100 80 80 65 81 66 86 85 83 82 67 89 70 91 72 30 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 14 15 16 17 78 63 77 62 FBGA 121 B8 A8 D6 A7 C7 D7 C5 A5 H5 C1 C2 D1 D2 D3 E2 E3 E4 F5 F6 G5 G6 E1 F4 F3 F2 A9 B9 94 79 64 C8 116 96 76 B2 99 84 - B7 18 - - F1 19 - - G1 21 - - G3 20 - - G2 114 94 74 C3 113 93 73 B4 23 18 - H1 24 19 - H2 25 20 - H3 26 21 - H4 34 29 - J5 Page 33 of 164 S6E2H Series Pin Function Pin Name External Interrupt INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT01_2 INT02_0 INT02_1 INT02_2 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 INT05_2 INT06_1 INT06_2 INT07_1 INT07_2 INT08_1 INT08_2 INT09_1 INT09_2 INT10_1 INT10_2 INT11_1 INT11_2 INT12_1 INT12_2 INT13_1 INT13_2 INT14_1 INT14_2 INT15_1 INT15_2 External Interrupt NMIX Function Description External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin Document Number: 001-98943 Rev.*F LQFP 120 2 95 108 3 101 85 6 62 82 113 65 54 17 114 10 89 75 21 88 22 11 7 19 8 20 15 16 112 50 110 32 96 33 49 68 53 52 14 116 Pin No LQFP LQFP 100 80 2 2 80 65 3 3 86 6 6 52 41 93 73 55 44 12 12 94 74 74 65 54 16 73 59 17 7 7 14 8 8 15 10 10 11 11 45 35 27 81 66 28 44 34 58 47 9 9 96 76 FBGA 121 C1 B8 E6 C2 D6 B10 D3 J10 E7 B4 G10 H8 F2 C3 F5 B11 E11 G3 C11 G4 F6 E2 G1 E3 G2 F4 F3 C4 K8 D5 L2 A8 J3 J8 F10 G7 H7 E1 B2 Page 34 of 164 S6E2H Series Pin Function Pin Name GPIO P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F P20 P21 P22 P23 P24 P25 P26 P27 Function Description General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 Document Number: 001-98943 Rev.*F LQFP 120 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 62 63 64 65 66 67 68 69 74 75 76 77 78 79 80 81 89 88 87 86 85 84 83 82 Pin No LQFP LQFP 100 80 91 72 90 71 89 70 88 69 87 68 86 85 84 83 82 67 81 66 80 65 79 64 78 63 77 62 52 41 53 42 54 43 55 44 56 45 57 46 58 47 59 48 64 53 65 54 66 55 67 56 68 69 70 74 73 59 72 58 71 57 - FBGA 121 A5 B5 C5 C6 B6 D6 A7 B7 C7 D7 A8 B8 C8 A9 B9 J10 H10 H9 G10 G9 G8 F10 F9 F8 E11 E10 E9 E8 D10 D9 F7 B11 C11 C10 D11 B10 C9 D8 E7 Page 35 of 164 S6E2H Series Pin Function Pin Name GPIO P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P5A P5B Function Description General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 Document Number: 001-98943 Rev.*F LQFP 120 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 37 39 40 41 42 47 48 49 50 2 3 4 5 6 7 8 9 10 11 12 13 Pin No LQFP LQFP 100 80 9 9 10 10 11 11 12 12 13 14 15 16 17 18 13 19 14 20 15 21 16 22 17 23 18 24 19 27 28 29 30 31 21 32 22 34 24 35 25 36 26 37 27 42 32 43 33 44 34 45 35 2 2 3 3 4 4 5 5 6 6 7 7 8 8 - FBGA 121 E1 F4 F3 F2 F1 G1 G2 G3 G4 H1 H2 H3 H4 J1 J2 K2 L2 J3 J5 H5 K3 J4 L4 K4 K5 K6 J6 J7 J8 K8 C1 C2 D1 D2 D3 E2 E3 E4 F5 F6 G5 G6 Page 36 of 164 S6E2H Series Pin Function GPIO Pin Name P60 P61 P62 P63 P64 P65 P66 P67 P68 P70 P71 P72 P73 P74 P80 P81 PE0 PE2 PE3 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) Multifunction Serial 0 SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) SIN1_0 SIN1_1 SOT1_0 (SDA1_0) Multifunction Serial 1 SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) Function Description LQFP 120 116 115 114 113 General-purpose I/O port 6 112 111 110 109 108 51 52 General-purpose I/O port 7 53 54 55 118 General-purpose I/O port 8 119 56 General-purpose I/O port E 58 59 88 Multi-function serial interface ch.0 input pin 65 Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I2C (operation mode 4). Document Number: 001-98943 Rev.*F Pin No LQFP LQFP 100 80 96 76 95 75 94 74 93 73 98 78 99 79 46 36 48 38 49 39 73 59 55 44 FBGA 121 B2 B3 C3 B4 C4 D4 D5 E5 E6 H6 H7 G7 H8 J9 A3 A2 L8 L9 L10 C11 G10 87 72 58 C10 66 56 45 G9 86 71 57 D11 67 57 46 G8 96 62 81 52 66 41 A8 J10 97 82 67 D7 63 53 42 H10 98 83 - C7 64 54 43 H9 Page 37 of 164 S6E2H Series Pin Function Multifunction Serial 2 Pin Name SIN2_0 SIN2_1 SIN2_2 SOT2_0 (SDA2_0) SOT2_1 (SDA2_1) SOT2_2 (SDA2_2) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) SCK2_2 (SCL2_2) SIN3_0 SIN3_1 SOT3_0 (SDA3_0) Multifunction Serial 3 SOT3_1 (SDA3_1) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) Multifunction Serial 4 SIN4_0 SIN4_1 SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SOT4_2 (SDA4_2) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) CTS4_0 CTS4_1 CTS4_2 RTS4_0 RTS4_1 RTS4_2 Function Description LQFP 120 53 Multi-function serial interface ch.2 input pin 85 68 Multi-function serial interface ch.2 output 54 pin. This pin operates as SOT2 when it is used 84 in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C 69 (operation mode 4). Multi-function serial interface ch.2 clock I/O 55 pin. This pin operates as SCK2 when it is used 83 in a CSIO (operation modes 2) and as SCL2 when it is used in an I2C (operation 74 mode 4). 110 Multi-function serial interface ch.3 input pin 15 Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 input pin Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 CTS input pin Multi-function serial interface ch.4 RTS output pin Document Number: 001-98943 Rev.*F Pin No LQFP LQFP 100 80 58 47 FBGA 121 G7 B10 F10 - - H8 - - C9 59 48 F9 - - J9 - - D8 64 53 F8 10 10 D5 F4 109 - - E5 16 11 11 F3 108 - - E6 17 12 12 F2 6 75 10 6 65 - 6 54 - D3 E11 F5 5 5 5 D2 76 66 55 E10 11 - - F6 4 4 4 D1 77 67 56 E9 12 - - G5 2 78 13 3 79 14 2 68 3 69 9 2 3 9 C1 E8 G6 C2 D10 E1 Page 38 of 164 S6E2H Series Pin Function Multifunction Serial 5 Pin Name SIN5_0 SIN5_1 SIN5_2 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) SCK5_2 (SCL5_2) SIN6_0 SIN6_1 SOT6_0 (SDA6_0) Multifunction Serial 6 SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) LQFP 120 114 Multi-function serial interface ch.5 input pin 113 20 Multi-function serial interface ch.5 output 115 pin. This pin operates as SOT5 when it is used 112 in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C 21 (operation mode 4). Multi-function serial interface ch.5 clock I/O 116 pin. This pin operates as SCK5 when it is used 111 in a CSIO (operation modes 2) and as SCL5 when it is used in an I2C (operation 22 mode 4). 7 Multi-function serial interface ch.6 input pin 95 Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I2C (operation mode 4). Pin No LQFP LQFP 100 80 94 74 15 - FBGA 121 C3 B4 G2 95 75 B3 - - C4 16 - G3 96 76 B2 - - D4 17 - G4 7 80 7 65 E2 B8 8 8 8 E3 94 79 64 C8 9 - - E4 93 78 63 A9 SCS6_1 Multi-function serial interface ch.6 serial chip select pin 92 77 62 B9 SIN7_0 SIN7_1 Multi-function serial interface ch.7 input pin 101 50 86 45 35 D6 K8 100 85 - A7 49 44 34 J8 99 84 - B7 48 43 33 J7 47 42 32 J6 SOT7_0 (SDA7_0) SOT7_1 (SDA7_1) Multifunction Serial 7 Function Description SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) SCS7_1 Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation modes 2) and as SCL7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 serial chip select pin Document Number: 001-98943 Rev.*F Page 39 of 164 S6E2H Series Pin Function Pin Name DTTI0X_0 DTTI0X_1 Multifunction Timer 0 FRCK0_0 FRCK0_1 FRCK0_2 IC00_0 IC00_1 IC00_2 IC01_0 IC01_1 IC01_2 IC02_0 IC02_1 IC02_2 IC03_0 IC03_1 IC03_2 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) RTO04_0 (PPG04_0) RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) RTO05_1 (PPG04_1) Function Description Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. 16-bit free-run timer ch.0 external clock input pin 16-bit input capture ch.0 input pin of Multi-function timer 0. ICxx describes channel number. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Document Number: 001-98943 Rev.*F LQFP 120 Pin No LQFP LQFP 100 80 FBGA 121 23 18 13 H1 79 69 - D10 18 80 62 22 75 63 21 76 64 20 77 65 19 78 66 13 70 52 17 65 53 16 66 54 15 67 55 14 68 56 41 54 42 55 43 56 44 45 F1 D9 J10 G4 E11 H10 G3 E10 H9 G2 E9 G10 G1 E8 G9 24 19 14 H2 86 71 57 D11 25 20 15 H3 85 - - B10 26 21 16 H4 84 - - C9 27 22 17 J1 83 - - D8 28 23 18 J2 82 - - E7 29 24 19 K2 81 - - F7 Page 40 of 164 S6E2H Series Pin Function Pin Name DTTI1X_0 Function Description Pin No LQFP LQFP 100 80 FBGA 121 8 8 8 E3 55 - - J9 96 81 66 A8 50 45 35 K8 IC10_0 95 80 65 B8 IC10_1 54 - - H8 IC11_0 94 79 64 C8 53 - - G7 93 78 63 A9 IC12_1 52 - - H7 IC13_0 92 77 62 B9 IC13_1 51 - - H6 2 2 2 C1 32 27 - L2 3 3 3 C2 33 28 - J3 4 4 4 D1 34 29 - J5 5 5 5 D2 35 30 - H5 6 6 6 D3 36 31 21 K3 7 7 7 E2 37 32 22 J4 DTTI1X_1 FRCK1_0 FRCK1_1 Input signal controlling wave form generator outputs RTO10 to RTO15 of Multi-function timer 1. 16-bit free-run timer ch.1 external clock input pin IC11_1 IC12_0 Multi- function Timer 1 LQFP 120 RTO10_0 (PPG10_0) RTO10_1 (PPG10_1) RTO11_0 (PPG10_0) RTO11_1 (PPG10_1) RTO12_0 (PPG12_0) RTO12_1 (PPG12_1) RTO13_0 (PPG12_0) RTO13_1 (PPG12_1) RTO14_0 (PPG14_0) RTO14_1 (PPG14_1) 16-bit input capture ch.1 input pin of Multi-function timer 1. ICxx describes channel number. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. RTO15_0 Wave form generator output pin of (PPG14_0) Multi-function timer 1. RTO15_1 This pin operates as PPG14 when it is (PPG14_1) used in PPG1 output modes. Document Number: 001-98943 Rev.*F Page 41 of 164 S6E2H Series Pin Function Pin Name DTTI2X_0 DTTI2X_1 Multi- function Timer 2 Quadrature Position/ Revolution Counter 0 FRCK2_0 FRCK2_1 IC20_0 IC20_1 IC21_0 IC21_1 IC22_0 IC22_1 IC23_0 IC23_1 RTO20_0 (PPG20_0) RTO20_1 (PPG20_1) RTO21_0 (PPG20_0) RTO21_1 (PPG20_1) RTO22_0 (PPG22_0) RTO22_1 (PPG22_1) RTO23_0 (PPG22_0) RTO23_1 (PPG22_1) RTO24_0 (PPG24_0) RTO24_1 (PPG24_1) RTO25_0 (PPG24_0) RTO25_1 (PPG24_1) AIN0_0 AIN0_1 AIN0_2 BIN0_0 BIN0_1 BIN0_2 ZIN0_0 ZIN0_1 ZIN0_2 Function Description LQFP 120 Pin No LQFP LQFP 100 80 FBGA 121 Input signal controlling wave form generator outputs RTO20 to RTO25 of Multi-function timer 2. 74 64 53 F8 15 10 10 F4 16-bit free-run timer ch.2 external clock input pin 116 101 119 100 118 99 114 98 113 97 96 86 99 85 98 84 94 83 93 82 76 79 78 74 73 67 B2 D6 A2 A7 A3 B7 C3 C7 B4 D7 69 59 48 F9 9 - - E4 68 58 47 F10 10 - - F5 67 57 46 G8 11 - - F6 87 72 58 C10 12 - - G5 88 73 59 C11 13 - - G6 89 74 - B11 14 9 9 E1 24 51 2 25 52 3 26 53 4 19 2 20 3 21 4 14 2 15 3 16 4 H2 H6 C1 H3 H7 C2 H4 G7 D1 16-bit input capture ch.2 input pin of Multi-function timer 2. ICxx describes channel number. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG10 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin QPRC ch.0 ZIN input pin Document Number: 001-98943 Rev.*F Page 42 of 164 S6E2H Series Pin Function Quadrature Position/ Revolution Counter 1 Quadrature Position/ Revolution Counter 2 Real-time clock Pin Name AIN1_0 AIN1_1 AIN1_2 BIN1_0 BIN1_1 BIN1_2 ZIN1_0 ZIN1_1 ZIN1_2 AIN2_0 AIN2_1 AIN2_2 BIN2_0 BIN2_1 BIN2_2 ZIN2_0 ZIN2_1 ZIN2_2 RTCCO_0 RTCCO_1 RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 Function Description QPRC ch.1 AIN input pin QPRC ch.1 BIN input pin QPRC ch.1 ZIN input pin QPRC ch.2 AIN input pin QPRC ch.2 BIN input pin QPRC ch.2 ZIN input pin 0.5 seconds pulse output pin of Real-time clock Sub clock output pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin WKUP1 1 Deep standby mode return signal input pin WKUP2 2 Deep standby mode return signal input pin WKUP3 3 DA0 D/A converter ch.0 analog output pin DA1 D/A converter ch.1 analog output pin VREGCTL On-board regulator control pin The return signal input pin from a VWAKEUP hibernation state SD memory card interface S_CLK_0 SD memory card clock output pin SD memory card interface S_CMD_0 SD memory card command output S_DATA1_0 S_DATA0_0 SD memory card interface S_DATA3_0 SD memory card data bus S_DATA2_0 SD memory card interface S_CD_0 SD memory card detection pin SD memory card interface S_WP_0 SD memory card write protection WKUP0 Low-Power Consumption Mode DAC VBAT SD I/F Document Number: 001-98943 Rev.*F LQFP 120 10 89 48 11 88 49 12 87 50 33 119 69 34 118 68 35 115 67 115 64 23 115 64 23 Pin No LQFP LQFP 100 80 74 43 33 73 44 34 72 45 35 28 99 79 59 48 29 98 78 58 47 30 95 75 57 46 95 75 54 43 18 13 95 75 54 43 18 13 FBGA 121 F5 B11 J7 F6 C11 J8 G5 C10 K8 J3 A2 F9 J5 A3 F10 H5 B3 G8 B3 H9 H1 B3 H9 H1 116 96 76 B2 14 9 9 E1 50 45 35 K8 69 59 48 F9 36 37 41 31 32 36 21 22 26 K3 J4 K5 42 37 27 K6 92 77 62 B9 93 78 63 A9 94 95 96 97 79 80 81 82 64 65 66 67 C8 B8 A8 D7 113 93 73 B4 114 94 74 C3 Page 43 of 164 S6E2H Series Pin Function CAN0 CAN1 Reset Pin Name Function Description TX0_0 TX0_1 TX0_2 RX0_0 RX0_1 RX0_2 TX1_0 TX1_1 TX1_2 RX1_0 RX1_1 RX1_2 INITX MD1 Mode MD0 CAN interface ch.0 TX output pin CAN interface ch.0 RX input pin CAN interface ch.1 TX output pin CAN interface ch.1 RX input pin External Reset Input pin. A reset is valid when INITX=L. Mode 1 pin. During serial programming to Flash memory, MD1=L must be input. Mode 0 pin. During normal operation, MD0=L must be input. During serial programming to Flash memory, MD0=H must be input. Power VCC Power supply Pin GND VSS GND Pin Clock X0 X1 X0A X1A CROUT_0 CROUT_1 AVCC ADC Power AVRL AVRH VBAT Power VBAT Main clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) input pin Sub clock (oscillation) I/O pin Built-in high-speed CR-osc clock output port A/D converter and D/A converter analog power supply pin A/D converter analog reference voltage input pin A/D converter analog reference voltage input pin VBAT power supply pin. Backup power supply (battery etc.) and system power supply. A/D converter and D/A converter GND pin Power supply stabilization capacity pin LQFP 120 51 18 114 52 19 113 84 12 63 85 11 62 Pin No LQFP LQFP 100 80 13 94 74 14 93 73 53 42 52 41 FBGA 121 H6 F1 C3 H7 G1 B4 C9 G5 H10 B10 F6 J10 38 33 23 L3 56 46 36 L8 57 47 37 K9 1 31 46 61 91 117 107 30 45 60 90 120 1 26 41 51 76 97 92 25 40 50 75 100 1 31 61 77 20 30 40 60 80 B1 K1 K7 K11 A10 A4 A6 L1 L7 L11 A11 A1 - - - K10 58 59 39 40 87 113 48 49 34 35 72 93 38 39 24 25 58 73 L9 L10 L4 K4 C10 B4 70 60 49 J11 72 62 51 G11 73 63 52 F11 43 38 28 L5 ADC AVSS 71 61 50 H11 GND C pin C 44 39 29 L6 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 001-98943 Rev.*F Page 44 of 164 S6E2H Series 7. I/O Circuit Type Type Circuit P-ch P-ch Remarks Digital output X1 N-ch Digital output R It is possible to select the main oscillation / GPIO function Pull-up resistor control Digital input When the main oscillation is selected. − Clock input Oscillation feedback resistor : Approximately 1MΩ Standby mode control − With Standby mode control When the GPIO is selected. A − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control Digital input − Pull-up resistor Standby mode control − IOH = -4 mA, IOL = 4 mA − CMOS level hysteresis input − Pull-up resistor Standby mode control : Approximately 50 kΩ R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control B Pull-up resistor : Approximately 50 kΩ Digital input Document Number: 001-98943 Rev.*F Page 45 of 164 S6E2H Series Type Circuit Remarks Digital input C Digital output N-ch P-ch P-ch Digital output E N-ch − Open drain output − CMOS level hysteresis input − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ Digital output R − IOH = -4 mA, IOL = 4 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is Pull-up resistor control always off. Digital input Standby mode control Document Number: 001-98943 Rev.*F Page 46 of 164 S6E2H Series Type Circuit P-ch P-ch N-ch Remarks Digital output Digital output F − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ Pull-up resistor control R Digital input − IOH = -4 mA, IOL = 4 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is Standby mode control always off. Analog input Input control P-ch P-ch Digital output G N-ch − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ Digital output R − IOH = -12 mA, IOL = 12 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is Pull-up resistor control Digital input always off. Standby mode control Document Number: 001-98943 Rev.*F Page 47 of 164 S6E2H Series Type Circuit P-ch P-ch Remarks Digital output I N-ch Digital output − CMOS level output − CMOS level hysteresis input − 5 V tolerant − With standby mode control − Pull-up resistor : Approximately 50 kΩ R − IOH = -4 mA, IOL = 4 mA − Available to control of PZR registers. Pull-up resistor control Digital input Standby mode control J Mode input P-ch L P-ch N-ch Digital output CMOS level hysteresis input − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor Digital output : Approximately 50 kΩ − IOH = -8 mA, IOL = 8 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is R Pull-up resistor control Digital input always off. Standby mode control Document Number: 001-98943 Rev.*F Page 48 of 164 S6E2H Series Type Circuit P-ch P-ch N-ch Remarks Digital output Digital output M Pull-up resistor control Digital input R − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -8 mA, IOL = 8 mA − CMOS level output − CMOS level hysteresis input − 5V tolerant − With pull-up resistor control − With standby mode control − Pull-up resistor Standby mode control Analog input Input control P-ch P-ch Pull-up resistor control Digital output : Approximately 50 kΩ N N-ch N-ch Digital output − IOH = -4 mA, IOL = 4 mA (GPIO) − IOL = 20 mA (Fast Mode Plus) R Fast mode control Digital input − When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Standby mode control Document Number: 001-98943 Rev.*F Page 49 of 164 S6E2H Series Type Circuit P-ch P-ch O N-ch Remarks Pull-up resistor control Digital output Digital output − CMOS level output − CMOS level hysteresis input − 5 V tolerant − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual R Digital input Standby mode control P-ch P-ch X0A N-ch P Pull-up resistor control Digital output Digital output − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual R Digital input Standby mode control OSC Document Number: 001-98943 Rev.*F Page 50 of 164 S6E2H Series Type Circuit Pull-up resistor control Digital output P-ch P-ch X1A Remarks It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. − Oscillation feedback resistor : Approximately 10MΩ Digital output N-ch Q R Digital input Standby mode control OSC RX − With Standby mode control − When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual Standby mode control Clock input P-ch P-ch N-ch Pull-up resistor control Digital output Digital output R − CMOS level output − CMOS level hysteresis input − Analog output − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -12 mA, IOL = 12 mA (4.5 V to 5.5 V) R − Digital input IOH = -8 mA, IOL = 8 mA (2.7 V to 4.5 V) Standby mode control Analog output Document Number: 001-98943 Rev.*F Page 51 of 164 S6E2H Series 8. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 8.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Document Number: 001-98943 Rev.*F Page 52 of 164 S6E2H Series Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 8.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Document Number: 001-98943 Rev.*F Page 53 of 164 S6E2H Series Lead-Free Packaging CAUTION: When ball grid array (FBGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 001-98943 Rev.*F Page 54 of 164 S6E2H Series 8.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 001-98943 Rev.*F Page 55 of 164 S6E2H Series 9. Handling Devices Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device. Power Supply Pins A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.  Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF  Lead type Load capacitance: Approximately 6 pF to 7 pF Document Number: 001-98943 Rev.*F Page 56 of 164 S6E2H Series Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device X0(X0A) Set as External clock input Can be used as general-purpose I/O ports. X1(PE3), X1A (P47) Handling when Using Multi-function Serial Pin as I2C Pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Document Number: 001-98943 Rev.*F Page 57 of 164 S6E2H Series Notes on Power-on Turn power on/off in the following order or at the same time. The device operates normally after all power on. VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then VCC turns Power-off. About Hibernation control, see Chapter 7-2: VBAT Domain(A) in FM4 Family Peripheral Manual Main Part (002-04856). If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on: Turning off: VBAT → VCC VCC → AVCC → AVRH AVRH → AVCC → VCC VCC → VBAT Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Features among the Products with Different Memory Sizes and between Flash Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Adjoining Wiring on Circuit Board If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of P48/VREGCTL, there is a possibility that the oscillation erroneously counts because X1A has noise with the change of P48/VREGCTL. Keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility. Device P46/ X0A P47/ X1A P48/ P49/ VREGCTL VWAKEUP Not allowed to run both wirings in parallel Ground Insert the ground pattern Handling when Using Debug Pins When debug pins(TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input. Document Number: 001-98943 Rev.*F Page 58 of 164 S6E2H Series 10. Memory Size See Memory size in 2. Product Lineup to confirm the memory size. 11. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0x4007_0000 0x4006_F000 0x4006_E000 0x4006_C000 0xFFFF_FFFF GPIO SD-Card I/F Reserved Reserved 0xE010_0000 0xE000_0000 0xD000_0000 Cortex-M4 Private Peripherals Reg. Area 0x4006_3000 0x4006_2000 0x4006_1000 0x4006_0000 External Device Area 0x4004_0000 0x4003_F000 CAN ch.1 CAN ch.0 DSTC DMAC Reserved EXT-bus I/F 0x6000_0000 Reserved Reserved 0x4400_0000 0x4200_0000 0x4003_C800 32 Mbytes Bit band alias 0x4003_C100 0x4003_B000 Peripherals 0x4000_0000 0x4003_A000 0x4003_9000 0x4003_8000 Reserved 0x2400_0000 0x2200_0000 Reserved 0x2010_0000 0x200E_0000 0x200C_0000 0x2004_4000 See "Memory Map(2)" for the memory size details. 0x2004_0000 0x2003_C000 0x2000_0000 0x1FFF_8000 0x0050_0000 0x0040_0000 Work Flash I/F Work Flash Reserved SRAM2 SRAM1 Reserved SRAM0 Reserved Security/CR Trim MainFlash 0x0000_0000 0x4003_7000 0x4003_6000 32 Mbytes Bit band alias 0x4003_5000 RTC/Port Ctrl Watch Counter CRC MFS CAN prescaler Reserved LVD/DS mode 0x4003_4000 0x4003_3000 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read EXTI Reserved CR Trim 0x4003_0000 0x4002_F000 0x4002_E000 Reserved 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 0x4002_3000 0x4002_2000 0x4002_1000 0x4002_0000 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Document Number: 001-98943 Rev.*F Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler A/DC QPRC Base Timer PPG Reserved MFT Unit2 MFT Unit1 MFT Unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved MainFlash I/F Page 59 of 164 S6E2H Series Memory Map (2) S6E2HG6 0x200D_FFFF S6E2HG4 0x200D_FFFF Reserved 0x200C_8000 0x200C_0000 Reserved 0x200C_8000 Work Flash 32Kbytes 0x200C_0000 Work Flash 32Kbytes Reserved Reserved 0x2004_4000 SRAM2 16 Kbytes 0x2004_0000 0x2004_2000 0x2004_0000 SRAM1 16 Kbytes 0x2003_E000 SRAM2 8 Kbytes SRAM1 8 Kbytes 0x2003_C000 Reserved Reserved 0x2000_0000 0x2000_0000 SRAM0 32 Kbytes 0x1FFF_C000 SRAM0 16 Kbytes 0x1FFF_8000 Reserved Reserved 0x0040_6000 0x0040_6000 0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_2000 CR trimming Security 0x0040_2000 CR trimming Security 0x0040_0000 0x0040_0000 Reserved 0x0008_0000 Reserved MainFlash 512 Kbytes 0x0004_0000 MainFlash 256 Kbytes 0x0000_0000 Document Number: 001-98943 Rev.*F 0x0000_0000 Page 60 of 164 S6E2H Series Peripheral Address Map Start address 0x4000_0000 0x4000_1000 0x4001_0000 0x4001_1000 0x4001_2000 0x4001_3000 0x4001_5000 0x4001_6000 0x4002_0000 0x4002_1000 0x4002_2000 0x4002_3000 0x4002_4000 0x4002_5000 0x4002_6000 0x4002_7000 0x4002_8000 0x4002_E000 0x4002_F000 0x4003_0000 0x4003_1000 0x4003_2000 0x4003_3000 0x4003_4000 0x4003_5000 0x4003_5800 0x4003_6000 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_C100 0x4003_C800 0x4003_F000 0x4004_0000 0x4006_0000 0x4006_1000 0x4006_2000 0x4006_3000 0x4006_4000 0x4006_E000 0x4006_F000 0x4006_7000 0x200E_0000 Document Number: 001-98943 Rev.*F End address 0x4000_0FFF 0x4000_FFFF 0x4001_0FFF 0x4001_1FFF 0x4001_2FFF 0x4001_4FFF 0x4001_5FFF 0x4001_FFFF 0x4002_0FFF 0x4002_1FFF 0x4002_2FFF 0x4003_FFFF 0x4002_4FFF 0x4002_5FFF 0x4002_6FFF 0x4002_7FFF 0x4002_DFFF 0x4002_EFFF 0x4002_FFFF 0x4003_0FFF 0x4003_1FFF 0x4003_4FFF 0x4003_3FFF 0x4003_4FFF 0x4003_57FF 0x4003_5FFF 0x4003_6FFF 0x4003_7FFF 0x4003_8FFF 0x4003_9FFF 0x4003_AFFF 0x4003_BFFF 0x4003_C0FF 0x4003_C7FF 0x4003_EFFF 0x4003_FFFF 0x4005_FFFF 0x4006_0FFF 0x4006_1FFF 0x4006_2FFF 0x4006_3FFF 0x4006_DFFF 0x4006_EFFF 0x4006_FFFF 0x41FF_FFFF 0x200E_FFFF Bus AHB APB0 APB1 APB2 AHB Peripherals MainFlash I/F register Reserved Clock/Reset Control Hardware Watchdog timer Software Watchdog timer Reserved Dual-Timer Reserved Multi-function timer unit0 Multi-function timer unit1 Multi-function timer unit2 Reserved PPG Base Timer Quadrature Position/Revolution Counter A/D Converter Reserved Internal CR trimming Reserved External Interrupt Controller Interrupt Request Batch-Read Function Reserved D/A Converter Reserved Low Voltage Detector Deep standby mode Controller Reserved CAN prescaler Multi-function serial Interface CRC Watch Counter RTC/Port Ctrl Low-speed CR Prescaler Peripheral Clock Gating Reserved External Memory interface Reserved DMAC register DSTC register CAN ch.0 CAN ch.1 Reserved SD-Card I/F GPIO Reserved WorkFlash I/F register Page 61 of 164 S6E2H Series 12. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the L level.  INITX=1 This is the period when the INITX pin is the H level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.  Setting prohibition Prohibition of a setting by specification limitation. Document Number: 001-98943 Rev.*F Page 62 of 164 S6E2H Series Pin status Type List of Pin Behavior by Mode State A B Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 INITX=1 Return from Deep Standby Mode State Power Supply Unstable ‐ INITX=0 INITX=1 Power Supply Stable INITX=1 ‐ ‐ ‐ ‐ SPL=0 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state GPIO Hi-Z / Hi-Z / selected Internal input Internal input Internal input fixed fixed fixed at 0 at 0 at 0 GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Power Supply Stable GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Main crystal Internal input oscillator fixed at 0 / output pin or Input enabled SPL=1 SPL=0 SPL=1 GPIO Hi-Z / Hi-Z / selected Internal input Internal input Internal input fixed fixed fixed at 0 at 0 at 0 Input enabled Input enabled Maintain previous state Input enabled Hi-Z / Internal input fixed at 0 Power Supply Stable INITX=1 GPIO selected Input enabled Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Mode input pin Input enabled Input enabled Input enabled Setting disabled Setting disabled Input enabled Hi-Z / Input enabled Input enabled Hi-Z / Input enabled Input enabled Setting disabled Input enabled Maintain previous state Input enabled GPIO selected Input enabled Maintain previous state E Document Number: 001-98943 Rev.*F GPIO selected GPIO selected Page 63 of 164 Pin status Type S6E2H Series Function Group NMIX selected Resource other than above selected F Power-on Reset or Low-voltage Detection State Device Internal Reset State I INITX=1 ‐ ‐ SPL=0 Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Pull-up / Input enabled Pull-up / Input enabled Setting disabled JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled J Resource other than above selected GPIO selected Power Supply Stable ‐ Setting disabled Analog output selected Power Supply Stable INITX=0 Setting disabled GPIO selected Deep Standby RTC Mode or Deep Standby Stop Mode State ‐ GPIO selected Resource other than above selected GPIO selected Resource selected Timer Mode, RTC Mode, or Stop Mode State Power Supply Stable INITX=1 Power Supply Stable G H Run Mode or Sleep Mode State Power Supply Unstable ‐ GPIO selected JTAG selected INITX Input State Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z / Input enabled Document Number: 001-98943 Rev.*F Hi-Z / Input enabled Maintain previous state INITX=1 Maintain previous state Maintain previous state Maintain previous state Maintain previous state *2 Maintain previous state Maintain previous state Power Supply Stable INITX=1 INITX=1 SPL=1 Maintain previous state SPL=0 SPL=1 - Hi-Z / WKUP WKUP Hi-Z / input enabled input enabled Internal input fixed at 0 Maintain previous state Maintain previous state Maintain previous state GPIO Hi-Z / Hi-Z / selected Internal input Internal input Internal input fixed fixed fixed at 0 at 0 at 0 Maintain previous state Maintain previous state Return from Deep Standby Mode State Maintain previous state Maintain previous state GPIO selected Maintain previous state Maintain previous state GPIO selected Maintain previous state GPIO Hi-Z / Hi-Z / selected Internal input Internal input Internal input fixed fixed fixed at 0 at 0 at 0 GPIO selected GPIO Hi-Z / Hi-Z / selected Internal input Internal input Internal input fixed fixed fixed at 0 at 0 at 0 GPIO selected *3 GPIO Hi-Z / selected Internal input Internal input Hi-Z / fixed fixed Internal input at 0 at 0 fixed at 0 GPIO selected Page 64 of 164 Pin status Type S6E2H Series Function Group External interrupt enabled selected Resource other than above selected GPIO selected K Analog input selected Power-on Reset or Low-voltage Detection State Analog input selected M External interrupt enabled selected Resource other than above selected GPIO selected Device Internal Reset State Run Mode or Sleep Mode State Power Supply Unstable ‐ INITX=0 INITX=1 Power Supply Stable INITX=1 ‐ ‐ ‐ ‐ Setting disabled Setting disabled Setting disabled Power Supply Stable Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z Hi-Z / Internal input fixedat 0/ Analog input enabled Hi-Z / Internal input fixedat 0/ Analog input enabled L Resource other than above selected GPIO selected INITX Input State Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Return from Deep Standby Mode State Power Supply Stable INITX=1 - Maintain previous state Maintain previous state Maintain previous state GPIO Hi-Z / selected Internal input Internal input fixed Hi-Z / fixed at 0 Internal input at 0 fixed at 0 GPIO selected Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal input Internal Internal input Internal input Internal input Internal input fixed input fixed fixed fixed fixed fixed at 0 / at 0 / at 0 / at 0 / at 0 / at 0 / Analog Analog Analog Analog Analog Analog input input input enabled input enabled input enabled input enabled enabled enabled Maintain previous state Maintain previous state GPIO Hi-Z / Hi-Z / selected Internal input Internal input Internal input fixed fixed fixed at 0 at 0 at 0 GPIO selected Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal input Internal Internal input Internal input Internal input Internal input fixed input fixed fixed fixed fixed fixed at 0 / at 0 / at 0 / at 0 / at 0 / at 0 / Analog Analog Analog Analog Analog Analog input input input enabled input enabled input enabled input enabled enabled enabled Maintain previous state Setting disabled Setting disabled Document Number: 001-98943 Rev.*F Setting disabled Maintain previous state Maintain previous state GPIO Hi-Z / selected Internal input Internal input fixed Hi-Z / fixed at 0 Internal input at 0 fixed at 0 GPIO selected Page 65 of 164 Pin status Type S6E2H Series Function Group Analog input selected N Trace selected Resource other than above selected GPIO selected Analog input selected O Trace selected External interrupt enabled selected Resource other than above selected GPIO selected Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Power Supply Unstable ‐ INITX=0 INITX=1 Power Supply Stable INITX=1 ‐ ‐ ‐ ‐ Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Power Supply Stable Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 INITX=1 SPL=1 SPL=0 SPL=1 Return from Deep Standby Mode State Power Supply Stable INITX=1 - Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal input Internal Internal input Internal input Internal input Internal input fixed input fixed fixed fixed fixed fixed at 0 / at 0 / at 0 / at 0 / at 0 / at 0 / Analog Analog Analog Analog Analog Analog input input input enabled input enabled input enabled input enabled enabled enabled Trace output Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Maintain previous state GPIO Hi-Z / selected Internal input Hi-Z / Internal input fixed Internal input fixed at 0 fixed at 0 at 0 GPIO selected Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal input Internal Internal input Internal input Internal input Internal input fixed input fixed fixed fixed fixed fixed at 0 / at 0 / at 0 / at 0 / at 0 / at 0 / Analog Analog Analog Analog Analog Analog input input input enabled input enabled input enabled input enabled enabled enabled Trace output Setting disabled Setting disabled Document Number: 001-98943 Rev.*F Setting disabled Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO Hi-Z / selected Internal input Internal input fixed fixed at 0 at 0 GPIO selected Page 66 of 164 Pin status Type S6E2H Series Function Group Analog input selected P Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Power Supply Unstable ‐ INITX=0 INITX=1 Power Supply Stable INITX=1 ‐ ‐ ‐ ‐ Hi-Z Hi-Z / Internal input fixedat 0/ Analog input enabled Hi-Z / Internal input fixedat 0/ Analog input enabled Power Supply Stable Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 Maintain previous state Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state WKUP enabled Q External interrupt enabled selected Resource other than above selected GPIO selected Setting disabled Setting disabled Hi-Z / Input enabled Hi-Z / Input enabled INITX=1 SPL=0 SPL=1 - Maintain previous state Hi-Z / WKUP WKUP input input enabled enabled GPIO selected GPIO Hi-Z / Hi-Z / selected Internal input Internal input Internal input fixed fixed fixed at 0 at 0 at 0 Maintain previous state Setting disabled Maintain previous state Hi-Z Power Supply Stable INITX=1 Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal input Internal Internal input Internal input Internal input Internal input fixed input fixed fixed fixed fixed fixed at 0 / at 0 / at 0 / at 0 / at 0 / at 0 / Analog Analog Analog Analog Analog Analog input input input enabled input enabled input enabled input enabled enabled enabled WKUP enabled Resource other than above selected GPIO selected SPL=1 Return from Deep Standby Mode State WKUP input enabled Hi-Z / WKUP input enabled GPIO Hi-Z / selected Internal input Internal input fixed Hi-Z / fixed at 0 Internal input at 0 fixed at 0 GPIO selected *1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode, Deep standby RTC mode, and Deep standby Stop mode. *2: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode. Document Number: 001-98943 Rev.*F Page 67 of 164 S6E2H Series VBAT Pin Status Type List of VBAT Domain Pin Status Power-on reset*1 Function Group ‐ ‐ ‐ Setting disabled Maintain previous state Sub crystal oscillator input pin / Input External sub enabled clock input selected Run Mode or Sleep Mode State Power Supply Stable INITX=1 Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 Maintain previous state ‐ Maintain previous state Maintain previous state Input enabled Input enabled Input enabled Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal Sub crystal Maintain input fixed oscillator previous at 0 / state output pin or Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled External sub Setting clock input disabled selected T Device Internal Reset State Power Supply Power Supply Stable Unstable ‐ INITX=0 INITX=1 GPIO selected S INITX Input State Resource selected U Hi-Z GPIO selected Maintain previous state INITX=1 Maintain previous state SPL=0 Maintain previous state SPL=1 Maintain previous state Input enabled Input enabled Input enabled Maintain Maintain previous previous state state Maintain Maintain previous previous state state Maintain Maintain Maintain Maintain previous previous previous previous state/ state/ state/ state/ When When When When oscillation oscillation oscillation oscillation stops, stops, stops, stops, Hi-Z*2 Hi-Z*2 Hi-Z*2 Hi-Z*2 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Return from Deep Standby Mode State VBAT RTC Mode State Return from VBAT RTC Mode State Power Supply Stable INITX=1 Power Supply Stable - Power Supply Stable - - Setting prohibitio n - GPIO selected Input enabled - Maintain Maintain previous previous state state Setting prohibitio n Maintain Maintain Maintain previous previous previous state state state GPIO selected Maintain previous state Maintain Maintain previous previous state state Maintain previous state Maintain Maintain previous previous state state *1: When VBAT and VCC power on. *2: When The SOSCNTL bit in the WTOSCCNT Register is 0, Sub crystal oscillator output pin is maintain previous state. When The SOSCNTL bit in the WTOSCCNT Register is 1, Oscillation is stopped at Stop mode and Deep standby Stop mode. Document Number: 001-98943 Rev.*F Page 68 of 164 S6E2H Series 13. Electrical Characteristics 13.1 Absolute Maximum Ratings Parameter 1 Symbol 2 Power supply voltage * , * Power supply voltage (VBAT) *1 ,*3 Analog power supply voltage *1 ,*4 Analog reference voltage *1 ,*4 Input voltage *1 Rating VCC VBAT AVCC AVRH VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS + 6.5 VSS + 6.5 VSS + 6.5 VCC + 0.5 (≤ 6.5 V) VSS + 6.5 AVCC + 0.5 (≤ 6.5 V) VCC + 0.5 (≤ 6.5 V) 10 20 20 22.4 4 8 12 20 100 50 - 10 mA mA mA mA mA mA mA mA mA mA mA 4 mA type 8 mA type 12 mA type I2C Fm+ 4 mA type 8 mA type 12 mA type I2C Fm+ - 20 - 20 -4 -8 - 12 - 100 - 50 + 150 mA mA mA mA mA mA mA °C 8 mA type 12 mA type 4 mA type 8 mA type 12 mA type VSS - 0.5 VSS - 0.5 Analog pin input voltage *1 VIA VSS - 0.5 Output voltage *1 VO VSS - 0.5 L level maximum output current * L level average output current *6 L level total maximum output current L level total average output current *7 H level maximum output current *6 H level average output current *6 H level total maximum output current H level total average output current *7 Storage temperature Remarks Max VSS + 6.5 VI 5 Unit Min VSS - 0.5 IOL - IOLAV - ∑IOL ∑IOLAV - IOH - IOHAV - ∑IOH ∑IOHAV TSTG - 55 V V V V V V 5 V tolerant V V 4 mA type *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: VBAT must not drop below VSS - 0.5 V. *4: Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on. *5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100-ms period. *7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100-ms. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 001-98943 Rev.*F Page 69 of 164 S6E2H Series 13.2 Recommended Operating Conditions Parameter Power supply voltage Power supply voltage (VBAT) Analog power supply voltage Analog reference voltage Smoothing capacitor Junction temperature Operating temperature Ambient temperature Symbol Conditions VCC VBAT AVCC AVRH CS TJ TA - Value Min 2.7*4 2.7 2.7 *3 1 - 40 - 40 Max 5.5 5.5 5.5 AVCC 10 + 125 *2 Unit V V V V μF °C °C Remarks AVCC=VCC for built-in regulator *1 *1: See "C pin" in "Handling Devices" for the connection of the smoothing capacitor. *2: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction temperature (TJ). The calculation formula of the ambient temperature (TA) is shown below. TA (Max) = TJ (Max) – Pd (Max) × θja Pd: θja: Power dissipation (W) Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: IOH: VOL: VOH: L level output current H level output current L level output voltage H level output voltage *3 :The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5 12-bit A/D Converter for the details. *4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Document Number: 001-98943 Rev.*F Page 70 of 164 S6E2H Series Table for Package Thermal Resistance and Maximum Permissible Power Package LQH080 (0.5mm pitch) LQI100 (0.5mm pitch) LQM120 (0.5mm pitch) FDI121 (0.5mm pitch) Printed Circuit Board Thermal Resistance θja (°C/W) Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers 82 56 59 39 71 50 63 37 Maximum Permissible Power (mW) TA=+85°C 488 714 678 1026 563 800 635 1081 TA=+105°C 244 357 339 513 282 400 317 540 WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 001-98943 Rev.*F Page 71 of 164 S6E2H Series Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage ICC is a current consumed in device. It can be analyzed as follows. ICC = ICC(INT) + ΣICC(IO) ICC(INT): Current consumed in internal logic and memory, etc. through regulator ΣICC(IO): Sum of current (I/O switching current) consumed in output pin For ICC (INT), it can be anticipated by (1) Current Rating in 3. DC Characteristics (This rating value does not include ICC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC(IO) = (CINT + CEXT) × VCC × fsw CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Symbol Pin internal load capacitance Conditions Capacitance Value 4 mA type 1.93 pF 8 mA type 3.45 pF 12 mA type 3.42 pF CINT Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself. 1. Measure current value ICC (Typ) at normal temperature (+25°C). 2. Add maximum leak current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC(Typ) + ICC(leak_max) Parameter Symbol Maximum leak current at operating ICC(leak_max) Document Number: 001-98943 Rev.*F Conditions TJ = +125°C TJ = +105°C TJ = +85°C Current Value 16.8 mA 8.6 mA 5.8 mA Page 72 of 164 S6E2H Series Current Explanation Diagram Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH)) ICC = ICC(INT)＋ΣICC(IO) VCC A ICC Chip ICC(INT) ΣICC(IO) A Regulator VOL V A ・・・ V IOL Flash VOH ・・・ Logic IOH RAM ICC(IO) CEXT ・・・ Document Number: 001-98943 Rev.*F Page 73 of 164 S6E2H Series 13.3 DC Characteristics 13.3.1 Current Rating Table 12-1 Typical and Maximum Current Consumption in Normal Operation(PLL), Code Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Enabled) Value Pin Parameter Symbol Conditions Frequency*4 Unit Remarks Name Typ*1 Max*2 71 160 MHz 51 67 144 MHz 47 120 MHz 39 59 100 MHz 33 53 *3 80 MHz 27 47 mA When all peripheral 60 MHz 20 40 clocks are ON 40 MHz 14 34 20 MHz 7.6 28 8 MHz 3.9 24 Power 4 MHz 2.7 23 Normal operation supply ICC VCC *5, *6 *9 160 MHz 30 51 (PLL) current 48 144 MHz 28 120 MHz 23 43 100 MHz 20 40 *3 36 80 MHz 16 mA When all peripheral 32 60 MHz 12 clocks are OFF 29 40 MHz 8.7 20 MHz 5.0 25 8 MHz 2.8 23 4 MHz 2.1 22 Table 12-2 Typical and Maximum Current Consumption in Normal Operation(PLL), Code with Data Accessing Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled) Value Pin Parameter Symbol Name Conditions Frequency*7 Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (PLL) *8 *9 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 56 51 43 37 30 23 16 8.5 4.3 2.9 30 28 24 20 17 13 9.2 5.3 3.0 2.2 76 71 63 57 50 43 36 29 25 23 51 48 44 41 37 33 30 26 23 23 *3 mA When all peripheral clocks are ON *3 mA When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are input and are fixed at "0" Document Number: 001-98943 Rev.*F Page 74 of 164 S6E2H Series *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *6: Data access is nothing to MainFlash memory *7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK *8: When permit flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) *9: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Table 12-3 Typical and Maximum Current Consumption in Normal Operation(PLL), Code with Data Accessing Running from Flash Memory (Flash 0 wait-cycle Mode and Read Access 0 wait) Value Pin Frequency*4 Parameter Symbol Conditions Unit Remarks Name (MHz) Typ*1 Max*2 58 72 MHz 38 53 60 MHz 33 48 48 MHz 28 *3 42 36 MHz 22 mA When all peripheral 36 24 MHz 16 clocks are ON 30 12 MHz 9.5 8 MHz 6.9 27 Power Normal 4 MHz 4.2 25 supply ICC VCC operation *5 *6 72 MHz 29 49 current (PLL) 46 60 MHz 26 48 MHz 22 42 *3 36 MHz 18 38 mA When all peripheral 33 24 MHz 13 clocks are OFF 28 12 MHz 7.8 26 8 MHz 5.8 4 MHz 3.7 24 *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are input and are fixed at "0" *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) *6: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 001-98943 Rev.*F Page 75 of 164 S6E2H Series Table 12-4 Typical and Maximum Current Consumption in Normal Operation(other than PLL), Code with Data Accessing Running from Flash Memory (Flash 0 wait-cycle Mode and Read Access 0 wait) Value Pin Parameter Symbol Conditions Frequency*4 Unit Remarks 1 Name Typ* Max*2 Normal operation (main oscillation) Normal operation (built-in high-speed CR) Power supply current ICC *5*6 *5 24 3.2 24 3.2 24 2.7 23 0.34 21 *3 mA When all peripheral clocks are ON 0.30 21 *3 mA When all peripheral clocks are OFF 0.36 21 *3 mA When all peripheral clocks are ON 0.33 21 *3 mA When all peripheral clocks are OFF 4 MHz 4 MHz VCC Normal operation (sub oscillation) Normal operation (built-in low-speed CR) *5 *5 *3 mA When all peripheral clocks are ON *3 mA When all peripheral clocks are OFF *3 mA When all peripheral clocks are ON *3 mA When all peripheral clocks are OFF 4.0 32 kHz 100 kHz *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are input and are fixed at "0" *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) *6: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 001-98943 Rev.*F Page 76 of 164 S6E2H Series Table 12-5 Typical and Maximum Current Consumption in Sleep Operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current Symbol Pin Name ICCS VCC Value 4 Conditions Frequency* Sleep operation *6 (PLL) 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 1 Typ* Max*2 35 32 27 23 18 14 9.9 5.5 3.1 2.3 14 13 11 9.5 7.8 6.3 4.6 2.9 2.2 2.0 55 52 47 43 39 34 30 26 23 23 35 33 31 30 28 27 25 23 23 22 Unit Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF Table 12-6 Typical and Maximum Current Consumption in Sleep Operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Value Pin 5 Parameter Symbol Name Conditions Frequency* Unit Remarks 1 Typ* Max*2 Power supply current ICCS VCC Sleep operation *6 (PLL) 72 MHz 60 MHz 23 19 48 MHz 16 43 39 36 36 MHz 12 32 24 MHz 12 MHz 8 MHz 4 MHz 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz 8.5 5.1 3.9 2.7 8.8 7.6 6.3 5.1 3.9 2.7 2.3 1.9 29 25 24 23 29 28 27 25 24 23 23 22 mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are input and are fixed at "0" *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *6: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 001-98943 Rev.*F Page 77 of 164 S6E2H Series Table 12-7 Typical and Maximum Current Consumption in Sleep Operation(other than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Symbol Pin Name Conditions Sleep operation *5 (main oscillation) Power supply current Sleep operation (built-in high-speed CR) ICCS Frequency*4 Value Typ* Max*2 Unit 2.1 22 mA *3 When all peripheral clocks are ON 1.3 22 mA *3 When all peripheral clocks are OFF 1.3 22 mA *3 When all peripheral clocks are ON 0.8 21 mA 0.28 21 mA 0.27 21 mA 0.29 21 mA *3 When all peripheral clocks are ON 0.28 21 mA *3 When all peripheral clocks are OFF 1 4MHz 4 MHz VCC Sleep operation (sub oscillation) Sleep operation (built-in low-speed CR) Remarks 32 kHz 100 kHz *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are input and are fixed at "0" *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 001-98943 Rev.*F Page 78 of 164 S6E2H Series Table 12-8 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode Value Parameter Symbol Pin Name ICCH Conditions Stop mode Timer mode *5 (main oscillation) Timer mode (built-in high-speed CR) Power supply current ICCT Frequency - 4 MHz 4 MHz Typ*1 Max*2 Unit 0.21 0.94 mA - 7.6 mA - 10 mA 1.4 2.1 mA - 8.8 mA - 11 mA 0.49 1.2 mA - 7.9 mA - 11 mA 0.23 0.96 mA - 7.6 mA - 10 mA 0.24 0.97 mA - 7.6 mA - 10 mA 0.21 0.94 mA - 7.6 mA - 10 mA VCC Timer mode (sub oscillation) Timer mode (built-in low-speed CR) ICCR RTC mode (sub oscillation) 32 kHz 100 kHz 32 kHz Remarks *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are input and are fixed at "0" *4: When LVD is OFF *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 001-98943 Rev.*F Page 79 of 164 S6E2H Series Table 12-9 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT Value Parameter Symbol Pin Name Conditions Frequency Deep standby Stop mode (When RAM is OFF) ICCHD Typ*1 Max*2 Unit 24 40 µA - 640 µA - 813 µA 41 146 µA - 1616 µA - 2059 µA 24 40 µA - 640 µA - 813 µA 41 146 µA - 1616 µA - 2059 µA 0.015 0.14 µA - 4.0 µA - 9.4 µA 1.3 2.4 µA - 6.2 µA - 12 µA Deep standby Stop mode (When RAM is ON) VCC Power supply current Deep standby RTC mode (When RAM is OFF) ICCRD 32 kHz Deep standby RTC mode (When RAM is ON) RTC stop*7 ICCVBAT VBAT RTC operation *6, *7 Remarks *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4, *5 TA=+25°C *3, *4, *5 TA=+85°C *3, *4, *5 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are input and are fixed at "0" *4: When LVD is OFF *5: When sub oscillation is OFF *6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) *7: In the case of setting RTC after VCC power on Document Number: 001-98943 Rev.*F Page 80 of 164 S6E2H Series Table 12-10 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/erase Value Parameter Symbol Pin Name Conditions Unit Remarks Min Typ Max Low-voltage detection circuit (LVD) power supply current At operation - 4 7 μA At Write/Erase - 13.4 15.9 mA At Write/Erase - 11.5 13.6 mA ICCLVD Main flash memory write/erase current ICCFLASH Work flash memory write/erase current ICCWFLASH VCC For occurrence of interrupt *1 *1: When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to the Power supply current (ICC). Table 12-11 Peripheral Current Dissipation Clock System Unit GPIO All ports DMAC - 0.68 1.35 2.63 DSTC - 0.93 1.88 3.65 External bus I/F - 0.17 0.34 0.71 SD card I/F - 0.01 0.02 0.03 CAN 1 ch. 0.47 0.92 1.85 Base timer 4 ch. 0.18 0.37 0.73 0.61 1.22 2.43 0.04 0.07 0.14 0.22 0.44 0.88 0.30 0.60 - HCLK PCLK1 PCLK2 Frequency (MHz) 40 80 160 0.16 0.32 0.62 Peripheral Multi-functional timer/PPG Quadrature position/Revolution counter 1 unit / 4 ch. Remarks mA TA=+25°C, VCC=3.3 V mA TA=+25°C, VCC=3.3 V mA TA=+25°C, VCC=3.3 V 1 unit A/DC 1 unit Multi-function serial 1 ch. Document Number: 001-98943 Rev.*F Unit Page 81 of 164 S6E2H Series 13.3.2 Pin Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter H level input voltage (hysteresis input) L level input voltage (hysteresis input) Symbol VIHS VILS Pin Name CMOS hysteresis input pin, MD0, MD1 5 V tolerant input pin Input pin doubled as I2C Fm+ CMOS hysteresis input pin, MD0, MD1 5 V tolerant input pin Input pin doubled as I2C Fm+ 4mA type 8mA type H level output voltage VOH 12mA type The pin doubled as I2C Fm+ Document Number: 001-98943 Rev.*F Conditions Value Unit Min Typ Max - VCC×0.8 - VCC + 0.3 V - VCC×0.8 - VSS + 5.5 V - VCC×0.7 - VSS + 5.5 V - VSS - 0.3 - VCC×0.2 V - VSS - 0.3 - VCC×0.2 V - VSS - VCC×0.3 V VCC - 0.5 - VCC V VCC - 0.5 - VCC V VCC - 0.5 - VCC V VCC - 0.5 - VCC V VCC ≥ 4.5 V, IOH = - 4 mA VCC < 4.5 V, IOH = - 2 mA VCC ≥ 4.5 V, IOH = - 8 mA VCC < 4.5 V, IOH = - 4 mA VCC ≥ 4.5 V, IOH = - 12 mA VCC < 4.5 V, IOH = - 8 mA VCC ≥ 4.5 V, IOH = - 4 mA VCC < 4.5 V, IOH = - 3 mA Remarks At GPIO Page 82 of 164 S6E2H Series Value Parameter Symbol Pin Name 4 mA type 8 mA type L level output voltage VOL 12 mA type Conditions VCC ≥ 4.5 V, IOL = 4 mA VCC < 4.5 V, IOL = 2 mA VCC ≥ 4.5 V, IOH = 8 mA VCC < 4.5 V, IOH = 4 mA VCC ≥ 4.5 V, IOL = 12 mA VCC < 4.5 V, IOL = 8 mA Unit Min Typ Max VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VCC ≥ 4.5 V, IOH = 4 mA The pin doubled as I2C Fm+ VCC < 4.5 V, IOH = 3 mA At GPIO VCC ≤ 5.5 V, IOH = 20 mA Input leak current Pull-up resistor value Input capacitance At I2C Fm+ IIL - - -5 - +5 μA RPU Pull-up pin VCC ≥ 4.5 V VCC < 4.5 V 25 30 50 80 100 200 kΩ CIN Other than VCC, VBAT, VSS, AVCC, AVSS, AVRH - - 5 15 pF Document Number: 001-98943 Rev.*F Remarks Page 83 of 164 S6E2H Series 13.4 AC Characteristics 13.4.1 Main Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Input frequency Pin Name fCH Input clock cycle tCYLH Input clock pulse width Input clock rising time and falling time Internal operating clock*1 frequency X0, X1 tCF, tCR fCC fCP0 fCP1 fCP2 - Conditions Value Min Max VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V PWH/tCYLH, PWL/tCYLH 4 4 4 4 20.83 50 48 20 48 20 250 250 45 - Unit Remarks MHz When crystal oscillator is connected MHz When using external clock ns When using external clock 55 % When using external clock - 5 ns When using external clock - 160 80 160 80 MHz MHz MHz MHz Base clock (HCLK/FCLK) APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 tCYCC 6.25 ns Base clock (HCLK/FCLK) tCYCP0 12.5 ns APB0 bus clock*2 tCYCP1 6.25 ns APB1 bus clock*2 tCYCP2 12.5 ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). Internal operating clock*1 cycle time *2: For about each APB bus which each peripheral is connected to, see 1. S6E2H Series Block Diagram" in this data sheet. X0 Document Number: 001-98943 Rev.*F Page 84 of 164 S6E2H Series 13.4.2 Sub Clock Input Characteristics (VBAT = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Input frequency Pin Name Conditions Input clock cycle Input clock pulse width tCYLL - Remarks Max - - 32.768 - kHz - 32 - 100 kHz When crystal oscillator is connected When using external clock PWH/tCYLL, PWL/tCYLL 10 - 31.25 μs When using external clock 45 - 55 % When using external clock 0.8 × VBAT VBAT VBAT VBAT VBAT X0A 13.4.3 Unit Typ 1/ tCYLL X0A, X1A Value Min Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Clock frequency Symbol Conditions Value Min Typ Max TJ = -20°C to + 105°C 3.92 4 4.08 TJ = - 40°C to + 125°C 3.88 4 4.12 Unit fCRH Remarks When trimmed*1 Clock frequency fCRH TJ = - 40°C to + 125°C 2.9 4 5 Frequency stabilization time tCRWT - - - 30 MHz When not trimming μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use high-speed CR clock as source clock. Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Clock frequency Symbol Condition fCRL - Document Number: 001-98943 Rev.*F Value Min Typ Max 50 100 150 Unit Remarks kHz Page 85 of 164 S6E2H Series 13.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Value Unit Min Typ Max tLOCK 200 - - μs fPLLI - 4 13 - 16 80 MHz multiplier fPLLO 200 - 320 MHz fCLKPLL - - 160 MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). 13.4.5 Operating Conditions of Main PLL (In the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Value Unit Min Typ Max tLOCK 200 - - μs fPLLI 3.8 4 4.2 MHz - 50 - 75 multiplier fPLLO 190 - 320 MHz fCLKPLL - - 160 MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). Note: − Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has been trimmed. 13.4.6 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Reset input time Symbol tINITX Document Number: 001-98943 Rev.*F Pin Name Condition INITX - Value Min Max 500 - Unit Remarks ns Page 86 of 164 S6E2H Series 13.4.7 Power-on Reset Timing (VSS = 0V) Parameter Power supply shut down time Power ramp rate Pin Symbol Name VCC Value Min Typ Max - 50 - - VCC: 0.2V to 2.70V 1.3 - 1000 - 0.33 - 0.60 tOFF dV/dt Time until releasing Power-on reset Conditions tPRT Unit ms Remarks *1 mV/µs *2 ms *1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50ms). Note: − tOFF must be satisfied. When tOFF cannot be satisfied, assert external reset (INITX) at power-up and at any brownout event. 2.7V VCC VDH 0.2V dV/dt 0.2V tPRT Internal RST CPU Operation RST Active 0.2V tOFF release start Glossary  VDH: detection voltage of Low-Voltage detection reset. See 13.7 Low-Voltage Detection Characteristics. Document Number: 001-98943 Rev.*F Page 87 of 164 S6E2H Series 13.4.8 GPIO Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Output frequency Symbol Pin Name Conditions tPCYCLE Pxx* VCC ≥ 4.5 V VCC < 4.5 V Value Min Max - 50 32 Unit MHz MHz *: GPIO is a target. Pxx tPCYCLE Document Number: 001-98943 Rev.*F Page 88 of 164 S6E2H Series 13.4.9 External Bus Timing External Bus Clock Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Output frequency Symbol Pin Name Conditions tCYCLE MCLKOUT*1 VCC ≥ 4.5 V VCC < 4.5 V Value Min Max - 50*2 32*3 Unit MHz MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral Manual Main part (002-04856). *2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100 MHz. *3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64 MHz. 0.8 × Vcc 0.8 × Vcc MCLK tCYCLE External Bus Signal Input/output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Signal input characteristics Symbol Conditions Value Unit 0.8 × VCC V 0.2 × VCC V VOH 0.8 × VCC V VOL 0.2 × VCC V VIH VIL Signal output characteristics - Signal input VIH VIL VIH VIL Signal output VOH VOL VOH VOL Document Number: 001-98943 Rev.*F Remarks Page 89 of 164 S6E2H Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MOEX Minimum pulse width MCSX↓→Address output delay time Pin Name tOEW MOEX tCSL – AV MOEX↑→Address hold time MCSX↓→ MOEX↓ delay time MOEX↑→ MCSX↑ time MCSX↓→MDQM↓ delay time Symbol tOEH - AX tCSL - OEL tOEH - CSH tCSL - RDQML Data set up→MOEX↑ time MOEX↑→ Data hold time MWEX Minimum pulse width MWEX↑→Address output delay time tDS - OE tDH - OE MOEX, MCSX[7:0] MCSX, MDQM[1:0] MOEX, MADATA[15:0] MOEX, MADATA[15:0] tWEW MWEX tWEH - AX MWEX, MAD[24:0] MCSX↓→MWEX↓ delay time tCSL - WEL MWEX↑→MCSX↑ delay time tWEH - CSH MCSX↓→MDQM↓ delay time tCSL-WDQML MWEX↓→ Data output time MWEX↑→ Data hold time MCSX[7:0], MAD[24:0] MOEX, MAD[24:0] tCSL-DX tWEH - DX MWEX, MCSX[7:0] MCSX, MDQM[1:0] MCSX, MADATA[15:0] MWEX, MADATA[15:0] Conditions VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V Value Unit Min Max MCLK×n-3 - -9 -12 MCLK×m-9 MCLK×m-12 20 38 +9 +12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 - 0 - ns MCLK×n-3 - ns 0 MCLK×m-9 MCLK×m-12 0 0 MCLK×n-9 MCLK×n-12 0 MCLK×n-9 MCLK×n-12 MCLK-9 MCLK-12 0 MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK+9 MCLK+12 MCLK×m+9 MCLK×m+12 ns ns ns ns ns ns ns ns ns ns ns ns ns Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) Document Number: 001-98943 Rev.*F Page 90 of 164 S6E2H Series tCYCLE MCLK tOEH-CSH MCSX[7:0] MAD[24:0] MOEX tCSL-AV tWEH-CSH tOEH-AX Address tWEH-AX tCSL-AV Address tCSL-OEL tOEW tCSL-WDQML tCSL-RDQML MDQM[1:0] tCSL-WEL tWEW MWEX MADATA[15:0] tDS-OE tDH-OE RD tWEH-DX WD Invalid tCSL-DX Document Number: 001-98943 Rev.*F Page 91 of 164 S6E2H Series Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Address delay time Symbol Pin Name Conditions tAV MCLK, MAD[24:0] VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V tCSL MCSX delay time tCSH tREL MOEX delay time tREH MCLK, MCSX[7:0] MCLK, MOEX Data set up →MCLK↑ time tDS MCLK, MADATA[15:0] MCLK↑→ Data hold time tDH MCLK, MADATA[15:0] tWEL MWEX delay time tWEH MDQM[1:0] delay time tDQML tDQMH MCLK, MWEX MCLK, MDQM[1:0] MCLK↑→ Data output time tODS MCLK, MADATA[15:0] MCLK↑→ Data hold time tOD MCLK, MADATA[15:0] Value Min 1 1 1 1 1 Max 9 12 9 12 9 12 9 12 9 12 Unit ns ns ns ns ns 19 37 - ns 0 - ns 1 1 1 1 MCLK+1 1 9 12 9 12 9 12 9 12 MCLK+18 MCLK+24 18 24 ns ns ns ns ns ns Note: − When the external load capacitance CL = 30 pF Document Number: 001-98943 Rev.*F Page 92 of 164 S6E2H Series tCYCLE MCLK tCSL tCSH MCSX[7:0] tAV tAV Address MAD[24:0] Address tREL tREH tDQML tDQMH MOEX tDQML tDQMH tWEL tWEH MDQM[1:0] MWEX tDS tDH RD MADATA[15:0] Document Number: 001-98943 Rev.*F tOD WD Invalid tODS Page 93 of 164 S6E2H Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Multiplexed address delay time tALE-CHMADV Multiplexed address hold time tCHMADH Pin Name MALE, MADATA[15:0] Conditions Value Min Max 10 20 VCC ≥ 4.5 V VCC < 4.5 V 0 VCC ≥ 4.5 V MCLK×n+0 MCLK×n+10 VCC < 4.5 V MCLK×n+0 MCLK×n+20 Unit ns ns Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 001-98943 Rev.*F Page 94 of 164 S6E2H Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol tCHAL MALE delay time tCHAH MCLK↑→ Multiplexed address delay time Pin Name Conditions MCLK, ALE VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V 1 1 Max 9 12 9 12 Unit Remarks ns ns ns ns VCC ≥ 4.5 V tCHMADV MCLK, MADATA[15:0] MCLK↑→ Multiplexed data output time Value Min 1 tOD ns 1 tOD ns VCC < 4.5 V VCC ≥ 4.5 V tCHMADX VCC < 4.5 V Note: − When the external load capacitance CL = 30 pF MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 001-98943 Rev.*F Page 95 of 164 S6E2H Series NAND Flash Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MNREX Min pulse width Data set up →MNREX↑ time MNREX↑→ Data hold time MNALE↑→ MNWEX delay time MNALE↓→ MNWEX delay time MNCLE↑→ MNWEX delay time MNWEX↑→ MNCLE delay time MNWEX Min pulse width MNWEX↓→ Data output time MNWEX↑→ Data hold time Symbol Pin Name tNREW MNREX tDS – NRE tDH – NRE tALEH - NWEL tALEL - NWEL tCLEH - NWEL tNWEH - CLEL tNWEW tNWEL – DV tNWEH – DX MNREX, MADATA[15:0] MNREX, MADATA[15:0] MNALE, MNWEX MNALE, MNWEX MNCLE, MNWEX MNCLE, MNWEX MNWEX MNWEX, MADATA[15:0] MNWEX, MADATA[15:0] Conditions VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V Value Unit Min Max MCLK×n-3 - ns 20 38 - ns 0 - ns MCLK×m-9 MCLK×m-12 MCLK×m-9 MCLK×m-12 MCLK×m-9 MCLK×m-12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 0 MCLK×n-3 - -9 -12 +9 +12 MCLK×m+9 MCLK×m+12 0 ns ns ns ns ns ns ns Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) NAND Flash Read MCLK MNREX MADATA[15:0] Read Document Number: 001-98943 Rev.*F Page 96 of 164 S6E2H Series NAND Flash Address Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Write NAND Flash Command Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Write Document Number: 001-98943 Rev.*F Page 97 of 164 S6E2H Series External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name tRDYI MCLK, MRDY MCLK↑ MRDY input setup time Conditions Value Min VCC ≥ 4.5 V 19 VCC < 4.5 V 37 Max - Unit Remarks ns  When RDY is input ··· MCLK Over 2cycle Original MOEX MWEX tRDYI MRDY  When RDY is released MCLK ··· ··· 2 cycle Extended MOEX MWEX tRDYI 0.5×VCC MRDY Document Number: 001-98943 Rev.*F Page 98 of 164 S6E2H Series SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Output frequency tCYCSD Address delay time Value Unit Min Max MSDCLK - 32 MHz tAOSD MSDCLK, MAD[15:0] 2 12 ns MSDCLK↑→Data output delay time tDOSD MSDCLK, MADATA[31:0] 2 12 ns MSDCLK↑→Data output Hi-Z time tDOZSD MSDCLK, MADATA[31:0] 2 20 ns MDQM[1:0] delay time tWROSD MSDCLK, MDQM[1:0] 1 12 ns MCSX delay time tMCSSD MSDCLK, MCSX8 2 12 ns MRASX delay time tRASSD MSDCLK, MRASX 2 12 ns MCASX delay time tCASSD MSDCLK, MCASX 2 12 ns MSDWEX delay time tMWESD MSDCLK, MSDWEX 2 12 ns MSDCKE delay time tCKESD MSDCLK, MSDCKE 2 12 ns Data set up time tDSSD MSDCLK, MADATA[31:0] 23 - ns Data hold time tDHSD MSDCLK, MADATA[31:0] 0 - ns Note: − When the external load capacitance CL = 30 pF Document Number: 001-98943 Rev.*F Page 99 of 164 S6E2H Series SDRAM Access tCYCSD MSDCLK tAOSD MAD[24:0] MDQM[1:0] MCSX MRASX MCASX MSDWEX MSDCKE Address tWROSD tMCSSD tRASSD tCASSD tMWESD tCKESD tDSSD MADATA[15:0] tDOSD MADATA[15:0] Document Number: 001-98943 Rev.*F tDHSD RD tDOZSD WD Page 100 of 164 S6E2H Series 13.4.10 Base Timer Input Timing Timer Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol Pin Name Conditions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK VIHS VIHS TIN VILS VILS Trigger Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol Pin Name Conditions tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see 1. S6E2H Series Block Diagram in this data sheet. Document Number: 001-98943 Rev.*F Page 101 of 164 S6E2H Series 13.4.11 CSIO Timing Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Baud Rate Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time tF tR SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation External shift clock operation VCC < 4.5 V Min Max 8 4tCYCP - VCC ≥ 4.5 V Min Max 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 102 of 164 S6E2H Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL MS bit = 0 tSLSH VIH SCK tF VIL tSHSL VIL SIN VIH tR tSLOVE SOT VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 001-98943 Rev.*F Page 103 of 164 S6E2H Series Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Baud Rate Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation External shift clock operation VCC < 4.5 V Min Max 8 4tCYCP - VCC ≥ 4.5 V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 104 of 164 S6E2H Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL VIH VIL SCK tR tSLSH tSHOVE SOT SIN VIH VIL VIL tF VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 001-98943 Rev.*F Page 105 of 164 S6E2H Series Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Baud Rate Serial clock cycle time tSCYC - SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time tF tR Internal shift clock operation External shift clock operation VCC < 4.5 V Min Max 8 4tCYCP - VCC ≥ 4.5 V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 106 of 164 S6E2H Series tSCYC VOH VOL SCK SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH VIH SCK SOT VIL V VIL IH tF *V VIH tSHOVE tR VOH VOL OH VOL tIVSLE SIN tSHSL tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 001-98943 Rev.*F Page 107 of 164 S6E2H Series Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Baud Rate Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time tF tR Pin Name Conditions SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx - Internal shift clock operation External shift clock operation VCC < 4.5 V Min Max 8 4tCYCP - VCC ≥ 4.5 V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 108 of 164 S6E2H Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL VIH tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 001-98943 Rev.*F Page 109 of 164 S6E2H Series When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↓setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SUT delay time tDSE SCS↑→SUT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+0 (*3)-50 +5tCYCP 3tCYCP+30 (*2)+50 (*3)+50 +5tCYCP - (*2)+0 (*3)-50 +5tCYCP 3tCYCP+30 (*2)+50 (*3)+50 +5tCYCP - ns ns ns 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 110 of 164 S6E2H Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 001-98943 Rev.*F Page 111 of 164 S6E2H Series When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↑setup time tCSSI SCK↓→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↑setup time tCSSE SCK↓→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+0 (*3)-50 +5tCYCP 3tCYCP+30 (*2)+50 (*3)+50 +5tCYCP - (*2)+0 (*3)-50 +5tCYCP 3tCYCP+30 (*2)+50 (*3)+50 +5tCYCP - ns ns ns 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 112 of 164 S6E2H Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 001-98943 Rev.*F Page 113 of 164 S6E2H Series When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↑→SCK↓setup time tCSSI SCK↑→SCS↓ hold time tCSHI SCS deselect time tCSDI Conditions Internal shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+50 (*3)+50 +5tCYCP - (*2)+0 (*3)-50 +5tCYCP 3tCYCP+30 (*2)+50 (*3)+50 +5tCYCP - ns SCS↑→SCK↓setup time tCSSE (*2)+0 (*3)-50 +5tCYCP 3tCYCP+30 SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns External shift clock operation ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 114 of 164 S6E2H Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 001-98943 Rev.*F Page 115 of 164 S6E2H Series When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↑→SCK↑setup time tCSSI SCK↓→SCS↓ hold time tCSHI SCS deselect time tCSDI Conditions Internal shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+50 (*3)+50 +5tCYCP - (*2)+0 (*3)-50 +5tCYCP 3tCYCP+30 (*2)+50 (*3)+50 +5tCYCP - ns SCS↑→SCK↑setup time tCSSE (*2)+0 (*3)-50 +5tCYCP 3tCYCP+30 SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns External shift clock operation ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 116 of 164 S6E2H Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 001-98943 Rev.*F Page 117 of 164 S6E2H Series High-speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5 V VCC ≥ 4.5 V Min Max Min Max SCKx 4tCYCP - 4tCYCP - ns tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns Serial clock L pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns Parameter Symbol Pin Name Serial clock cycle time tSCYC SCK↓→SOT delay time SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCKx, SINx Conditions Internal shift clock operation 14 12.5* External shift clock operation SCKx, SINx Unit SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − − − − These characteristics only guarantee the following pins. No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 001-98943 Rev.*F Page 118 of 164 S6E2H Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL MS bit = 0 tSLSH SCK VIH tF VIL tSHSL VIL SIN VIH tR tSLOVE SOT VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 001-98943 Rev.*F Page 119 of 164 S6E2H Series High-speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Serial clock cycle time tSCYC SCKx SCK↑→SOT delay time tSHOVI SCKx, SOTx Conditions VCC < 4.5 V VCC ≥ 4.5 V Min Max Min Max 4tCYCP - 4tCYCP - ns -10 +10 -10 +10 ns - 12.5 - ns Internal shift clock operation 14 Unit SIN→SCK↓ setup time tIVSLI SCKx, SINx SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns Serial clock L pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns 5 - 5 - ns 12.5* External shift clock operation SIN→SCK↓ setup time tIVSLE SCKx, SINx SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − − − − These characteristics only guarantee the following pins. No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 001-98943 Rev.*F Page 120 of 164 S6E2H Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK VIH VIL tR tSLSH tSHOVE SOT SIN VIH VIL VIL tF VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 001-98943 Rev.*F Page 121 of 164 S6E2H Series High-speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5 V VCC ≥ 4.5 V Min Max Min Max SCKx 4tCYCP - 4tCYCP - ns tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx - 12.5 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock L pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns 5 - 5 - ns Parameter Symbol Pin Name Serial clock cycle time tSCYC SCK↑→SOT delay time Conditions Internal shift clock operation 14 12.5* Unit External shift clock operation SIN→SCK↓ setup time tIVSLE SCKx, SINx SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − − − − These characteristics only guarantee the following pins. No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 001-98943 Rev.*F Page 122 of 164 S6E2H Series tSCYC VOH SCK VOL SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH VIH SCK SOT VIL V VIL IH tF *V VIH tSHOVE tR VOH VOL OH VOL tIVSLE SIN tSHSL tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 001-98943 Rev.*F Page 123 of 164 S6E2H Series High-speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5 V VCC ≥ 4.5 V Min Max Min Max SCKx 4tCYCP - 4tCYCP - ns tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock L pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Parameter Symbol Pin Name Internal shift clock operation tSCYC SCK↓→SOT delay time Conditions Internal shift clock operation External shift clock operation 14 12.5* Unit Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − − − − These characteristics only guarantee the following pins. No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 001-98943 Rev.*F Page 124 of 164 S6E2H Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL VIH tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 001-98943 Rev.*F Page 125 of 164 S6E2H Series When Using High-speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↓setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time SCS↑→SOT delay time Conditions Internal shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*3)-20 +5tCYCP 3tCYCP+15 (*2)+20 (*3)+20 +5tCYCP - (*2)+0 (*3)-20 +5tCYCP 3tCYCP+15 (*2)+20 (*3)+20 +5tCYCP - ns ns ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns tDSE - 25 - 25 ns tDEE 0 - 0 - ns External shift clock operation (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 126 of 164 S6E2H Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 001-98943 Rev.*F Page 127 of 164 S6E2H Series When Using High-speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↑setup time tCSSI SCK↓→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↑setup time tCSSE SCK↓→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*3)-20 +5tCYCP 3tCYCP+15 (*2)+20 (*3)+20 +5tCYCP - (*2)+0 (*3)-20 +5tCYCP 3tCYCP+15 (*2)+20 (*3)+20 +5tCYCP - ns ns ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 128 of 164 S6E2H Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 001-98943 Rev.*F Page 129 of 164 S6E2H Series When Using High-speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCS↑→SCK↓setup time Symbol Conditions tCSSI SCK↑→SCS↓ hold time tCSHI SCS deselect time tCSDI Internal shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+20 (*3)+20 +5tCYCP - (*2)+0 (*3)-20 +5tCYCP 3tCYCP+15 (*2)+20 (*3)+20 +5tCYCP - ns SCS↑→SCK↓setup time tCSSE (*2)+0 (*3)-20 +5tCYCP 3tCYCP+15 SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns External shift clock operation ns ns SCS deselect time tCSDE SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 130 of 164 S6E2H Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 001-98943 Rev.*F Page 131 of 164 S6E2H Series When Using High-speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↑→SCK↑setup time tCSSI SCK↓→SCS↓ hold time tCSHI SCS deselect time tCSDI Conditions Internal shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+20 (*3)+20 +5tCYCP - (*2)+0 (*3)-20 +5tCYCP 3tCYCP+15 (*2)+20 (*3)+20 +5tCYCP - ns SCS↑→SCK↑setup time tCSSE (*2)+0 (*3)-20 +5tCYCP 3tCYCP+15 SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns External shift clock operation ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 1. S6E2H Series Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 001-98943 Rev.*F Page 132 of 164 S6E2H Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 001-98943 Rev.*F Page 133 of 164 S6E2H Series External Clock (EXT = 1): when in Asynchronous Mode Only (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time tSLSH tSHSL tF tR Condition CL = 30 pF tR SCK Document Number: 001-98943 Rev.*F Value Min Max tCYCP + 10 tCYCP + 10 5 5 tSHSL VIL VIH Unit ns ns ns ns tF tSLSH VIH VIL Remarks VIL VIH Page 134 of 164 S6E2H Series 13.4.12 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol Pin Name Conditions Unit Min Max - 2tCYCP*1 - ns - 2tCYCP*1 2tCYCP + 100*1 500*2 500*3 - ns ns ns ns ADTG Input pulse width tINH, tINL FRCKx ICxx DTTIxX INT00 to INT15, NMIX WKUPx Remarks A/D converter trigger input - Free-run timer input clock Input capture Waveform generator External interrupt, NMI Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see 1. S6E2H Series Block Diagram in this data sheet. *2: When in Stop mode, in timer mode. *3: When in deep standby RTC mode, in deep standby Stop mode. Document Number: 001-98943 Rev.*F Page 135 of 164 S6E2H Series 13.4.13 Quadrature Position/Revolution Counter Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter AIN pin H width AIN pin L width BIN pin H width BIN pin L width BIN rising time from AIN pin H level AIN falling time from BIN pin H level BIN falling time from AIN pin L level AIN rising time from BIN pin L level AIN rising time from BIN pin H level BIN falling time from AIN pin H level AIN falling time from BIN pin L level BIN rising time from AIN pin L level ZIN pin H width ZIN pin L width AIN/BIN rising and falling time from determined ZIN level Determined ZIN level from AIN/BIN rising and falling time Value Symbol Conditions tAHL tALL tBHL tBLL - tAUBU PC_Mode2 or PC_Mode3 tBUAD PC_Mode2 or PC_Mode3 tADBD PC_Mode2 or PC_Mode3 tBDAU PC_Mode2 or PC_Mode3 tBUAU PC_Mode2 or PC_Mode3 tAUBD PC_Mode2 or PC_Mode3 tBDAD PC_Mode2 or PC_Mode3 tADBU PC_Mode2 or PC_Mode3 tZHL tZLL QCR:CGSC="0" QCR:CGSC="0" tZABE QCR:CGSC="1" tABEZ QCR:CGSC="1" Min Max 2tCYCP* - Unit ns *: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 1. S6E2H Series Block Diagram in this data sheet. tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL Document Number: 001-98943 Rev.*F tBLL Page 136 of 164 S6E2H Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN ZIN AIN/BIN Document Number: 001-98943 Rev.*F Page 137 of 164 S6E2H Series 13.4.14 I2C Timing Standard-mode，Fast-mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCL clock frequency (Repeated) Start condition hold time SDA ↓ → SCL ↓ SCL clock L width SCL clock H width (Repeated) Start condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between Stop condition and Start condition fSCL Noise filter Conditions Standard-mode Min Max 0 100 Fast-mode Min Max 0 400 Unit kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs 4.7 - 0.6 - μs 0 3.45* 0 0.9* tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs tSUSTA tHDDAT tSP CL = 30 pF, 1 R = (Vp/IOL)* 2 MHz ≤ tCYCP