DS2408S+T&R;

DS2408 1-Wire 8-Channel Addressable Switch BENEFITS AND FEATURES  Control Eight Independent I/O Port Pins from a Single Micro Port Pin o Eight Channels of Programmable I/O with Open-Drain Outputs o On-Resistance of PIO Pulldown Transistor 100Ω (max); Off-Resistance 10MΩ (typ) o Individual Activity Latches Capture Asynchronous State Changes at PIO Inputs for Interrogation by the Bus Master o Data-Strobe Output to Synchronize PIO Logic States to External Read/Write Circuitry  Minimalist 1-Wire Interface Lowers Cost and Interface Complexity o Built-in Multidrop Controller Ensures Compatibility with Other 1-Wire® Net Products o Supports 1-Wire Conditional Search Command with Response Controlled by Programmable PIO Conditions o Unique Factory-Lasered 64-Bit Registration Number Ensures Error-Free Device Selection and Absolute Part Identity o Communicates to Host with a Single Digital Signal at 15.3kbps or 100kbps  PIN CONFIGURATION 150-mil SO ORDERING INFORMATION PART DS2408S+ DS2408S+T&R TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 16 SO 16 SO +Denotes a lead(Pb)-free package. T&R = Tape and reel. Wide Voltage and Temperature Operating Ranges Enables Robust System Performance o 2.8V to 5.25V o -40°C to +85°C Industrial Temperature Range DESCRIPTION The DS2408 is an 8-channel, programmable I/O 1-Wire chip. PIO outputs are configured as open-drain and provide an on resistance of 100Ω max. A robust PIO channel-access communication protocol ensures that PIO output-setting changes occur error-free. A data-valid strobe output can be used to latch PIO logic states into external circuitry such as a D/A converter (DAC) or microcontroller data bus. DS2408 operation is controlled over the single-conductor 1-Wire bus. Device communication follows the standard Dallas Semiconductor 1-Wire protocol. Each DS2408 has its own unalterable and unique 64-bit ROM registration number that is factory lasered into the chip. The registration number guarantees unique identification and is used to address the device in a multidrop 1-Wire net environment. Multiple DS2408 devices can reside on a common 1-Wire bus and can operate independently of each other. The DS2408 also supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity; the conditions to cause participation in the conditional search are programmable. The DS2408 has an optional VCC supply connection. When an external supply is absent, device power is supplied parasitically from the 1-Wire bus. When an external supply is present, PIO states are maintained in the absence of the 1-Wire bus power source. The RSTZ signal is configurable to serve as either a hard-wired reset for the PIO output or as a strobe for external circuitry to indicate that a PIO write or PIO read has completed. 1-Wire is a registered trademark of Maxim Integrated Products, Inc. 1 of 39 19-5702; 3/15 DS2408 ABSOLUTE MAXIMUM RATINGS* P0 to P7, RSTZ, I/O Voltage to GND P0 to P7, RSTZ, I/O combined sink current Operating Temperature Range Junction Temperature Storage Temperature Range Lead temperature (soldering 10s) Soldering Temperature (reflow) * -0.5V, +6V 20mA -40°C to +85°C +150°C -55°C to +125°C +300°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ELECTRICAL CHARACTERISTICS (VCC = 0V or ≥ VPUP, TA = -40°C or +85°C.) PARAMETER SYMBOL CONDITIONS 1-Wire Pullup Standard speed VPUP Voltage Overdrive speed Standby Supply VCC at VPUP, ICCS Current I/O pin at 0.3V I/O Pin General Data 1-Wire Pullup RPUP (Notes 1, 2) Resistance Input Capacitance CIO (Notes 3, 4) I/O pin at VPUP, Input Load Current IL VCC at 0V High-to-Low VTL (Notes 4, 5, 6) Switching Threshold Input-Low Voltage VIL (Notes 1, 7) Low-to-High VTH (Notes 4, 5, 8) Switching Threshold Switching Hysteresis VHY (Notes 9, 4) Output-Low Voltage VOL (Note 10) at 4mA Standard speed, RPUP = 2.2kΩ Overdrive speed, RPUP = Recovery Time tREC 2.2kΩ (Note 1) Overdrive speed, Directly prior to reset pulse; RPUP = 2.2kΩ Rising-Edge Hold-off Standard speed tREH Time (Notes 11, 4) Overdrive speed Timeslot Duration Standard speed tSLOT (Notes 1, 12) Overdrive speed 2 of 39 MIN 2.8 3.3 MAX 5.25 5.25 UNITS 1 µA 2.2 kΩ 1200 pF 1 µA 3.2 V 0.30 V 0.8 3.4 V 0.16 0.73 V 0.4 V 0.5 TYP V 5 2 µs 5 0.5 0.5 65 10 5 2 µs µs DS2408 PARAMETER SYMBOL CONDITIONS I/O Pin, 1-Wire Reset, Presence-Detect Cycle Standard speed, VPUP > 4.5V Reset-Low Time tRSTL (Notes 1, 12) Standard speed Overdrive speed Standard speed Presence-Detect High tPDH Time (Note 12) Overdrive speed Standard speed, VPUP > 4.5V Presence-Detect Fall tFPD Time (Note 13) Standard speed Overdrive speed Standard speed, VPUP > 4.5V Presence-Detect Low tPDL Time (Note 12) Standard speed Overdrive speed Standard speed, VPUP > 4.5V Presence-Detect tMSP Sample Time (Note 1) Standard speed Overdrive speed I/O Pin, 1-Wire Write Write-0 Low Time Standard speed tW0L (Notes 1, 12, 14) Overdrive speed Write-1 Low Time Standard speed tW1L (Notes 1, 12, 14) Overdrive speed Write Sample Time Standard speed (Slave Sampling) tSLS Overdrive speed (Note 12) I/O Pin, 1-Wire Read Read-Low Time Standard speed t RL (Notes 1, 15) Overdrive speed Read-0 Low Time Standard speed (Data From Slave) tSPD Overdrive speed (Note 12) Read-Sample Time Standard speed tMSR (Notes 1, 12, 15) Overdrive speed P0 to P7, RSTZ Pin Input-Low Voltage VIL (Notes 1, 7) VX = max (VPUP,VCC) Input-High Voltage VIH (Note 1) Output-Low Voltage VOL (Note 10) at 4mA Leakage Current ILP 5.25V at the pin Output Fall Time tFPIO (Notes 4, 16) Minimum-Sensed tPWMIN (Notes 4, 17) PIO Pulse 3 of 39 MIN TYP MAX UNITS 480 720 660 53 15 2 720 80 60 7 1 5 1 8 1 60 240 60 7 280 27 65 75 68 8 75 9 60 8 5 1 15 120 13 15 1.8 60 1.8 8 5 1 15 15 - δ 1.8 - δ 60 1.8 8 tRL + δ tRL + δ 15 1.8 µs 0.30 V 5.25 V 0.4 V 1 µA ns 5 µs VX - 0.8 100 1 µs µs µs µs µs µs µs µs µs µs DS2408 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18: System Requirement Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. If a 2.2kΩ resistor is used to pull up the data line to VPUP, 5µs after power has been applied, the parasite capacitance does not affect normal communications. Guaranteed by design—not production tested. VTL and VTH are functions of the internal supply voltage, which in parasitic power mode, is a function of VPUP and the 1-Wire recovery times. The VTH and VTL maximum specifications are valid at VPUP = 5.25V. In any case, VTL < VTH < VPUP. Voltage below which, during a falling edge on I/O, a logic '0' is detected. The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low. Voltage above which, during a rising edge on I/O, a logic '1' is detected. After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be detected as logic '0'. The I-V characteristic is linear for voltages less than 1V. The earliest recognition of a negative edge is possible at tREH after VTH has been reached before. Highlighted numbers are NOT in compliance with the published 1-Wire standards. See comparison table below. Interval during the negative edge on I/O at the beginning of a presence detect pulse between the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of VPUP. ε in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε respectively. δ in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of VPUP. PIO pullup resistor = 2.2kΩ. Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset (for the RSTZ pin). For a pulse duration tPW: If tPW < tPWMIN(min), the pulse will be rejected. If tPWMIN(min) < tPW < tPWMIN(max), the pulse may or may not be rejected. If tPW > tPWMIN(max) the pulse will be recognized and latched. Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined. No requirement for current balance among different pins. 4 of 39 DS2408 STANDARD VALUES DS2408 VALUES PARAMETER STANDARD OVERDRIVE STANDARD OVERDRIVE NAME SPEED SPEED SPEED SPEED MIN MAX MIN MAX MIN MAX MIN MAX tSLOT (incl. tREC) 61µs (undef.) 7µs (undef.) 65µs 1) (undef.) 10µs (undef.) tRSTL 480µs (undef.) 48µs 80µs 660µs 720µs 53µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 60µs 2µs 7µs tPDL 60µs 240µs 8µs 24µs 60µs 280µs 7µs 27µs tW0L 60µs 120µs 6µs 16µs 60µs 120µs 8µs 13µs tSLS, tSPD 15µs 60µs 2µs 6µs 15µs 60µs 1.8µs 8µs 1) Intentional change, longer recovery-time requirement due to modified 1-Wire front end. PIN DESCRIPTION PIN 1 NAME N.C. 2 P0 3 VCC 4 5 6 7 8 9 I/O GND N.C. P7 P6 P5 10 RSTZ 11 12 13 14 15 16 P4 P3 P2 P1 N.C. N.C. DESCRIPTION Not Connected I/O Pin of Channel 0. Logic input/open-drain output with 100Ω maximum on-resistance; 0V to 5.25V operating range. Power-on default is indeterminate. If it is application-critical for the outputs to power up in the "off" state, the user should attach an appropriate power-on-reset circuit or supervisor IC to the RSTZ pin. Optional Power Supply Input. Range 2.8V to 5.25V; must be tied to GND if not used. 1-Wire Interface. Open-drain, requires external pullup resistor. Ground Not Connected I/O Pin of Channel 7. Same characteristics as P0. I/O Pin of Channel 6. Same characteristics as P0. I/O Pin of Channel 5. Same characteristics as P0. SW configurable PIO reset input ( RST ) or open-drain strobe output ( STRB ). When configured as RST , a LOW input sets all PIO outputs to the "off" state by setting all bits in the PIO Output Latch State Register. When configured as STRB , an output strobe will occur after a PIO write (see Channel-Access Write command) or after a PIO Read (see ChannelAccess Read command). The power-on default function of this pin is RST . I/O pin of channel 4; same characteristics as P0 I/O pin of channel 3; same characteristics as P0 I/O pin of channel 2; same characteristics as P0 I/O pin of channel 1; same characteristics as P0 Not connected Not connected 5 of 39 DS2408 APPLICATION The DS2408 is a multipurpose device. Typical applications include port expander for microcontrollers, remote multichannel sensor/actuator, communication and control unit of a microterminal, or as network interface of a microcontroller. Typical application circuits and communication examples are found later in this data sheet (Figures 17 to 22). OVERVIEW Figure 1 shows the relationships between the major function blocks of the DS2408. The device has two main data components: 1) 64-bit lasered ROM, and 2) 64-bit register page of control and status registers. Figure 2 shows the hierarchical structure of the 1-Wire protocol. The bus master must first provide one of the eight ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM, 7) Overdrive-Match ROM, or 8) Resume. Upon completion of an Overdrive ROM command byte executed at standard speed, the device will enter overdrive mode, where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 12. After a ROM function command is successfully executed, the control functions become accessible and the master may provide any one of the five available commands. The protocol for these control commands is described in Figure 8. All data is read and written least significant bit first. Figure 1. DS2408 BLOCK DIAGRAM VCC I/O PARASITE POWER INTERNAL VCC 1-WIRE FUNCTION CONTROL 64-BIT LASERED ROM REGISTER FUNCTION CONTROL PORT FUNCTION CONTROL GND CRC16 GENERATOR PORT INTERFACE REGISTER PAGE 6 of 39 RSTZ P0 P1 P2 P3 P4 P5 P6 P7 DS2408 Figure 2. HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL 1-Wire Net Bus Master Other Devices DS2408 Command Level: Available Commands: 1-Wire ROM Function Commands DS2408-Specific Control Function Commands Cmd. Data Field Codes: Affected: Read ROM Match ROM Search ROM Skip ROM Conditional Search ROM Overdrive Match Overdrive Skip Resume 33h 55h F0h CCh ECh 69h 3Ch A5h 64-BIT ROM, RC-FLAG 64-BIT ROM, RC-FLAG 64-BIT ROM, RC-FLAG RC-FLAG 64-BIT ROM, RC-FLAG, Port Status, Cond. Search Settings, 64-BIT ROM, RC-FLAG, OD-Flag RC-FLAG, OD-Flag RC-FLAG Read PIO Registers Channel Access Read Channel Access Write Write Conditional Search Register Reset Activity Latches F0h F5h 5Ah CCh PIO Registers Port Input Latches Port Output Latches Conditional Search Register C3h Activity Latches PARASITE POWER The DS2408 can derive its power entirely from the 1-Wire bus by storing energy on an internal capacitor during periods of time when the signal line is high. During low times the device continues to operate from this “parasite” power source until the 1-Wire bus returns high to replenish the parasite (capacitor) supply. If power is available, the VCC pin should be connected to the external voltage supply. Figure 3. 64-BIT LASERED ROM MSB LSB 8-BIT CRC CODE MSB LSB 8-BIT FAMILY CODE (29h) 48-BIT SERIAL NUMBER MSB LSB MSB LSB 64-BIT LASERED ROM Each DS2408 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is available in Application Note 27. 7 of 39 DS2408 The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a time is shifted in. After the eighth bit of the family code has been entered, the serial number is entered. After the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC returns the shift register to all 0s. Figure 4. 1-Wire CRC GENERATOR 8 5 4 POLYNOMIAL = X + X + X + 1 st nd 1 STAGE X 0 rd 2 STAGE X 1 th 3 STAGE X 2 th 4 STAGE X 3 th 5 STAGE X 4 th 6 STAGE X 5 th 7 STAGE X 6 8 STAGE X 7 X 8 INPUT DATA REGISTER ACCESS The registers needed to operate the DS2408 are organized as a Register Page, as shown in Figure 5. All registers are volatile, i. e., they lose their state when the device is powered down. PIO, Conditional Search, and Control/Status registers are read/written using the device level Read PIO Registers and Write Conditional Search Register commands described in subsequent sections and Figure 8 of this document. Figure 5. DS2408 REGISTER ADDRESS MAP ADDRESS RANGE ACCESS TYPE DESCRIPTION 0000h to 0087h R Undefined Data 0088h R PIO Logic State 0089h R PIO Output Latch State Register 008Ah R PIO Activity Latch State Register 008Bh R/W Conditional Search Channel Selection Mask 008Ch R/W Conditional Search Channel Polarity Selection 008Dh R/W Control/Status Register 008Eh to 008Fh R These Bytes Always Read FFh 8 of 39 DS2408 PIO Logic-State Register The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as STRB . See the Channel-Access commands description for details on STRB . PIO Logic State Register Bitmap ADDR 0088h b7 P7 b6 P6 b5 P5 b4 P4 b3 P3 b2 P2 b1 P1 b0 P0 This register is read-only. Each bit is associated with the pin of the respective PIO channel as shown in Figure 6. The data in this register is sampled at the last (most significant) bit of the byte that proceeds reading the first (least significant) bit of this register. See the Read PIO Registers command description for details. PIO Output Latch State Register The data in this register represents the latest data written to the PIO through the Channel-access Write command. This register is read using the Read PIO Registers command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as STRB . See the Channel-access commands description for details on STRB . This register is not affected if the device reinitializes itself after an ESD hit. PIO Output Latch State Register Bitmap ADDR 0089h b7 PL7 b6 PL6 b5 PL5 b4 PL4 b3 PL3 b2 PL2 b1 PL1 b0 PL0 This register is read-only. Each bit is associated with the output latch of the respective PIO channel as shown in Figure 6. The flip-flops of this register will power up in a random state. If the chip has to power up with all PIO channels off, a LOW pulse must be generated on the RSTZ pin, e.g., by means of an open-drain CPU supervisor chip (see Figure 20). When using an RC circuit to generate the power-on reset, make sure that RSTZ is NOT configured as strobe output (ROS bit in control/status register 008Dh needs to be 0). PIO Activity Latch State Register The data in this register represents the current state of the PIO activity latches. This register is read using the Read PIO Registers command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as STRB . See the Channel-access commands description for details on STRB . PIO Activity Latch State Register Bitmap ADDR 008Ah b7 AL7 b6 AL6 b5 AL5 b4 AL4 b3 AL3 b2 AL2 b1 AL1 b0 AL0 This register is read-only. Each bit is associated with the activity latch of the respective PIO channel as shown in Figure 6. This register is cleared to 00h by a power-on reset, by a low pulse on the RSTZ pin (only if RSTZ is configured as RST input), or by successful execution of the Reset Activity Latches command. 9 of 39 DS2408 Figure 6. CHANNEL I/O AND RSTZ SIMPLIFIED LOGIC DIAGRAM TO PIO LOGIC STATE REGISTER PIO ACTIVITY LATCH "1" TO ACTIVITY LATCH STATE REGISTER D Q POWER ON RESET CHANNEL I/O PIN Q R CLR ACT LATCH EDGE DETECTOR TO PIO OUTPUT LATCH STATE REG. DATA D CLOCK S Q Q PIO OUTPUT LATCH RSTZ PIN PORT FUNCTION CONTROL ROS STRB Conditional Search Channel Selection Mask Register The data in this register controls whether a PIO channel qualifies for participation in the conditional search command. To include one or more of the PIO channels, the bits in this register that correspond to those channels need to be set to 1. This register can only be written through the Write Conditional Search Registers command. Conditional Search Channel Selection Mask Register Bitmap ADDR 008Bh b7 SM7 b6 SM6 b5 SM5 b4 SM4 b3 SM3 b2 SM2 b1 SM1 b0 SM0 This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7. This register is cleared to 00h by a power-on reset 10 of 39 DS2408 Conditional Search Channel Polarity Selection Register The data in this register specifies the polarity of each selected PIO channel for the device to respond to the conditional search command. Within a PIO channel, the data source may be either the channel's input signal (pin) or the channel's activity latch, as specified by the PLS bit in the Control/Status register at address 008Dh. This register can only be written through the Write Conditional Search Registers command. Conditional Search Channel Polarity Selection Register Bitmap ADDR 008Ch b7 SP7 b6 SP6 b5 SP5 b4 SP4 b3 SP3 b2 SP2 b1 SP1 b0 SP0 This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7. This register is cleared to 00h by a power-on reset. Figure 7. Conditional Search Logic PLS CHANNEL 0 SP0 SM0 CT AL0 P0 INPUT FROM CHANNELS 1 TO 6 (NOT SHOWN) CHANNEL 7 SP7 SM7 AL7 P7 11 of 39 CSR DS2408 Control/Status Register The data in this register reports status information, determines the function of the RSTZ pin and further configures the device for conditional search. This register can only be written through the Write Conditional Search Registers command. Control/Status Register Bitmap ADDR 008Dh b7 VCCP b6 0 b5 0 b4 0 b3 PORL b2 ROS b1 CT b0 PLS This register is read/write. Without VCC supply, this register reads 08h after a power-on reset. The functional assignments of the individual bits are explained in the table below. Bits 4 to 6 have no function; they will always read 0 and cannot be set to 1. Control/Status Register Details BIT DESCRIPTION PLS: Pin or Activity Latch Select BIT(S) b0 CT: Conditional Search Logical Term b1 ROS: RSTZ Pin Mode Control b2 PORL: Power-On Reset Latch b3 VCCP: VCC Power Status (Read-Only) b7 DEFINITION Selects either the PIO pins or the PIO activity latches as input for the conditional search. 0: pin selected (default) 1: activity latch selected Specifies whether the data of two or more channels needs to be OR’ed or AND’ed to meet the qualifying condition for the device to respond to a conditional search. If only a single channel is selected in the channel selection mask (008Bh) this bit is a don't care. 0: bitwise OR (default) 1: bitwise AND Configures RSTZ as either RST input or STRB output 0: configured as RST input (default) 1: configured as STRB output Specifies whether the device has performed a power-on reset. This bit can only be cleared to 0 under software control. As long as this bit is 1 the device will always respond to a conditional search. For VCC powered operation the VCC pin needs to be tied to a voltage source ≥ VPUP. 0: VCC pin is grounded 1: VCC -powered operation The interaction of the various signals that determine whether the device responds to a conditional search is illustrated in Figure 7. The selection mask SM selects the participating channels. The polarity selection SP determines for each channel whether the channel signal needs to be 1 or 0 to qualify. The PLS bit determines whether all channel signals are taken from the activity latches or I/O pins. The signals of all channels are fed into an AND gate as well as an OR gate. The CT bit finally selects the AND’ed or OR’ed result as the conditional search response signal CSR. Note on CT bit: OR The qualifying condition is met if the input (pin state or activity latch) for one or more selected channels matches the corresponding polarity. AND For the qualifying condition to be met, the input (pin state or activity latch) for every selected channel must match the corresponding polarity. 12 of 39 DS2408 Figure 8-1. CONTROL FUNCTIONS FLOW CHART From ROM Functions Flow Chart (Figure 12) Bus Master TX Control Function Command F0h Read PIO Reg.? To Figure 8 nd 2 Part N Note: To read the three PIO state and latch register bytes, the target address should be 0088h. Returned data for a target address