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DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
General Description
The DS28E38 is an ECDSA public key-based secure
authenticator that incorporates Maxim’s patented
ChipDNA™ PUF technology. ChipDNA technology
involves a physically unclonable function (PUF) that
enables the DS28E38 to deliver cost-effective protection against invasive physical attacks. Using the random
variation of semiconductor device characteristics that
naturally occur during wafer fabrication, the ChipDNA
circuit generates a unique output value that is repeatable
over time, temperature, and operating voltage. Attempts
to probe or observe ChipDNA operation modifies the
underlying circuit characteristics, preventing discovery
of the unique value used by the chip cryptographic functions. The DS28E38 utilizes the ChipDNA output as key
content to cryptographically secure all device stored data
and optionally, under user control, as the private key for
the ECDSA signing operation. With ChipDNA capability, the device provides a core set of cryptographic tools
derived from integrated blocks including an asymmetric
(ECC-P256) hardware engine, a FIPS/NIST-compliant
true random number generator (TRNG), 2Kb of secured
EEPROM, a decrement-only counter and a unique 64-bit
ROM identification number (ROM ID). The ECC public/
private key capabilities operate from the NIST-defined
P-256 curve to provide a FIPS 186-compliant ECDSA
signature generation function. The unique ROM ID is
used as a fundamental input parameter for cryptographic
operations and serves as an electronic serial number
within the application. The DS28E38 communicates over
the single-contact 1-Wire® bus at both standard and
overdrive speeds. The communication follows the 1-Wire
protocol with the ROM ID acting as node address in the
case of a multidevice 1-Wire network.
Benefits and Features
●● Robust Countermeasures Protect Against Security
Attacks
• Patented Physically Unclonable Function Secures
Device Data
• Actively Monitored Die Shield Detects and Reacts
to Intrusion Attempts
• All Stored Data Cryptographically Protected from
Discovery
●● Efficient Public-Key Authentication Solution to
Authenticate Peripherals
• FIPS 186-Compliant ECDSA P256 Signature for
Challenge/Response Authentication
• Options for ECDSA Public/Private Key Pair Source
Include ChipDNA Generated, Chip Computed, and
User Installed
• TRNG with NIST SP 800-90B Compliant Entropy
Source
●● Supplemental Features Enable Easy Integration into
End Applications
• 17-Bit One-Time Settable, Nonvolatile DecrementOnly Counter with Authenticated Read
• 2Kbits of EEPROM for User Data, Key, Control
Registers, and Certificate
• Unique and Unalterable Factory Programmed
64-Bit Identification Number (ROM ID)
• Single-Contact, 1-Wire Interface Communication
with Host at 11.7kbps and 62.5kbps
• Operating Range: 3.3V ±10%, -40°C to +85°C
• 6-Pin TDFN-EP Package (3mm x 3mm)
• 2-Pad SFN Package (3.5mm x 6.5mm)
Ordering Information appears at end of data sheet.
Applications
●● Authentication of Medical Sensors and Tools
●● Secure Management of Limited Use Consumables
●● IoT Node Authentication
●● Peripheral Authentication
●● Reference Design License Management
●● Printer Cartridge Identification and Authentication
19-100093; Rev 2; 5/20
DeepCover and 1-Wire are registered trademarks and
ChipDNA is a trademark of Maxim Integrated Products, Inc.
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Typical Application Circuit
VCC
100kΩ
VCC
PIOX
Q1
1kΩ
RPUP
*PMV65XP
PIOY
DS28E38
BIDIRECTIONAL
OPEN DRAIN PORT
VCC
IO
CEXT
GND
CX
µC
Rp
I2C
PORT
GND
VCC
SDA
SCL
PIOA
PIOB
DS2476
IO
IO
*NOTE: USE A Q1 LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY.
www.maximintegrated.com
Maxim Integrated │ 2
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to GND...........-0.5V to 4.0V
Maximum Current into Any Pin........................... -20mA to 20mA
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -40°C to +125°C
Lead temperature (soldering, 10s)................................... +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
6 TDFN-EP
Package Code
T633+2
Outline Number
21-0137
Land Pattern Number
90-0058
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA)
55ºC/W
Junction to Case (θJC)
9ºC/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
42ºC/W
Junction to Case (θJC)
9ºC/W
2 SFN
Package Code
T23A6N+1
Outline Number
21-0575
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2.97
3.3
MAX
UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
VPUP
System requirement
1-Wire Pullup Resistance
RPUP
(Note 1)
Input Capacitance
CIO
(Notes 1, 2)
Capacitor External
CX
System requirement. IO pin at VPUP
(Note 3)
Input Load Current
IL
IO pin at VPUP
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3.63
V
1000
Ω
0.1 +
CX
399.5
nF
470
540.5
nF
10
360
µA
Maxim Integrated │ 3
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
High-to-Low Switching
Threshold
VTL
(Notes 4, 5)
Input Low Voltage
VIL
(Note 6)
Low-to-High Switching
Threshold
VTH
(Notes 4, 7)
0.75 x
VPUP
Switching Hysteresis
VHY
(Notes 4, 8)
0.3
Output Low Voltage
VOL
IOL = 4mA (Note 9)
MAX
0.65 x
VPUP
UNITS
V
0.10 x
VPUP
V
V
V
0.4
V
IO PIN: 1-Wire INTERFACE
Standard speed, RPUP = 1000Ω
Recovery Time (Note 9)
tREC
Rising-Edge Hold-Off
(Note 11)
tREH
Time Slot Duration
(Note 12)
tSLOT
25
Overdrive speed, RPUP = 1000Ω
10
Directly prior to reset pulse: RPUP = 1000Ω
100
Applies to standard speed only
μs
1
Standard speed
85
Overdrive speed
16
μs
μs
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time
tRSTL
Reset High Time
(Note 13)
tRSTH
Presence-Detect Sample
Time (Note 14)
tMSP
System requirement, standard speed
480
640
System requirement, overdrive speed
48
80
Standard speed
480
Overdrive speed
48
Standard speed
60
75
Overdrive speed
6
10
Standard speed
60
120
Overdrive speed
6
15.5
Standard speed
0.25
15
Overdrive speed
0.25
2
Standard speed
0.25
15 - δ
Overdrive speed
0.25
2-δ
Standard speed
tRL + δ
15
Overdrive speed
tRL+ δ
2
μs
μs
μs
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Note 15)
tW0L
Write-One Low Time
(Note 15)
tW1L
μs
μs
IO PIN: 1-Wire READ
Read Low Time (Note 16)
tRL
Read Sample Time
(Note 16)
tMSR
μs
μs
STRONG PULLUP OPERATION
Strong Pullup Current
ISPU
(Note 17)
Strong Pullup Voltage
VSPU
(Note 17)
Read Memory
www.maximintegrated.com
tRM
10
2.8
mA
V
30
ms
Maxim Integrated │ 4
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. )
PARAMETER
Write Memory
SYMBOL
CONDITIONS
MIN
tWM
TYP
MAX
UNITS
65
ms
Write State
tWS
15
ms
Generate ECC Key Pair
tGKP
200
ms
Generate ECDSA
Signature
tGES
130
ms
TRNG On-Demand
Check
tODC
20
ms
EEPROM
Write/Erase Cycles
(Endurance)
NCY
(Notes 18, 19)
Data Retention
tDR
TA = +85ºC (Notes 20, 21, 22)
100K
10
years
Note 1: System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system
and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire
recovery times.
Note 2: Value represents the typical parasite capacitance when VPUP is first applied. Once the parasite capacitance is charged,
it does not affect normal communication. Typically, during normal communication, the parasite capacitance is effectively
~100pF.
Note 3: Capacitor External parameter does not apply to the 2 SFN package, which incorporates a built-in capacitor.
Note 4: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of
VTL, VTH, and VHY.
Note 5: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 6: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic-zero level.
Note 7: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 8: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic-zero.
Note 9: The I-V characteristic is linear for voltages less than 1V.
Note 10: System requirement. Applies to a single device attached to a 1-Wire line.
Note 11: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Note 12: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 13: An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 14: System requirement. Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E38 present.
The power-up presence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 15: System requirement. ε in Figure 5 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to
VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 16: System requirement. δ in Figure 5 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to
the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 17: Current drawn from IO during a SPU operation interval. The pullup circuit on IO during the SPU operation interval should
be such that the voltage at IO is greater than or equal to VSPUMIN. A low-impedance bypass of RPUP activated during the
SPU operation is the recommended way to meet this requirement.
Note 18: Write-cycle endurance is tested in compliance with JESD47G.
Note 19: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 20: Data retention is tested in compliance with JESD47G.
Note 21: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 22: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated
temperatures is not recommended.
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Maxim Integrated │ 5
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Pin Configuration
TOP VIEW
N.C. 1
IO 2
TOP VIEW
+
1
2
IO
GND
6 CEXT
5 N.C.
DS28E38
4 N.C.
GND 3
SFN
(3.5mm x 6.5mm x 0.75mm)
TDFN-EP
(3mm x 3mm)
Pin Description
DS28E38G+
DS28E38Q+
NAME
—
1, 4, 5
N.C.
1
2
IO
2
3
Ground
—
6
CEXT
—
–
EP
www.maximintegrated.com
FUNCTION
No Connection
1-Wire IO
Ground
Input for External Capacitor
Exposed Pad (TDFN Only). Solder evenly to the board's ground plane
for proper operation. Refer to Application Note 3273: Exposed Pads: A
Brief Introduction for additional information.
Maxim Integrated │ 6
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Detailed Description
Design Resource Overview
The DS28E38 is the first secure authenticator to integrate
the Maxim ChipDNA capability to protect all device stored
data from invasive discovery. Optionally, under user control, the ChipDNA output can also be used as the ECCP256 private key. In addition to the ChipDNA circuit and
ECC-P256 engines for signatures, the device integrates
a FIPS/NIST-compliant TRNG, 2Kb EEPROM for user
memory, ECC key set, control registers, and certificates.
One user page can optionally be designated as a
decrement-only counter. The device operates from a
1-Wire interface with external parasitic supply by way of
an external capacitor (CX). Figure 1 shows the relationships between the circuit elements of the DS28E38.
PARASITE
POWER
Operation of the DS28E38 involves use of device EEPROM
and execution of device function commands. The following
provides an overview including the decrement counter.
Refer to the DS28E38 Security User Guide for details.
Memory
A 2Kb secured EEPROM array provides storage options for
an ECDSA key pair and certificate, a decrement counter,
and/or general-purpose, user-programmable memory.
Depending on the memory space, there are either default
or user-programmable options to set protection modes.
CX
CEXT
64-BIT ROM ID
IO
1-WIRE
INFC
&
CMD
BUFFER
TRNG
ECC-P256
2kb E2 ARRAY
USER MEMORY
KEYS & CERTIFICATE
DECREMENT COUNTER
ChipDNA
PRIVATE KEY
DS28E38
Figure 1. Block Diagram
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Maxim Integrated │ 7
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Function Commands
After a 1-Wire reset/presence cycle and ROM function
command sequence is successful, a command start
can be accepted and then followed by a device function
command. These commands, in general, follow Figure 2.
FROM ROM FUNCTIONS
FLOW CHART
Within this diagram, the data transfer is verified when writing
and reading by a CRC of 16-bit type (CRC-16). The CRC-16
is computed as described in Maxim's Application Note 27:
Understanding and Using Cyclic Redundancy Checks with
Maxim 1-Wire and iButton Products.
66h
COMMAND
START?
MASTER Tx
COMMAND START
N
Y
MASTER Tx INPUT
LENGTH BYTE
MASTER Tx COMMAND BYTE
MASTER Tx
PARAMETER BYTE(S)
MASTER Rx CRC-16 (INVERTED
OF COMMAND START, LENGTH,
COMMAND, AND PARAMETERS)
MASTER Tx RELEASE BYTE
N
SLAVE Rx AAh
RELEASE BYTE?
Y
DELAY WITH STRONG PULLUP
MASTER Rx FFh DUMMY BYTE
MASTER Rx OUTPUT
LENGTH BYTE
MASTER Rx RESULT BYTE
MASTER Rx DATA BYTE(S)
MASTER Rx CRC-16 (INVERTED
OF LENGTH, RESULT, AND DATA)
MASTER
Rx 1s
N
MASTER Tx
RESET?
Y
TO ROM FUNCTIONS
FLOW CHART
Figure 2. Device Function Flow Chart
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Maxim Integrated │ 8
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Decrement Counter
The optional 17-bit decrement counter can be written one
time on a dual-purpose page of memory. A dedicated
device function command is used to decrement the count
value by one with each call. Once the count value reaches
a value of 0, no additional decrements are possible.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS28E38 is
a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing).
The 1-Wire protocol defines bus transactions in terms of
the bus state during specific time slots that are initiated
on the falling edge of sync pulses from the bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus can drive it at the
appropriate time. To facilitate this, each device attached
to the 1-Wire bus must have open-drain or three-state
outputs. The 1-Wire port of the DS28E38 is open drain
with an internal circuit equivalent.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E38 supports both a standard
and overdrive communication speed of 12.5kbps (max)
and 90.9kbps (max), respectively. The value of the pullup
resistor primarily depends on the network size and load
conditions. The DS28E38 requires a pullup resistor of
1kΩ (max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason
a transaction needs to be suspended, the bus must be left
in the idle state if the transaction is to resume. If this does
not occur and the bus is left low for more than 15.5μs
(overdrive speed) or more than 120μs (standard speed),
one or more devices on the bus could be reset.
Transaction Sequence
The protocol for accessing the DS28E38 through the
1-Wire port is as follows:
●● Initialization
●● ROM Function command
●● Device Function command
●● Transaction/data
Initialization
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS28E38 is
on the bus and is ready to operate. For more details, see
the 1-Wire Signaling and Timing section.
VPUP
*SEE NOTE
1-WIRE SLAVE PORT
BUS MASTER
Tx
PIOX
Rx
PIOY
Tx
BIDIRECTIONAL
OPEN-DRAIN PORT
CTL
RPUP
DATA
Rx = RECEIVE
Tx = TRANSMIT
CX
Rx
IL
Tx
100Ω
MOSFET
*NOTE: USE A LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY.
Figure 3. Hardware Configuration
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Maxim Integrated │ 9
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
1-Wire Signaling and Timing
After the bus master has released the line, it goes into
receive mode. Now, the 1-Wire bus is pulled to VPUP
through the pullup resistor or, in the case of a special
driver chip, through the active circuitry. Now, the 1-Wire
bus is pulled to VPUP through the pullup resistor. When
the threshold VTH is crossed, the DS28E38 waits and
then transmits a presence pulse by pulling the line low. To
detect a presence pulse, the master must test the logical
state of the 1-Wire line at tMSP.
The DS28E38 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence
pulse, write-zero, write-one, and read-data. Except for the
presence pulse, the bus master initiates all falling edges.
The DS28E38 can communicate at two speeds: standard
and overdrive. If not explicitly set into the overdrive mode,
the DS28E38 communicates at standard speed. While in
overdrive mode, the fast timing applies to all waveforms.
Immediately after tRSTH has expired, the DS28E38 is
ready for data communication. In a mixed population network, tRSTH should be extended to a minimum 480μs at
standard speed and a 48μs at overdrive speed to accommodate other 1-Wire devices.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from VPUP below the threshold VTL. To get
from active to idle, the voltage needs to rise from VILMAX
past the threshold VTH. The time it takes for the voltage
to make this rise is seen in Figure 4 as ε, and its duration depends on the pullup resistor (RPUP) used and the
capacitance of the 1-Wire network attached. The voltage
VILMAX is relevant for the DS28E38 when determining a
logical level, not triggering any events.
Read/Write Time Slots
Data communication with the DS28E38 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 5 illustrates the
definitions of the write and read time slots.
Figure 4 shows the initialization sequence required to begin
any communication with the DS28E38. A reset pulse followed by a presence pulse indicates that the DS28E38 is
ready to receive data, given the correct ROM and device
function command. If the bus master uses slew-rate control
on the falling edge, it must pull down the line for tRSTL +
tF to compensate for the edge. A tRSTL duration of 480μs
or longer exits the overdrive mode, returning the device to
standard speed. If the DS28E38 is in overdrive mode and
tRSTL is no longer than 80μs, the device remains in overdrive mode. If the device is in overdrive mode and tRSTL is
between 80μs and 480μs, the device resets, but the communication speed is undetermined.
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
the threshold VTL, the DS28E38 starts its internal timing
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line must
have crossed the VTH threshold before the write-one low
time tW1LMAX is expired. For a write-zero time slot, the
voltage on the data line must stay below the VTH threshold
MASTER Tx “RESET PULSE”
MASTER Rx “PRESENCE PULSE”
ε
VPUP
tMSP
VIHMASTER
VTH
VTL
VILMAX
0V
tRSTL
tREC
tF
tRSTH
RESISTOR (RPUP)
MASTER
1-WIRE SLAVE
Figure 4. Initialization Procedure: Reset and Presence Pulse
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Maxim Integrated │ 10
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
until the write-zero low time tW0LMIN is expired. For the
most reliable communication, the voltage on the data line
should not exceed VILMAX during the entire tW0L or tW1L
window. After the VTH threshold has been crossed, the
DS28E38 needs a recovery time tREC before it is ready
for the next time slot.
The sum of tRL + δ (rise time) on one side and the internal
timing generator of the DS28E38 on the other side define
the master sampling window (tMSRMIN to tMSRMAX), in
which the master must perform a read from the data line.
For the most reliable communication, tRL should be as
short as permissible, and the master should read close
to, but no later than tMSRMAX. After reading from the data
line, the master must wait until tSLOT is expired. This
guarantees sufficient recovery time tREC for the DS28E38
to get ready for the next time slot. Note that tREC specified herein applies only to a single DS28E38 attached to a
1-Wire line. For multidevice configurations, tREC must be
extended to accommodate the additional 1-Wire device
input capacitance. Alternatively, an interface that performs
active pullup during the 1-Wire recovery time such as the
special 1-Wire line drivers can be used.
Slave-to-Master
A read-data time slot begins like a write-one time slot. The
voltage on the data line must remain below VTL until the
read low time tRL is expired. During the tRL window, when
responding with a 0, the DS28E38 starts pulling the data
line low; its internal timing generator determines when this
pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28E38 does not hold the data
line low at all, and the voltage starts rising as soon as tRL
is over.
WRITE-ONE TIME SLOT
tW1L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
ε
tSLOT
RESISTOR (RPUP)
MASTER
WRITE-ZERO TIME SLOT
tW0L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
ε
tREC
tSLOT
RESISTOR (RPUP)
MASTER
READ-DATA TIME SLOT
tMSR
tRL
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
MASTER SAMPLING
WINDOW
tF
δ
tREC
tSLOT
RESISTOR (RPUP)
MASTER
1-WIRE SLAVE
Figure 5. Read/Write Timing Diagrams
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Maxim Integrated │ 11
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
1-Wire ROM Commands
long. For operational details, see Figure 6 and Figure 7.
A descriptive list of these ROM function commands follows in the subsequent sections and the commands are
summarized in Table 1.
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that the
DS28E38 supports. All ROM function commands are 8 bits
BUS MASTER Tx
RESET PULSE
FROM DEVICE FUNCTIONS
FLOW CHART
OD
RESET PULSE?
FROM ROM FUNCTION FLOW PART 2
N
OD = 0
Y
SLAVE Tx
PRESENCE PULSE
BUS MASTER Tx
ROM FUNCTION COMMAND
33h
READ ROM
COMMAND?
N
55h
MATCH ROM
COMMAND?
F0h
SEARCH ROM
COMMAND?
N
N
CCh
SKIP ROM
COMMAND?
Y
Y
Y
Y
RC = 0
RC = 0
RC = 0
RC = 0
SLAVE Tx
FAMILY CODE
(1 BYTE)
SLAVE Tx BIT 0
MASTER Tx BIT 0
N
N
Y
BIT 0 MATCH?
Y
SLAVE Tx BIT 1
MASTER Tx BIT 1
SLAVE Tx BIT 1
MASTER Tx BIT 0
Y
BIT 1 MATCH?
N
N
Y
SLAVE Tx
CRC BYTE
TO ROM FUNCTION
FLOW PART 2
SLAVE Tx BIT 0
MASTER Tx BIT 0
BIT 0 MATCH?
SLAVE Tx
SERIAL NUMBER
(6 BYTES)
N
BIT 1 MATCH?
Y
SLAVE Tx BIT 63
MASTER Tx BIT 63
SLAVE Tx BIT 63
MASTER Tx BIT 63
BIT 63 MATCH?
RC = 1
N
N
BIT 63 MATCH?
RC = 1
TO ROM FUNCTION
FLOW PART 2
FROM ROM FUNCTION FLOW PART 2
Figure 6. ROM Function Flow, Part 1
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Maxim Integrated │ 12
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
TO ROM FUNCTION FLOW PART 1
FROM ROM
FUNCTION
FLOW PART 1
A5h
RESUME
COMMAND?
3Ch
OVERDRIVESKIP ROM?
N
Y
RC = 1?
N
Y
N
Y
RC = 0; OD = 1
RC = 0; OD = 1
N
69h
OVERDRIVEMATCH ROM?
MASTER Tx BIT 0
Y
MASTER Tx
RESET?
N
OD = 0
Y
N
MASTER Tx
RESET?
BIT 0 MATCH?
MASTER Tx BIT 1
Y
N
BIT 1 MATCH?
N
OD = 0
Y
SLAVE Tx BIT 63
BIT 63 MATCH?
FROM ROM FUNCTION
FLOW PART 1
N
OD = 0
RC = 1
TO ROM FUNCTION FLOW PART 1
TO DEVICE FUNCTIONS
FLOW CHART
Figure 7. ROM Function Flow, Part 2
Table 1. 1-Wire ROM Commands Summary
ROM FUNCTION COMMAND
CODE
DESCRIPTION
Search ROM
F0h
Search for a device
Read ROM
33h
Read ROM from device (single drop)
Match ROM
55h
Select a device by ROM number
Skip ROM
CCh
Select only device on 1-Wire
Resume
A5h
Selected device with RC bit set
Overdrive Skip ROM
3Ch
Put all devices in overdrive
Overdrive Match ROM
69h
Put the device with the ROM in overdrive
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Maxim Integrated │ 13
DS28E38
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
Search ROM[F0h]
Resume [A5h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a process of elimination to identify the ID of all slave devices.
For each bit in the ID number, starting with the least significant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion, including an example.
To maximize the data throughput in a multidrop environment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the device function commands, similar
to a Skip ROM command. The only way to set the RC bit
is through successfully executing the Match ROM, Search
ROM, or Overdrive-Match ROM command. Once the RC
bit is set, the device can repeatedly be accessed through
the Resume command. Accessing another device on the
bus clears the RC bit, preventing two or more devices from
simultaneously responding to the Resume command.
Read ROM[33h]
The Read ROM command allows the bus master to read
the DS28E38’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
Match ROM[55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28E38 on a multidrop bus. Only the DS28E38 that
exactly matches the 64-bit ROM sequence responds
to the subsequent device function command. All other
slaves wait for a reset pulse. This command can be used
with a single device or multiple devices on the bus.
Skip ROM [CCh]
This command can save time in a single-drop bus system
by allowing the bus master to access the device functions
without providing the 64-bit ROM ID. If more than one
slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wiredAND result).
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Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the device functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM command
sets the DS28E38 into the overdrive mode (OD = 1). All
communication following this command must occur at
overdrive speed until a reset pulse of minimum 480μs
duration resets all devices on the bus to standard speed
(OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search process. If more than one slave supporting overdrive is present on the bus and the Overdrive-Skip ROM command
is followed by a read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (opendrain pulldowns produce a wired-AND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-bit
ROM sequence transmitted at overdrive speed allows the
bus master to address a specific DS28E38 on a multidrop bus and to simultaneously set it in overdrive mode.
Only the DS28E38 that exactly matches the 64-bit ROM
sequence responds to the subsequent device function
command. Slaves already in overdrive mode from a previous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All overdrivecapable slaves return to standard speed at the next reset
pulse of minimum 480μs duration. The Overdrive-Match
ROM command can be used with a single device or multiple devices on the bus.
Maxim Integrated │ 14
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Improved Network Behavior
(Switch-Point Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization with
the master and, consequently, result in a Search ROM
command coming to a dead end or cause a device-specific function command to abort. For better performance
in network applications, the DS28E38 uses a 1-Wire front
end that is less sensitive to noise.
The DS28E38’s 1-Wire front-end has the following features:
●● There is additional lowpass filtering in the circuit that
detects the falling edge at the beginning of a time
slot. This reduces the sensitivity to high-frequency
noise. This additional filtering does not apply at overdrive speed.
●● There is a hysteresis at the low-to-high switching
threshold VTH. If a negative glitch crosses VTH, but
does not go below VTH - VHY, it is not recognized
(Figure 8, Case A). The hysteresis is effective at any
1-Wire speed.
●● There is a time window specified by the rising edge
hold-off time tREH during which glitches are ignored,
even if they extend below the VTH - VHY threshold
(Figure 8, Case B, tGL < tREH). Deep voltage drops
or glitches that appear late after crossing the VTH
threshold and extend beyond the tREH window cannot be filtered out and are taken as the beginning of
a new time slot (Figure 8, Case C, tGL ≥ tREH).
tREH
tREH
VPUP
VTH
VHY
CASE A
CASE B
0V
tGL
CASE C
tGL
Figure 8. Noise Suppression Scheme
Ordering Information
TEMP RANGE
PIN-PACKAGE
DS28E38Q+T
PART
-40°C to +85°C
6 TDFN (2.5k pcs)
DS28E38G+T
-40°C to +85°C
2 SFN (2.5k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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Maxim Integrated │ 15
DeepCover® Secure ECDSA Authenticator
with ChipDNA PUF Protection
DS28E38
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
6/17
Initial release
1
9/17
Updated General Description, Benefits and Features, Electrical Characteristics table,
Detailed Description, and Design Resource Overview sections
1, 4, 5, 7
2
5/20
Updated Benefits and Features, Package Information, Electrical Characteristics table,
and Ordering Information
1, 3–6, 15
DESCRIPTION
—
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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