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MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
General Description
Benefits and Features
The MAX25601A/B/C/D is a synchronous boost controller followed by a synchronous buck LED controller. The
4.5V to 40V input voltage range of the boost controller is
ideal for automotive applications, and acts as a pre-boost
power supply for the second-stage buck LED controller.
The synchronous boost is a current-mode controller
that can be be paralleled with another device to provide
higher output power. A SYNCOUT pin provides the clock
to drive the RT/SYNCIN pin of the other device, enabling
two-phase 180-degree out-of-phase operation. The boost
converter can be programmed with a switching frequency
of 200kHz to 2.2MHz. Spread spectrum is included to
reduce EMI. An internal digital soft-start feature is provided to enable a smooth power up of the boost output.
Protection features like hiccup mode, overvoltage protection, and thermal shutdown are provided.
The synchronous buck LED controller uses Maxim's F3
Architecture, a proprietary average-current-mode control
scheme to regulate the inductor current at a constant
switching frequency without any control-loop compensation. Inductor current is sensed in the bottom synchronous
n-channel MOSFET. The device operates over a wide
4.5V to 65V input range at switching frequencies as high
as 1MHz. Both analog and PWM dimming are included.
LED current can be monitored on the IOUTV pin.
Both controllers have high- and low-side gate drivers
with at least 1A peak source and sink-current capability. Adaptive non-overlap control logic prevents shootthrough currents during transition. Both the boost and the
buck faults are monitored on the FLT pin.
The MAX25601A/C is available in a 32-pin SWTQFN
package and the MAX25601B/D is available in a 28-pin
TSSOP package. The 32-pin package features an
additional switch control that can be used in high-beam/
low-beam and heads-up display applications.
Applications
●● Automotive Exterior Lighting: High-Beam/Low-Beam/
Signal/Position Lights, Daytime Running Lights
(DRLs), Matrix Light, Pixel Light, and Other Adaptive
Front-Light Assemblies
●● Commercial, Industrial, and Architectural Lighting
19-100564; Rev 3; 1/20
●● Integration Minimizes BOM for High-Brightness LED
Driver, Saving Space and Cost
• Wide Input-Voltage Range from 4.5V to 40V
• Wide Boost-Output Range up to 65V
• Programmable Switching Frequency Optimizes
Component Size
• External MOSFETs Can be Sized for Appropriate
Current
• Synchronous Rectification Provides High Efficiency
and Fast Transient Response
• Average Current-Mode Control for Buck Eliminates
Compensation Components
●● Wide Dimming Ratio Allows High Contrast Ratio
• Analog Dimming and PWM Dimming
• Analog Voltage-Controlled PWM Dimming
●● Protection Features and Wide Temperature Range
Increase System Reliability
• Short Circuit, Overvoltage, and Thermal Protection
• -40°C to +125°C Operating Temperature Range
Simplified Application Circuit
N1
CIN
INPUT AND BIAS
INP
INN
OUT, FB
CCOMP
N2
DL1
BOOST
VOUT
MAX25601
N3
DH2
PWM, ANALOG
DIMMING
BUCK TON
SETTING
CBOOST
DH1
LX1
SYNC IN/OUT
FLTB, IOUTV
BOOST
VOUT
LBOOST
RIN
INPUT
LX2
DL2
COMP
N4
LBUCK
CBUCK
CSP
RCS_LED
RCOMP
CSN
SHUNT_DRV*
PWM_HUD
* MAX25601A/C ONLY
BUCK
VOUT
SHUNT_CTRL*
N5
Ordering Information appears at end of data sheet.
BUCK
VOUT
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Absolute Maximum Ratings
IN, UVEN, INP, INN to AGND
(MAX25601A, MAX25601B)...............................-0.3V to +40V
IN, UVEN, INP, INN to AGND
(MAX25601C, MAX25601D)..............................-0.3V to +52V
LX1, TON to PGND................................................-0.3V to +70V
LX2 to PGND............................................................-1V to +70V
BST_ to LX_.............................................................-0.3V to +6V
DH_ to LX_................................................ -0.3V to VBST_ +0.3V
DL_, SHUNT_DRV to PGND.......................-0.3V to VDRV+0.3V
CSP, CSN to PGND.................................................-2.5V to +6V
CSP to CSN, INP to INN.......................................-0.3V to +0.3V
VCC to SGND...............................................-0.3V to VDRV+0.3V
REFI, IOUTV, SYNCOUT to AGND.............-0.3V to VDRV+0.3V
FB, OUT, COMP to AGND...........................-0.3V to VDRV+0.3V
FLT, SHUNT_CTRL, PWMDIM,
RT/SYNCIN to AGND...........................................-0.3V to +6V
VDRV to PGND.......................................................-0.3V to +6V
PGND to AGND.....................................................-0.3V to +0.3V
Continous Power Dissipation (Single-Layer Board),
32 pin SW TQFN T3255Y+6C
(TA = +70°C, derate 21.3mW/°C above +70°C.)........1702mW
Continuous Power Dissipation (Multilayer Board),
32 pin SW TQFN T3255Y+6C
(TA = +70°C, derate 34.5mW/°C above +70°C.)........2759mW
Continuous Power Dissipation (Single-Layer Board),
28 pin TSSOP U28E+1C
(TA = +70°C, derate 22.2mW/°C above +70°C.)........1777mW
Continuous Power Dissipation (Multilayer Board),
28 pin TSSOP U28E+1C (TA = +70°C,
derate 29.7mW/°C above +70°C.).................. mW to 2380mW
Operating Temperature Range.............................-40°C to 125°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
32 pin TQFN
Package Code
T3255Y+6C
Outline Number
21-100041
Land Pattern Number
90-100066
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA)
47°C/W
Junction to Case (θJC)
3°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
36°C/W
Junction to Case (θJC)
3°C/W
28 pin TSSOP
Package Code
U28E+1C
Outline Number
21-100182
Land Pattern Number
90-100069
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA)
45°C/W
Junction to Case (θJC)
2°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
33.6°C/W
Junction to Case (θJC)
3.3°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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Maxim Integrated │ 2
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Electrical Characteristics
(VIN = 12V, VUVEN = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT VOLTAGE
Input Voltage Range
VIN
MAX25601A/MAX25601B
5
36
MAX25601C/MAX25601D
5
48
4.5
5.5
IN connected to VDRV and VCC (external bias)
Quiescent Current
IQ
Shutdown Current
ISHDN
VDIM = 5V, VIN = 12V, VOUT_BOOST = 48V,
boost and buck not switching
5
VDIM = 0V, VIN = 12V, VUVEN = 0V
V
10
mA
12
μA
VCC and VDRV
VDRV Output Voltage
VDRV
VDRV Dropout Voltage
VDRV Short-Circuit Current
IVDRV = 30mA, 5.5V ≤ VIN ≤ 36V
4.95
5.0
5.05
IVDRV = 10mA to 60mA, 6V ≤ VIN ≤ 25V
4.90
5.0
5.10
35
100
IVDRV = 5mA, VIN = 4.5V
VDRVIMAX
VDRV = 4.5V, VIN = 6V
90
V
mV
mA
VDRV Undervoltage
Lockout Rising
VDRVUVLOR
Rising voltage
3.92
V
VDRV Undervoltage
Lockout Falling
VDRVUVLOF
Falling voltage
3.45
V
UV ENABLE
UVEN Threshold
VTH_UVEN
1.12
Hysteresis
1.24
1.37
100
V
mV
FLT
Any boost or buck fault present
FLTLow Voltage
FLTLeakage Current
FLTLK
VFLT = 5.5V, 100kΩ pullup
0.4
V
1
μA
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Rising
Thermal Shutdown Hysteresis
165
°C
10
°C
BUCK / OFF-TIME CONTROL
Minimum Off-Time
tOFF_MIN_
BUCK
VCSP - VCSN = 0V
125
Maximum Off-Time
CS Comparator
Propagation Delay
Linear Range of Pulse
Doubler
www.maximintegrated.com
tCS_DLY
0
200
ns
42
μs
65
ns
5
μs
Maxim Integrated │ 3
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Electrical Characteristics (continued)
(VIN = 12V, VUVEN = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BUCK / ON-TIME CONTROL/OVERVOLTAGE PROTECTION/SHORT FAULT INDICATOR
Minimum On-Time
tON_MIN_BUCK
110
ns
Maximum On-Time
tON_MAX_BUCK TON = GND, VOUT = 1V
24
μs
VIN = 65V, RTON > 20kΩ
15
tON Pulldown
Resistance
tONThreshold to DH
Falling Delay
OUT Overvoltage
Threshold
tON_DLY_BUCK
VTH_OVP_
BUCK
OUT Overvoltage
Hysteresis
Short Fault Threshold
65
OUT rising
2.38
OUT falling
OUTV_SHF
Output falling, VOUT is lower than threshold
VOUT_BUCK = 1V, RTON = 50kΩ, CTON = 1nF
Programmed On-Time
30
2.5
Ω
ns
2.62
V
20
mV
50
mV
4.55
μs
BUCK / ANALOG DIMMING INPUT
REFI Input Voltage
Range
VREFI_RNG
REFI Zero Current
Threshold
VREFI_ZC
Internal REFI Clamp
Voltage
REFI Input Bias Current
0.2
1.2
V
VCSP - VCSN < 5mV
0.16
0.18
0.20
V
VREFI_CLMP
IREFI sink = 1μA
1.254
1.3
1.326
V
IREFI
VREFI = 0 to VCC
20
200
nA
BUCK / BUCK FAULTS
LED Open-Fault Enable
Threshold
LOFREFI_VTH
VREFI greater than this threshold, 50mV (typ)
hysteresis
300
325
350
mV
LED Open-Fault
Detection Threshold
LOFIOUTV_TH
VIOUTV lower than the threshold when DIM is
high
10
25
40
%
BUCK / CURRENT-SENSE AMPLIFIER
Buck Current-Sense
Gain
Buck Current-Sense
Amplifier Offset
CSABUCK
5
VCS_OFS_
0.182
BUCK
0.2
V/V
0.208
V
BUCK / PWM AND ANALOG-TO-PWM DIMMING
DIM Input High
VDIM_IH
DIM Rising
2.0
DIM Input Low
VDIM_IL
DIM Falling
DIM Rising to DL2
Rising Delay
tDIM_RIS
DIM Rising
External DIM Frequency
Range
fDIM_EXT
10
Internal Ramp Frequency
fDIM_INT
180
VDIM_OFS
170
DIM Comparator Offset
Voltage
DIM Voltage for 100%
Duty Cycle
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V
0.8
100
3.2
V
ns
2000
Hz
200
220
Hz
200
230
mV
V
Maxim Integrated │ 4
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Electrical Characteristics (continued)
(VIN = 12V, VUVEN = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
DH2 = high
2.5
5.0
DH2 = low
1.0
2.0
UNITS
BUCK / GATE DRIVERS
DH2 Gate Driver
On-Resistance
DH2 Gate Driver Source/
Sink Current
DL2 Gate Driver
On-Resistance
DL2 Gate Driver Source/
Sink Current
RDH2_SRC
RDH2_SINK
IDH2
RDL2_SRC
RDL2_SINK
TA = -40°C to
+125°C, BST2LX2 forced to 5V
DH2-LX2 forced to 2.5V, BST2-LX2 forced to 5V.
TA = -40°C to
+125°C
1
DL2 to DH2 Deadtime
A
DL2 = high
2.5
5.0
DL2 = low
1.0
3.0
IDL2
DL2 fall to DH2 rise, CL = 1nF
Ω
Ω
1
A
20
ns
BUCK / CURRENT MONITOR (IOUTV)
Current Sense Gain
5
Current Sense Offset
0.182
IOUTV Source/Sink
Current
0.2
0.208
±0.5
V
mA
BOOST / OSCILLATOR
Switching-Frequency
Range
FSW_RNG
Switching Frequency
FSW_BOOST
Set by the RT resistor, 14kΩ < RRT < 171kΩ,
or by an external clock
Spread-Spectrum
Disabled
200
RRT = 85kΩ
370
400
430
RRT = 14kΩ
1980
2200
2365
Spread-Spectrum
Spreading Factor
RT/SYNCIN Regulation
Voltage
Soft-Start Time
tSS
Hiccup Period
thiccup
2200
%
15kΩ < RRT < 171kΩ
1.25
V
Voltage mode soft-start; based on FSW_BOOST
clocks
3712
clocks
Triggers when current limit is reached and
boost output voltage < 70%; based on FSW_
BOOST clocks
21504
clocks
ns
tOFF_MIN_BST
60
Minimum On-Time
tON_MIN_BST
60
VSYNCIN_IL
RT/SYNCIN Input High
VSYNCIN_IH
ns
1
2.5
Phase relation between internal oscillator clock
and SYNCOUT clock
SYNCOUT Clock
kHz
±6
Minimum Off-Time
RT/SYNCIN Input Low
kHz
V
V
180
deg
BOOST / GATE DRIVERS
DH1 Gate Driver
On-Resistance
DH1 Gate Driver Source/
Sink Current
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RDH1_SRC
RDH1_SINK
IDH1
TA = -40°C to
+125°C, BST1LX1 forced to 5V
DH1 = high
1.6
3.2
DH1 = low
1.0
2.0
DH1-LX1 forced to 2.5V, BST1-LX1 forced to 5V
1
Ω
A
Maxim Integrated │ 5
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Electrical Characteristics (continued)
(VIN = 12V, VUVEN = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
DL1 Gate Driver
On-Resistance
SYMBOL
RDL1_SRC
RDL1_SINK
DL1 Gate Driver Source/
Sink Current
CONDITIONS
TA = -40°C to
+125°C
MIN
TYP
MAX
DL1 = high
1.7
3.5
DL1 = low
0.8
1.6
IDL1
UNITS
Ω
1.5
A
DH1 to DL1 Deadtime
DH1 fall to DL1 rise, CL = 5nF
20
ns
DL1 to DH1 Deadtime
DL1 fall to DH1 rise, CL = 5nF
20
ns
BOOST / REGULATION / CURRENT SENSE
Feedback Voltage
VFB
FB Input Current
OVP Threshold
INP-INN Negative
Current-Limit Threshold
Boost Current-Sense
Gain
Boost Current-Sense
Amplifier Offset
Peak Slope-Compensation Ramp Voltage
1.14
Falling voltage
VILIM_BST
VNEG_ILIM_
BST
1.20
1.035
V
+1
µA
1.24
100
Peak current limit
70
With respect to positive current limit
CSABOOST
85
9
11
100
8V ≤ VIN ≤ 20V
RDL2 = 30kΩ
1.39
RDL2 = 100kΩ
2.08
mV
%
12
0.5
BOOST
V
mV
-30
VCS_OFS_
VSC_RAMP
1.01
-1
VTH_OVP_BST
OVP Hysteresis
INP-INN Current-Limit
Threshold
0.990
TA = 25°C
V/V
V
V
BOOST / ERROR AMPLIFLIER
Transconductance
Gm
200
300
400
μS
COMP Source Current
FB = 0V for maximum Gm source current
+92
μA
COMP Sink Current
FB = 2V for Minimum GM sink current
-45
µA
4
V
COMP Clamp Voltage
COMP Output Offset
VCOMP_OFS
1.7
HUD INPUT/OUTPUT (32-pin TQFN Only)
PWM_HUD Input High
VPWM_HUD_IH
PWM_HUD Rising
PWM_HUD Input Low
VPWM_HUD_IL
PWM_HUD Falling
PWM_HUD to HUD_
OUT Delay
tHUD_DLY
HUD_OUT Driver
On-Resistance
PWM_HUD Input
Resistance
RHUD_SRC
RHUD_SNK
2.0
PWM_HUD Rising to HUD_OUT Falling, or
PWM_HUD Falling to HUD_OUT Rising.
CL = 10nF.
TA = -40°C to
+125°C
V
0.8
30
ns
HUD_OUT = high
2.5
5
HUD_OUT = low
1.5
3.0
600
V
Ω
kΩ
Note 1: Limits are 100% tested at TA = +25°C and TA = +125°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization.
www.maximintegrated.com
Maxim Integrated │ 6
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Typical Operating Characteristics
(VIN = 12V, VREFI = 1.2V, VDIM = VCC, CVCC = CVDRV = 4.7µF, TA = +25°C, unless otherwise noted.)
www.maximintegrated.com
Maxim Integrated │ 7
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Typical Operating Characteristics (continued)
(VIN = 12V, VREFI = 1.2V, VDIM = VCC, CVCC = CVDRV = 4.7µF, TA = +25°C, unless otherwise noted.)
PRELIMINARY
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Maxim Integrated │ 8
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Pin Configurations
COMP
VCC
AGND
RT/SYNCIN
SHUNT_CTRL
SYNCOUT
PWMDIM
TOP VIEW
FB
TQFN
24
23
22
21
20
19
18
17
FLT
25
16
TON
SHUNT_DRV
26
15
IOUTV
LX1
27
14
REFI
BST1
28
13
NC
DH1
29
DL1
30
INN
31
INP
32
MAX25601A
MAX25601C
12 CSN
EP
1
2
3
4
5
6
7
8
IN
PGND
VDRV
NC
BST2
DH2
LX2
DL2
+
11
UVEN
10
CSP
9
OUT
TQFN-EP (SW)
(5mm x 5mm)
TSSOP
TOP VIEW
DL1
1
INN
INP
+
28
DH1
2
27
BST1
3
26
LX1
IN
4
25
FLT
PGND
5
24
COMP
23
FB
22
VCC
MAX25601B
MAX25601D
VDRV
6
BST2
7
DH2
8
21
AGND
LX2
9
20
RT/SYNCIN
DL2
10
19
SYNCOUT
OUT
11
18
PWMDIM
CSP
12
17
TON
UVEN
13
16
IOUTV
EP
CSN
REFI
TSSOP-EP
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Maxim Integrated │ 9
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Pin Description
PIN
NAME
FUNCTION
TQFN
TSSOP
1
4
IN
2
5
PGND
Power Ground
3
6
VDRV
+5V Regulator Output and Driver Supply. Connect a 4.7μF ceramic capacitor from
VDRV to PGND. If an external bias is used, then connect IN to VDRV, and connect the
external supply to VDRV.
4
—
NC
5
7
BST2
High-Side Power Supply for High-Side Gate Drive of Buck LED Regulator. Connect
a 0.1μF ceramic capacitor from BST2 to LX2, and a BST diode between VDRV and
BST2.
6
8
DH2
High Side Driver of Buck LED Regulator. Connect to gate of the buck regulator's
high-side n-channel MOSFET. Use series resistor to limit current slew rate and
mitigate EMI noise, if required.
7
9
LX2
Switching Node of Buck LED Regulator
Supply Input for VDRV regulator. Connect a 0.1µF ceramic capacitor from this pin to
PGND. If an external bias is used, then connect IN to VDRV.
Not Internally Connected
Low-Side Driver of Buck LED Regulator. Connect to gate of the buck regulator’s
low-side n-channel MOSFET. Use series resistor to limit current slew rate and
mitigate EMI noise, if necessary.
8
10
DL2
During startup, DL2 is used to select the slope compensation of the boost regulator
based on the following options:
DL2 RESISTOR TO PGND
SLOPE COMPENSATION SELECTION
100kΩ
Larger slope compensation for boost output
voltages greater than 45V
30kΩ
Smaller slope compensation for boost output
voltages less than 45V
9
11
OUT
Feedback Voltage of Buck. Connect a resistor-divider from this pin to the output voltage on buck. This pin has the scaled-down feedback of the output voltage of the buck.
10
12
CSP
Positive Current-Sense Input for Buck Regulator. Connect a resistor from this pin to
CSN to sense the buck regulator inductor current.
11
13
UVEN
12
14
CSN
13
---
NC
14
15
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REFI
Input UVLO and Enable Pin. Dual-function pin to set the input UV threshold, or to use
as an enable input. The UVEN threshold is set at 1.24V (typ).
Negative Current-Sense Input for Buck Regulator
Not Internally Connected
Analog Dimming Input for Buck LED Regulator. The voltage at REFI sets the LED
current.Connect a resistor-divider from VCC to set the default LED current.
Alternatively, drive REFI with an external voltage source for analog dimming.
ILED = (VREFI - 0.2)/(5 x RCS_LED)
Maxim Integrated │ 10
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Pin Description (continued)
PIN
TQFN
TSSOP
15
16
16
17
18
17
18
19
NAME
FUNCTION
IOUTV
Current Monitor output for the Buck LED controller. Connect a 100Ω resistor and 22nF
capacitor from IOUTV to AGND.
VIOUTV = ILED x RCS_LED x 5 + 0.2
TON
Frequency Setting Pin for the Buck. The buck switching frequency is set by a
resistor from the input to the TON pin, a capacitor from the TON pin to AGND, and the
resistor-divider on the OUT pin.
FSW_BUCK = (ROUT2 + ROUT1)/(CTONRTONROUT2)
DIM
Dimming Input for Buck Regulator PWM Dimming.
Direct PWM dimming control: Connect to an external 3.3V or 5V PWM signal, with
DIM frequency between 10Hz and 2kHz.
Analog-to-PWM dimming control: Connect to an analog voltage between 0.2V and 3V
to set the PWM dimming duty cycle using the internal 200Hz clock.
Keep DIM above 3.2V for 100% duty cycle.
SYNCOUT
Sync Clock Output. 180-degree clock signal. Connect SYNCOUT to the RT/SYNCIN
of a second MAX25601A/B/C/D to have it run at 180 degrees out of phase from this
controller.
During startup, SYNCOUT is used to select the master/slave configuration for the
boost regulator based on the following options:
SYNCOUT RESISTOR TO PGND
MASTER/SLAVE CONFIGURATION
35kΩ
Single-phase/dual-phase master
5kΩ
Dual-phase slave
PWM Input for SHUNT_DRV. PWM control input for the shunt driver.
19
—
SHUNT_CTRL
20
20
RT/SYNCIN
21
21
AGND
22
22
VCC
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SHUNT_CTRL
SHUNT_DRV
APPLICATION FUNCTION
Low
High
External FET on. HUD disabled
(dimmed).
High
Low
External FET off. HUD enabled.
Frequency Setting Pin for Boost Regulator. This pin sets the switching frequency of
the boost regulator when driven by an external clock. or by using a resistor to AGND.
When set by an external resistor, the switching frequency follows the equation:
FSW_BOOST = 34.2x109 / (RT + 550)
When using an external clock, drive SYNCIN with a 3.3V or 5V signal, between
200kHz and 2.2MHz, with a minimum off-time of 80ns. To shift SYNCOUT phase 180
degrees from SYNCIN, drive SYNCIN with a 50% duty cycle signal.
Analog Ground Connection. Low-noise ground pin.
Analog Power Supply. Connect to VDRV through a series 10Ω resistor. Bypass VCC to
AGND with a 1μF ceramic capacitor.
Maxim Integrated │ 11
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Pin Description (continued)
PIN
TQFN
TSSOP
NAME
23
23
FB
24
24
COMP
FUNCTION
Feedback Input for the Boost Regulator. FB regulates to 1V, while the boost OVP
threshold at FB is 1.2V. Connect a resistor-divider at FB to set the boost output
voltage.
VOUT_BOOST = VFB (RFB1 + RFB2)/RFB2
VOVP_BOOST = VTH_OVP_BOOST (RFB1 + RFB2)/RFB2
Compensation Pin for the Boost Regulator
25
25
FLT
Fault Output Indicator. Buck and boost faults are reported on this pin. FLTdoes not
change state when DIM is low.
Buck Faults: LED open, LED short, output overvoltage
Boost Fault: Undervoltage
26
---
SHUNT_DRV
Shunt FET Driver Output. Connect SHUNT_DRV to the gate of an n-channel FET
for dimming.
27
26
LX1
28
27
BST1
High-Side Power Supply for High-Side Gate Drive of Boost Regulator. Connect a
0.1μF ceramic capacitor from BST1 to LX1, and a BST diode between VDRV and
BST2.
29
28
DH1
High-Side Driver of Boost Regulator. Connect to the gate of boost regulator's highside n-channel MOSFET. Use series resistor to limit current slew rate and mitigate
EMI noise, if necessary.
30
1
DL1
Low-Side Driver of Boost Regulator. Connect to gate of the boost regulator's low-side
n-channel MOSFET. Use series resistor to limit current slew rate and mitigate EMI
noise, if necessary.
31
2
INN
Negative Current-Sense Input for the Boost Regulator
32
3
INP
Positive Current-Sense Input for the Boost Regulator. The maximum differential
voltage across INP and INN is 80mV (typ), and sets the peak input current limit.
EP
EP
EP
Exposed Pad. Connect EP to a large-area contiguous-copper ground plane for
effective power dissipation. Do not use as the main IC ground connection. EP must
be connected to AGND.
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Switching Node of Boost Controller
Maxim Integrated │ 12
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Functional Block Diagram
BST2
REFI
MAX25601
BUCK
CSA
CSP
CSN
PULSE
DOUBLER
PWM
5X
0.2V
200ms LOW-STATE
TIME COUNTER
ANALOG/
DIGITAL
DETECT
PWMDIM
TON_RESET
11X
SLOPE
SELECT
DL2
DECODE
BUCK CSA
+0.2V
IOUTV
1X
BUCK FAULT
BOOST POK
VDRV_OK
INUVLO
N
BOOST FAULT
SLOPE
SELECT
COMP
VDRV
PWM
FB
BOOST
CONTROL
LOGIC
Gm
S
Q
R
Q
DL1
DEAD
TIME
BST1
DEAD TIME
AND LEVEL
SHIFT UP
3172 CLK SOFTSTART RAMP
IN
DH1
LX1
BOOST OSC
UVEN
VDRV
LDO
INUVLO
TLIM
CNTRL
4V
ALW
ON
VDRV_OK
RT/SYNCIN
TLIM
LDO
BOOST OSC
MASTER/SLAVE
SELECT
OSC
SYNCOUT
SYNCOUT
DECODE
VDRV
VCC
AGND
DL2
DEAD
TIME
FLT
250mV
REF
LX2
3.0V
BOOST
CSA
BOOST OSC +
SLOPE COMP
Q
DL2 ENABLE
N
OUT
INP
R
BUCK
CONTROL
LOGIC
BUCK
OV
INN
Q
DH2
VDRV
SHUTDOWN
MODE
TON_RESET
TON
S
DEAD TIME
AND LEVEL
SHIFT UP
REF
GEN
EP
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SHUNT_DRV*
REF
PGND
2x NC*
SHUNT_CTRL*
* MAX25601A/C ONLY
Maxim Integrated │ 13
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Detailed Description
Input Voltage (IN)
The input supply pin (IN) is the input to the internal LDO,
and must be locally bypassed with a minimum of 0.1μF
capacitance close to the pin. All the input current drawn by
the device goes through this pin. The positive terminal of
the bypass capacitor must be placed as close as possible
to this pin, and the negative terminal of the bypass capacitor must be placed as close as possible to the PGND pin.
V Regulator (VDRV)
A regulated 5V output is provided for driving the gates of
the external MOSFETs and other external circuitry with
a current up to 10mA. Bypass VDRV to PGND with a
minimum of 2.2μF ceramic capacitor, positioned as close
as possible to the device. In certain applications when an
external regulated 5V supply is available, the IN, VDRV
and VCC pins can be connected together to the regulated
5V, saving the power dissipation in the internal regulator
of the device.
Input Undervoltage/Enable (UVEN)
The device features adjustable UVLO using the enable
input (UVEN). Connect UVEN to VIN_BOOST through a
resistive divider to set the UVLO threshold. The device is
enabled when VUVEN exceeds the 1.24V (typ) threshold.
UVEN also functions as an enable/disable input to the
device. Drive UVEN low to disable the output and high to
enable the output.
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs.
The high-side gate driver (DH) sources and sinks 1.5A,
and the low-side gate driver (DL_) sources 1.0A and
sinks 2.4A. This ensures robust gate drive for high-current
applications. The DH_ floating high-side MOSFET driver
is powered by BST_, while the DL synchronous-rectifier
driver is powered directly by the 5V bias supply (VDRV).
High-Side Gate-Drive Supply (BST_)
The floating BST-LX capacitor provides the required supply for the high-side MOSFET. This capacitor is charged
through the BST diode each time LX is pulled low.
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Synchronous Boost and
Synchronous Buck LED Controllers
Shunt Dimming (SHUNT_CTRL, SHUNT_DRV)
The MAX25601A/C includes an integrated gate driver for
HUD dimming. This allows much faster on/off switching
of the LEDs, enabling much wider dimming ratios up to
10,000.
A control signal at SHUNT_CTRL directly drives SHUNT_
DRV. SHUNT_DRV is capable of driving n-channel
MOSFETs with up to 10nC gate charge.
Thermal Shutdown
Internal thermal-shutdown circuitry is provided to protect
the device in the event that the maximum junction temperature is exceeded. The threshold for thermal shutdown
is 165°C with a 15°C hysteresis (both values typical).
During thermal shutdown, the low- and high-side gate
drivers are disabled.
Fault Indicator (FLT)
The device features an active-low, open-drain fault indicator (FLT). FLT asserts when one of the following conditions occur:
1) Buck overvoltage or open across the LED string
2) Buck short-circuit condition across the LED string
3) Boost undervoltage
Short-circuit condition across the LED string: When the
LED string is shorted and the OUT pin voltage drops
below the short threshold of 50mV for more than 1.2ms,
the FLT pin goes low. During PWM dimming, the short
detection is reported on the FLT pin only when DIM is
high. Once FLT is asserted when the DIM is high, it stays
asserted until the fault condition is removed.
Open LED detection: When the LED string is opened and
the IOUTV pin voltage drops to lower than 75% of the targeted voltage for more than 1.2ms, the FLT pin goes low.
During PWM dimming, the open detection is reported on
the FLT pin only when DIM is high. Once FLT is asserted
when the DIM is high, it remains asserted until the fault
condition is removed. The LED open detection works only
when the REFI pin is greater than 325mV.
Overvoltage detection: When the voltage on the OUT
pin exceeds the overvoltage threshold of 3V for more
than 1.2ms, the FLT pin goes low. During PWM dimming, the overvoltage detection is reported on the FLT
pin only when DIM is high. Once FLT is asserted when
DIM is high, it remains asserted until the fault condition
is removed.
Maxim Integrated │ 14
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Boost Controller
Boost Switching Frequency (RT/SYNCIN)
Boost Peak Current-Mode-Controlled Architecture
The MAX25601A/B/C/D offers peak current-mode control
operation for best load-step performance and simpler
compensation. The inherent feed-forward characteristic
is especially useful in automotive applications where the
input voltage changes quickly during cold-crank and loaddump conditions. While the current-mode architecture
offers many advantages, there are some shortcomings.
In high duty-cycle operation, subharmonic oscillations can
occur. To avoid this, the device offers programmable internal slope compensation. To avoid premature turn-off at
the beginning of the on-cycle, the current-limit and PWM
comparator inputs have leading-edge blanking.
Loop Compensation
A transconductance amplifier in the voltage feedback
path allows a simple type-2 configuration to compensate
the loop. The appropriate poles and zeros are set by the
external resistors and capacitors around the COMP output of the transconductance amplifier.
Slope Compensation
Slope compensation helps prevent subharmonic oscillations by decreasing any perturbation over subsequent
switching cycles. The boost controller has internal slope
compensation that is proportional to the selected switching frequency. Two options are available for selection
based on the DL2 pin configuration at power on. The
higher slope compensation setting is recommended for
output voltages greater than 45V, while the lower setting
is for output voltages less than 45V. The slope compensation is also automatically changed at appropriate input
voltage thresholds as shown in Table 1.
The boost switching frequency can be set by a resistor from RT/SYNCIN to SGND, or driven externally by
a PWM signal with a frequency between 200kHz and
2.2MHz. When set by an external resistor, the switching
frequency follows the equation:
FSW_BOOST(kHz) = 37600/RT(kΩ)
When using an external clock, drive SYNCIN with a 3.3V
or 5V signal, between 200kHz and 2.2MHz, with a minimum off-time of 80ns.
SYNCOUT
The SYNCOUT pin provides a 180-degree phase-shifted
clock to the SYNCIN pin of another boost controller. When
using an external clock, drive SYNCIN with a 50% duty
cycle signal to shift SYNCOUT phase 180 degrees from
SYNCIN.
Spread Spectrum
The boost controller has an internal spread-spectrum
option to optimize EMI performance. The operating frequency is varied ±6%, centered on the oscillator frequency (FSW_BOOST). The modulation signal is a triangular
wave with a period of 1ms when the boost switching frequency is set to 400kHz. FSW_BOOST ramps down -6%
and ramps up +6% around 400kHz in 1ms. The cycle then
repeats. The modulation period is inversely proportional
to the boost switching frequency.
TSPREAD = 1ms x 400kHz / FSW_BOOST
The internal spread-spectrum function is disabled when
using an external clock. Frequency dithering must then be
done by the external clock.
Table 1. Slope Compensation Setting
DL2 RESISTOR
V IN_BOOST THRESHOLD
100kΩ
(Higher Slope Compensation)
< 8V
4.17x FSW_BOOST
8V-20V
2.08 x FSW_BOOST
> 20V
1.39 x FSW_BOOST
< 8V
2.08 x FSW_BOOST
8V-20V
1.39 x FSW_BOOST
>20V
1.04 x FSW_BOOST
30kΩ
(Lower Slope Compensation)
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SLOPE COMPENSATION (V/S)
Maxim Integrated │ 15
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Boost Output Voltage and Overvoltage Protection
Boost Soft-Start
The boost controller has programmable output voltage set
by the resistor-divider at the FB pin. Overvoltage protection is 20% higher than the regulation voltage. The output
voltage and overvoltage setpoints are defined by the following equations:
The boost controller features a voltage soft-start to reduce
inrush current. The soft-start time is approximately 9ms
when the boost switching frequency is set to 400kHz.
The soft-start time is inversely proportional to the boost
switching frequency.
VOUT_BOOST = VFB (RFB1 + RFB2)/RFB2
tSS_BOOST = 3712/FSW_BOOST
VOVP_BOOST = VTH_OVP_BOOST (RFB1 + RFB2)/RFB2
where VFB is 1V typ and VTH_OVP_BOOST is 1.2V typ in
the Electrical Characteristics section.
If the output voltage reaches VOVP_BOOST, the DH1
and DL1 pins are pulled low. The OVP circuit has a fixed
hysteresis of 100mV before the driver attempts to switch
again.
Multi phase Configurations
The boost controller can be configured for master or
slave mode of operation in multiphase configurations.
The modes are selected by the resistor value at the
SYNCOUT pin. At power up, the resistor value is decoded
during the 3ms power on initialization, and the selected
configuration is latched.
Boost Output Undervoltage and
Hiccup Operation
The boost controller includes output undervoltage protection. The boost controller must be in current limit when the
boost output voltage drops below 70% of the setpoint to
cause the boost controller to shut down and enter hiccup
mode operation. Hiccup mode causes the boost controller to remain off during the hiccup period. The hiccup
period is approximately 54ms when the boost switching
frequency is set to 400kHz. The hiccup period is inversely
proportional to the boost switching frequency.
Buck Controller
Buck Average Current-Mode-Controlled
Architecture
The buck controller uses a new average current-modecontrol scheme to regulate the current in the output
inductor of the buck LED driver. The inductor current is
not directly sensed. Current is sensed across the lowside current-sense resistor (RCS_LED) using the CSP and
CSN pins, during the time when the synchronous FET is
conducting. The voltage at REFI sets the regulation voltage for V(CSP-CSN).
In a buck converter operating in continuous-conduction
mode, the average inductor current is the same as the
output current. A pulse doubler is used to determine the
on-time of the synchronous FET by doubling the time the
inductor current is above the regulation threshold:
tOFF_BUCK = 2 x tPW_BUCK
where tPW_BUCK is the high-state pulse width of the internal comparator in the device.
∆ILED
ILED = ILBUCK
tPW_BUCK
tHICCUP_BOOST = 21504 / FSW_BOOST
Table 2. Multiphase Configuration
SYNCOUT RESISTOR
MASTER/SLAVE SELECTION
35kΩ
Single phase or
multiphase master
5kΩ
Multiphase slave
www.maximintegrated.com
0A
DH2
DL2
2x tPW_BUCK
Figure 1. Buck Pulse Doubler
Maxim Integrated │ 16
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Buck Switching Frequency
Dimming (PWMDIM, REFI, SHUNT_CTRL,
SHUNT_DRV)
The on-time is determined based on the external resistor
(RTON) connected between TON and the input voltage,
in combination with a capacitor (CTON) between RTON
and SGND pin. The input voltage and the RTON resistor
set the current sourced into the capacitor (CTON), which
governs the ramp speed. The ramp threshold is proportional to scaled-down feedback of the output voltage at
the OUT pin. The proportionality of VOUT_BUCK is set by
an external resistor-divider (ROUT1, ROUT2) from VOUT.
The device supports both analog and PWM dimming of
the LED. In analog dimming, the LED current is adjusted
by the voltage on the REFI pin. In PWM dimming, dimming is achieved by repeatedly switching the LEDs on
and off to achieve a lower effective brightness. Using the
PWMDIM pin, PWM dimming can be achieved by driving
a PWM signal on the PWMDIM pin, or by setting an analog voltage on the PWMDIM pin to use the internal 200Hz
dimming oscillator. Using the SHUNT_CTRL pin, lower
dimming duty cycles can be achieved by driving a PWM
signal on the SHUNT_CTRL pin.
tON_BUCKVIN_BUCK/RTON = CTON
(VOUT_BUCKROUT2/(ROUT2 + ROUT1))
In the case of a buck converter tONVIN_BUCK is also
given by:
The PWMDIM pin must be set at its logic-high level when
using PWM dimming through SHUNT_CTRL. The buck
shuts down if the PWMDIM input is below the VDIM_OFS
for 210ms (to be confirmed).
tON_BUCK = VOUT_BUCK/VIN_BUCKfSW_BUCK
where fSW_BUCK is the switching frequency.
Based on that, the switching frequency in case of the new
average current-mode-controlled architecture is given by:
Analog Dimming using REFI
The device has an analog dimming-control input (REFI).
The voltage at REFI sets the LED current level when
VREFI ≤ 1.2V. For VREFI > 1.3V, REFI is clamped to
1.3V (typ). The maximum withstand voltage of this input
is 5.5V. The LED current is set to zero when the REFI
voltage is at or below 0.18V typ. The LED current can be
linearly adjusted from zero to full scale for the REFI voltage in the range of 0.2V to 1.2V.
fSW_BUCK = 1/K or fSW_BUCK =
(ROUT2 + ROUT1)/(CTONRTONROUT2)
In the actual application, there will be slight variations
in switching frequency due to the voltage drops in the
switches and the inductor, the propagation delay from the
tON input to the LX switching node, and the nonlinear current charging the tON capacitor. These effects have been
ignored in the calculations for switching frequency.
VIN_BUCK
PWM DIMMING
SIGNAL
FIXED VREFI
DH2
DIM
REFI
CBUCK
DL2
MAX25601A
MAX25601B
MAX25601C
MAX25601D
SHUNT_CTRL
LBUCK
LED1
CSP
RCS_LED
CSN
LEDn
SHUNT_DRV
Figure 2. Analog Dimming using REFI
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Maxim Integrated │ 17
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
PWM Dimming using PWMDIM
the buck regulator on and off to dim the LEDs. When the
PWMDIM signal is high, the switching of the synchronous MOSFETs in the buck LED driver is enabled. When
the PWMDIM signal is low, both the high- and low-side
MOSFETs are turned off. The LED current waveform is
shown in Figure 4.
The PWMDIM pin functions as the PWM dimming input of
the buck. The PWMDIM pin can be driven with either an
analog or PWM signal. This method of dimming repeatedly switches the buck regulator on and off to dim the
LEDs. Minimum duty cycle is limited by the ramping up
and down of the inductor current, which is determined
by the inductor value, switching frequency, and input-tooutput voltage ratio.
Analog-to-PWM Dimming: Set an analog voltage in the
range of 0.2V ≤ VDIM ≤ 3V on the PWMDIM pin. The IC
compares the DC input voltage to an internally generated
200Hz ramp to pulse-width-modulate the buck.
For PWM dimming with the PWM signal, drive the
PWMDIM pin with an external PWM signal with a frequency between 10Hz and 2kHz to repeatedly switch
VIN_BUCK
PWM DIMMING
SIGNAL
FIXED VREFI
LBUCK
DH2
DIM
REFI
CBUCK
DL2
MAX25601A
MAX25601B
MAX25601C
MAX25601D
CSP
RCS_LED
CSN
SHUNT_CTRL
LED1
LEDn
SHUNT_DRV
Figure 3. Digital PWMDIM Diming
ILED = ILBUCK
VREFI sets ILED
0A
DIM
DH2
DL2
DH2 SWITCHING
DL2 SWITCHING
Figure 4. External PWM Dimming
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Maxim Integrated │ 18
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
VIN_BUCK
FIXED OR ADJUSTABLE
DC VOLTAGE FOR VDIM
FIXED VREFI
DH2
DIM
REFI
CBUCK
DL2
MAX25601A
MAX25601B
MAX25601C
MAX25601D
SHUNT_CTRL
LBUCK
LED1
CSP
RCS_LED
CSN
LEDn
SHUNT_DRV
Figure 5. Analog-to-Digital PWMDIM Diming
3V
0.2V
3.2V
INTERNAL 200Hz DIMMING
RAMP
VDIM
0V
DIMMING
Figure 6. Analog-to-PWM Dimming
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Maxim Integrated │ 19
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
PWM Dimming using SHUNT_CTRL
low enough on-resistance to minimize power loss. Shunt
dimming is typically used in HUD applications where the
entire string is shorted out by the shunt. Shunt dimming
can also be used in high-beam/low-beam applications in
which the high-beam portion of the LED string is shorted
out (disabled) by the shunt.
The SHUNT_CTRL pin drives the SHUNT_DRV pin to
control an external shorting FET. This provides extremely
fast on/off switching of the LEDs that does not depend on
the buck regulator startup or shutdown response, allowing for lower dimming duty cycles, and wider dimming
range. Use a shorting FET with QG less than 10nC, and a
VIN_BUCK
FIXED OR ADJUSTABLE
DC VOLTAGE FOR VDIM
DH2
DIM
REFI
FIXED VREFI
CBUCK
DL2
MAX25601A
MAX25601C
HUD DIMMING
SIGNAL
LBUCK
SHUNT_CTRL
LED1
CSP
RCS_LED
CSN
LEDn
SHUNT_DRV
Figure 7. Shunt Dimming
ILED = ILBUCK
Low Frequency
Switching
VREFI sets ILED
0A
PWM_HUD
DH2
DH2 SWITCHING
DL2
DL2 SWITCHING
Figure 8. SHUNT_CTRL Dimming in HUD Applications
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Maxim Integrated │ 20
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
PWM Dimming by Shorting individual
LEDs in the String
Extremely fast dimming of individual LEDs in the string
can be acheived by applying a shorting FET across each
LED, as shown in Figure 9. This application is used in
matrix lighting where individual LEDs in the string are
controlled by a shorting MOSFET across each LED. With
this method, each LED in the string can be turned on and
off without any impact on the brightness of the other LEDs
in the string. If required, the entire string can be shorted
at the same time while still maintaining current regulation
in the inductor with minimal overshoot or undershoot.
The rise and fall times of the currents in each LED are
extremely fast. With this method, only the speed of the
parallel-shunt MOSFET limits the dimming frequency
and dimming duty cycle. Minimize the output capacitor
(CBUCK) to minimize current spikes due to the discharge
of this capacitor into the LEDs when the shorting FETs
are turned on. In some applications, this capacitor can be
completely eliminated.
Buck Overvoltage Protection
The device has programmable overvoltage protection
using the resistor-divider at the OUT pin. The overvoltage
setpoint is defined by:
VOVP_BUCK= VTH_OVP_BUCK (ROUT1 + ROUT2)/ROUT2
where VTH_OVP_BUCK is 3V (typ) in the Electrical
Characteristics section.
If the output voltage reaches VOVP_BUCK, the DH2 and
DL2 pins are pulled low to prevent damage to the LEDs or
the rest of the circuit. The OVP circuit has a fixed hysteresis of 100mV before the driver attempts to switch again.
Buck Current Monitor (IOUTV)
The device includes a current monitor on the IOUTV pin.
The IOUTV voltage is an analog voltage indication of the
inductor current when PWMDIM is high. The currentsense signal on the bottom MOSFET across RCS_LED
is inverted and amplified by a factor of 5 by an inverting
amplifier inside the device. An added offset voltage of
0.2V is also added to this voltage. This amplified signal
goes through a sample and hold switch. The sample and
hold switch is controlled by the DL2 signal. The sampleand-hold switch is turned on only when DL2 is high (and
off when DL2 is low). This provides a signal on the output
of the sample and hold that is a true representation of
the inductor current when PWMDIM is high. The sample
and hold signal passes through an RC filter and then the
buffered output is available on the IOUTV pin. The voltage
on the IOUTV pin is given by:
VIOUTV = ILED x RCS_LED x 5 + 0.2V
where ILED is the LED current, which is the same as the
average inductor current when PWMDIM is high. VIOUTV
indicates the same voltage when PWMDIM goes low
as when PWMDIM was previously high.
VIN_BUCK
FIXED OR ADJUSTABLE
DC VOLTAGE FOR VDIM
FIXED VREFI
DH2
DIM
REFI
CBUCK
DL2
MAX25601A
MAX25601B
MAX25601C
MAX25601D
SHUNT_CTRL
LBUCK
LED1
PWM1
LEDn
PWMn
CSP
RCS_LED
CSN
SHUNT_DRV
Figure 9. Matrix LED Dimming
www.maximintegrated.com
Maxim Integrated │ 21
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Applications Information
Input Undervoltage/Enable
The minimum operating input voltage is set by the resistor-divider at UVEN.
VIN_BOOST(MIN) = VUVEN (RUVEN1 + RUVEN2)/RUVEN2
where VUVEN is 1.24V (typ) in the Electrical Characteristics
section.
Select RUVEN2 between 10kΩ and 50kΩ to minimize
power loss.
Calculate RUVEN1 as follows:
RUVEN1 = (VIN_BOOST(MIN)/VUVEN – 1) x RUVEN2
Boost Output Voltage and Power
As a pre-boost to the buck regulator, the boost output
voltage and power requirements are determined by the
buck regulator output voltage and power requirements.
Establish these requirements with the equations below.
These are then used in the subsequent boost calculation
sections.
POUT_BOOST = PIN_BUCK =
(VOUT_BUCK_MAX x ILED)/ηBUCK
VOUT_BOOST = VIN_BUCK = VOUT_BUCK_MAX
/ (1 – tON_MIN_BUCK/FSW_BUCK)
where VOUT_BUCK_MAX = VLED + ILED x RDYN and
ηBUCK is the buck efficiency, tON_MIN_BUCK = 110ns max
in the Electrical Characteristics, and FSW_BUCK is the
selected buck switching frequency.
Set the boost output voltage 20% above VIN_BUCK to
allow for boost output voltage transients and loadline.
Calculate the required VOUT_BOOST as follows:
VOUT_BOOST = 1.20 x VIN_BUCK
IOUT_BOOST = POUT_BOOST/ VOUT_BOOST
Boost Switching Frequency
Switching frequency is selected based on the tradeoffs
between efficiency, solution size/cost, and the range of
output voltage that can be regulated. Many applications
place limits on switching frequency due to EMI sensitivity.
Having selected the boost switching frequency, place a
resistor from RT/SYNCIN to SGND based on the following equation:
RT = (34.2x109 /FSW_BOOST) – 550
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Synchronous Boost and
Synchronous Buck LED Controllers
If using an external clock, drive SYNCIN with a 3.3V or
5V signal, between 200kHz and 2.2MHz, with a minimum
off-time of 80ns.
Boost Inductor Selection
In the boost converter, the average inductor current varies with the line voltage. The maximum average current
occurs at the lowest line voltage. For the boost converter,
the average inductor current is equal to the input current.
Calculate maximum duty cycle using the equation below:
DMAX = (VOUT_BOOST + VDSSYNC_FET +
∆VIN_RES- VIN_BOOST(MIN))/(VOUT_BOOST +
VDSSYNC_FET – VDSCTRL_FET)
∆VIN_RES = IOUT_BOOST x (RIN+ RDCR)
where VOUT_BOOST and IOUT_BOOST are determined
in the Boost Output Voltage and Power section, VIN_
BOOST(MIN) is the minimum input supply voltage, and
VDSCTRL_FET and VDSSYNC_FET are the average
drain-to-source voltage of the boost control and synchronous FETs when they are on, and VIN_RES is the voltage
drop along the input current path.
Use an approximate value of 0.2V for VDSCTRL_FET and
VDSSYNC_FET initially to calculate DMAX. A more accurate value of the maximum duty cycle can be calculated
once the power MOSFET is selected based on the maximum inductor current.
Use the following equations to calculate the maximum
average inductor current (ILBOOST(MAX)), peak-to-peak
inductor current ripple (∆ILBOOST), and the peak inductor
current (IIN_PK) in amperes:
ILBOOST(MAX) = IOUT_BOOST/(1 - DMAX)
Allowing the peak-to-peak inductor ripple to be ∆ILBOOST,
the peak inductor current is given by:
ILBOOST(PK) = ILBOOST(MAX) + 0.5 x ∆ILBOOST
Select ∆ILBOOST in the range of 0.2x to 0.4x of
ILBOOST(MAX).
The inductance value (L) of inductor LBOOST is calculated
as:
LBOOST = (VIN_BOOST(MIN) – ∆VIN_RES VDSCTRL_FET) x DMAX/(FSW_BOOST x ∆ILBOOST)
where FSW_BOOST is the switching frequency, and other
terms defined earlier. Choose an inductor that has a minimum inductance greater than the calculated value. The
current rating of the inductor should be higher than ILPK
at the operating temperature.
Maxim Integrated │ 22
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Boost Input Current Sense
The boost input current sense is selected based on the
required current limit at the peak inductor current.
RIN = VILIM_BST/ ILBOOST(PK)
where VILIM_BST is 72mV (min) in the Electrical
Characteristics section, and IIN_PK is determined in the
Boost Inductor Selection section.
Boost Input and Output Capacitors
When selecting a ceramic capacitor, special attention
must be paid to the operating conditions of the application. Ceramic capacitors can lose 50% or more of their
capacitance at their rated DC-voltage bias, and can also
lose capacitance with extremes in temperature. Make
sure to check any recommended deratings and also verify
if there is any significant change in capacitance at the
operating input voltage and operating temperature.
Boost Input Capacitor
The input current to a boost converter is almost continuous and the RMS ripple current at the input capacitor is
low. Calculate the minimum input capacitor value and
maximum ESR using the following equations:
CIN_BOOST = ∆ILBOOST/(4 x FSW_BOOST x ∆VQPP)
ESRMAX = ∆VESR/∆ILBOOST
∆ILBOOST is peak-to-peak inductor ripple current. ∆VQPP
is the portion of input ripple due to the capacitor discharge
and ∆VESR is the contribution due to ESR of the capacitor. Assume the input capacitor ripple contribution due to
ESR (∆VESR) and capacitor discharge (∆VQPP) are equal
when using a combination of ceramic and aluminium
capacitors.
A large current is drawn from the input source during converter startup, especially at high output-to-input differential. The devices have an internal soft-start, but a larger
input capacitor than calculated above may be necessary
to avoid chattering due to finite hysteresis during startup.
Boost Output Capacitor
In a boost converter, the output capacitor supplies the
load current when the main switch is on. The required output capacitance is high, especially at lower duty cycles.
Also, the output capacitor ESR needs to be low enough
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Synchronous Boost and
Synchronous Buck LED Controllers
to minimize the voltage drop due to ESR while supporting
the load current. Use the following equations to calculate
the output capacitor for a specified output ripple. All ripple
values are peak-to-peak.
ESR = ∆VESR/IOUT_BOOST
COUT_BOOST = (IOUT_BOOST x (1 - DMAX))/
(∆VQPP x FSW_BOOST)
where IOUT_BOOST is the output current, ∆VQPP is the
portion of the ripple due to the capacitor discharge, and
∆VESR is the ripple contribution due to the ESR of the
capacitor. DMAX is the maximum duty cycle (i.e., the duty
cycle at the minimum input voltage). Low-ESR ceramic
capacitors are suitable for lower output ripple and noise.
Since the buck input is taken from the boost output, the
capacitance required is then the higher of the two requirements. See the Buck Input Capacitor Selection.
Boost Output Voltage and
Overvoltage Setting
VOUT_BOOST is set by the resistor-divider at FB.
VOUT_BOOST = VFB (RFB1 + RFB2)/RFB2
where VFB is 1V (typ) in the Electrical Characteristics
section.
Select RFB2 between 10kΩ and 50kΩ to minimize power
loss.
Calculate RFB1 as follows:
RFB1 = (VOUT_BOOST/VFB – 1) x RFB2
With RFB1 and RFB2 determined, calculate VOVP_BOOST:
VOVP_BOOST = VTH_OVP_BOOST (RFB1 + RFB2)/RFB2
where VTH_OVP_BOOST is 1.2V (typ) in the Electrical
Characteristics section.
Maximum Output/Input Ratio
The maximum boost output/input ratio is limited by the
minimum off-time of the boost oscillator (tOFF_MIN_BST).
(1 - DMAX)/FSW_BOOST = tOFF_MIN_BST
Lower switching frequencies allow for higher DMAX, and
hence a higher output-to-input ratio. DMAX can be roughly
approximated as (1 - VIN_BOOST/VOUT_BOOST), or more
accurately defined in the Boost Inductor Selection section.
Maxim Integrated │ 23
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Boost Controller Loop Compensation (COMP)
The basic regulator loop is modeled as a power modulator, output feedback-divider, and an error amplifier, as
shown in Figure 10. The power modulator has a DC gain
set by gMC x RLOAD, with a pole and zero pair set by
RLOAD, the output capacitor (COUT_), and its ESR. The
loop response is set by the following equation:
( 1 −2 D ) ×
GMOD = gMC × RLOAD ×
( )(
1+j
1+j
f
fzMOD
f
× 1 − jf
f
fpMOD
Rph_zMOD
)
where RLOAD = VOUT_/ILOUT(MAX) in ohms and gMC =
1/(AV_CS_ x RDC) in S. AV_CS_ is the voltage gain of the
current-sense amplifier and is typically 11V/V. RDC is the
current-sense resistor in ohms.
In a current-mode step-down converter, the output capacitor and the load resistance introduce a pole at the following frequency:
When COUT_ is composed of n identical capacitors in
parallel, the resulting COUT_ = n x COUT(EACH), and
ESR = ESR(EACH)/n. Note that the capacitor zero for a
parallel combination of similar capacitors is the same as
for an individual capacitor. The feedback voltage-divider
has a gain of GAINFB_ = VFB_/VOUT_, where VFB_ is
1.005V (typ).
The transconductance error amplifier has a DC gain of
GAINEA(DC) = gm,EA x ROUT,EA, where gm,EA is the
error amplifier transconductance, which is 400μS (max),
and ROUT,EA is the output resistance of the error amplifier, which is 10MΩ (typ).
A dominant pole (fdpEA) is set by the compensation capacitor (CC) and the amplifier output resistance (ROUT,EA). A
zero (fZEA) is set by the compensation resistor (RC) and
the compensation capacitor (CC). There is an optional
pole (fPEA) set by CF and RC to cancel the output capacitor ESR zero if it occurs near the crossover frequency
(fC), where the loop gain equals 1 (0dB). Therefore:
1
fpMOD = π × R
LOAD × COUT_
fpEA =
The output capacitor and its ESR also introduce a zero at:
(
1
)
2π × ROUT, EA + RC × CC
1
fzEA = 2π × R × C
C
C
1
fzMOD = 2π × ESR × C
OUT_
1
The right-half plane zero is at:
fp2EA = 2π × R × C
C
C
RLOAD
fRph_zMOD = 2π × L × (1 − D) × (1 − D)
gmc = 1/(AVCS x RDC)
INP
CURRENT-MODE
POWER
MODULATION
INN
R1
RESR
COUT_
gmea = 300µS
FB
ERROR
AMP
R2
VREF
10MΩ
RC
CF
CC
Figure 10. BOOST Controller Compensation Network
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Maxim Integrated │ 24
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
The loop gain crossover frequency (fC) should be ≤ 1/3 of
right-half plane zero frequency.
fC ≤
fRph_zMOD
3
At the crossover frequency, the total loop gain must be
equal to 1. Therefore:
GAIN
VFB_
×V
× GAIN
=1
MOD fC
EA fC
OUT_
( )
GAIN
GAIN
( )
EA fC
( )
MOD fC
( )
= gm, EA × RC
= GAINMOD(dc) ×
fpMOD
fC
When two MAX25601A/B/C/D boost controllers are operated in parallel, the SYNCIN of the second MAX25601A/
B/C/D can be driven by the SYNCOUT of the first
MAX25601A/B/C/D for ideal 180-degree out-of-phase
operation. When more than two boost regulators are used
in parallel, an external clock is recommended to drive the
SYNCIN pin of each regulator at the optimal phase separation of 360 degrees divided by the number of phases.
Dual-Phase Configuration
In the dual-phase configuration, one MAX25601A/B/C/D
is set as the master (SYNCOUT = 30kΩ), while the other
MAX25601A/B/C/D is set as a slave (SYNCOUT = 5kΩ).
The transconductance amplifier of the slave is disabled in
this configuration. The transconductance amplifier of the
master provides the necessary compensation to the slave
by connecting the COMP pins of the master and slave
together.
Power-Up Sequence
Therefore:
GAIN
VFB_
×V
× gm, EA × RC = 1
MOD fC
OUT_
( )
Solving for RC:
VOUT_
RC = g
m, EA × VFB_ × GAIN
MOD f
( C)
Set the error-amplifier compensation zero formed by RC
and CC at the fpMOD. Calculate the value of CC as follows:
1
CC = 2π × f
pMOD × RC
If fzMOD is less than 5 x fC, add a second capacitor (CF)
from COMP3 to AGND. The value of CF is:
1
CF = 2π × f
zMOD × RC
Multiphase/Parallel-Boost Configuration
A practical limit for a single-phase boost regulator is
approximately 50W. This limitation is largely due to the
losses in the power stage at low input voltages. While
doubling the MOSFETs and inductors is possible, a more
efficient solution is to add a second boost regulator that
operates out of phase, dividing the losses between two
phases, providing input and lower output-voltage ripple
cancellation, and provide faster transient response.
The MAX25601A/B/C/D incorporates features that allow
two or more boost regulators to operate in parallel.
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The master and slave must be powered up together by
tying the UVEN inputs together.
Buck Switching Frequency
Switching frequency is selected based on the tradeoffs
between efficiency, solution size, solution cost, and the
range of output voltage that can be regulated. Many applications place limits on switching frequency due to EMI
sensitivity. The on-time of the MAX25601A/B/C/D's buck
controller can be programmed for switching frequencies
ranging from 100kHz up to 1MHz. This on-time varies in
proportion to both input voltage and output voltage, as
described in the Buck Average Current-Mode-Controlled
Architecture section. However, in practice, the switching
frequency shifts in response to large swings in input or
output voltage. The maximum switching frequency is limited only by the minimum on-time and minimum off-time
requirements. The switching frequency (FSW_BUCK) is
given by:
FSW_BUCK = (ROUT2 + R OUT1)/(CTONRTONR OUT2)
Choose CTON between 100pF and 2.2nF. 470pF or 1nF
are good choices. ROUT1 and ROUT2 are selected by the
buck OVP requirement on the OUT pin. See the Buck
Overvoltage Setting section. Rearranging the equation
to solve for RTONonce the other component values are
determined,
RTON = (ROUT2 + R OUT1)/(CTONR OUT2fSW_BUCK)
RTON should be large enough so that at VIN(MAX), the
voltage at the TON pin is < 50mV when the internal discharge FET is turned on.
RTON > (VIN(MAX) / 50mV – 1) x 30Ω
Maxim Integrated │ 25
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
LBOOST1
RIN1
INPUT
CIN1
RUVEN1
INP
INN
UVEN
SYNCOUT_M
DL1
RT/SYNCIN
RT
CCOMP
COMP_M
SYNCOUT_S
RFB2
RSYNCOUT_S
FB
LBOOST2
RIN2
INPUT
RSYNCOUT_M
CIN2
INP
INN
UVEN
CONFIGURE AS MASTER:
RSYNCOUT_M = 35kΩ
RFB1
MAX25601
COMP
SYNCOUT_M
DH1_M
SYNCOUT
RUVEN2
RCOMP
CBOOST
BOOST
VOUT
SYNCOUT_S
DL1
DH1_S
SYNCOUT
RT/SYNCIN
SYNCOUT_M
CONFIGURE AS SLAVE:
RSYNCOUT_S = 5kΩ
MAX25601
COMP_M
COMP
FB
DUAL PHASE CONFIGURATION
Figure 11. Dual-Phase Current-Sharing Configuration
Buck Overvoltage Setting
Overvoltage is typically set 20% higher than the maximum
buck output voltage. The maximum buck output voltage is
LED voltage.
VOUT_BUCK_MAX = VLED + ILED x RDYN
VOVP_OUT= 1.2 x VOUT_BUCK_MAX= VTH_OVP_BUCK
(ROUT1+ROUT2)/ROUT2
where
VLED is the maximum LED forward voltage of the LED
string., ILED is the maximum LED current, RDYN is the
total dynamic resistance of the LED string, and VTH_OVP_
BUCK is 3V (typ) in the Electrical Characteristics section.
Select ROUT2 between 10kΩ and 50kΩ to minimize
power loss.
Calculate ROUT1 as follows:
ROUT1 = ((1.2 x VOUT_BUCK_MAX)/
VTH_OVP_BUCK – 1) ROUT2
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Programming the LED Current
The LED current is programmed by the voltage on REFI
when VREFI ≤ 1.2V (analog dimming). The current is
given by:
ILED = (VREFI – VCS_OFS)/(5 x RCS_LED)
Rearranging the equation to solve for VREFI,
VREFI = (ILED x 5 x RCS_LED) + VCS_OFS
where VCS_OFS is 0.2V (typ) in the Electrical
Characteristics section.
Select RCS_LED such that at the desired LED current,
the voltage across RCS_LED is in the 100mV to 200mV
range, balancing signal-to-noise levels and power loss.
Calculate the power loss in RCS_LED and select a resistor
with a higher power rating.
PLOSS = ILED2x RCS_LEDx (1-DBUCK)
Maxim Integrated │ 26
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Buck Inductor Selection
The peak inductor current, selected switching frequency,
and the allowable inductor-current ripple determine the
value and size of the output inductor. Selecting a higher
switching frequency reduces the inductance requirements, but at the cost of efficiency. The charge/discharge
cycle of the gate capacitance of the external switching
MOSFET's gate and drain capacitance create switching
losses, which worsen at higher input voltages since the
switching losses are proportional to the square of the
input voltage. Choose inductors from the standard highcurrent, surface-mount inductor series available from various manufacturers. High inductor-current ripple causes
large peak-to-peak flux excursion, increasing the core
losses at higher frequencies.
The peak-to-peak current-ripple values typically range
from ±10% to ±40% of DC current (ILED). Based on the
LED current-ripple specification and desired switching frequency, the inductor value can be calculated as follows:
L = (VIN_BUCK - VOUT_BUCK) tON/∆ILED
where ∆ILED is the peak-to-peak inductor ripple.
It is important to ensure that the rated inductor saturation
current is greater than the worst-case operating current
(ILED+∆ILED/2) under the wide operating temperature
range.
Buck Input and Output Capacitors
When selecting a ceramic capacitor, special attention
must be paid to the operating conditions of the application. Ceramic capacitors can lose over 50% of their
capacitance at their rated DC-voltage bias, and also lose
capacitance with extremes in temperature. Make sure to
check any recommended deratings and also verify if there
is any significant change in capacitance at the operating
input voltage and the operating temperature.
Buck Input Capacitor Selection
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input capacitor. The switching frequency, peak inductor current, and
allowable peak-to-peak voltage ripple reflected back to
the source dictate the capacitance requirement. The input
ripple consists of ∆VQPP (caused by the capacitor discharge) and ∆VESR (caused by the ESR of the capacitor).
Use low-ESR ceramic capacitors with high ripple-current
capability at the input. A good starting point for selection
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Synchronous Boost and
Synchronous Buck LED Controllers
of CIN is to use an input-voltage ripple of 2% to 10% of
VIN_BUCK. CIN_MIN can be selected as follows:
CIN_MIN = 2(ILED x tON)/∆VIN_BUCK
where tON is the on-time pulse width per switching cycle.
As the buck input is taken from the boost output, the
capacitance required is then the higher of the two requirements. See the Boost Output Capacitor Selection.
Buck Output Capacitor Selection
The function of the output capacitor is to reduce the output ripple to acceptable levels. The ESR, ESL, and the
bulk capacitance of the output capacitor contribute to the
output ripple. In most applications, using low-ESR ceramic capacitors can dramatically reduce the output ESR and
ESL effects. To reduce the ESL effects, connect multiple
ceramic capacitors in parallel to achieve the required bulk
capacitance.
The output capacitance (COUT_BUCK) is calculated using
the following equation:
COUT_BUCK= ((VIN_MIN_BUCK-VLED) x VLED)/
(ΔVRx 2 x LBUCKx VIN_MAX_BUCKx FSW_BUCK2)
where ∆VR is the maximum allowable voltage ripple.
Switching MOSFET Selection
The device requires two external n-channel MOSFETs
for each switching regulator. The MOSFETs should have
a voltage rating at least 20% higher than the maximum
boost output voltage to ensure safe operation during
the ringing of the switch node. In practice, all switching
converters have some ringing at the switch node due to
the diode parasitic capacitance and the lead inductance.
The MOSFETs should also have a current rating at least
50% higher than the average switch current. The total
losses of the power MOSFETs in both high- and low-side
MOSFETs should be estimated once the MOSFETs are
chosen. The n-channel MOSFETs must be logic-level
types with guaranteed on-resistance specifications at
VGS = 4.5V. The conduction losses at minimum input voltage should not exceed MOSFET package thermal limits
or violate the overall thermal budget. Also, ensure that the
conduction losses plus switching losses at the maximum
boost output voltage do not exceed package ratings or
violate the overall thermal budget. In particular, check that
the dV/dt caused by DH_ turning on does not pull up the
DL_ gate through its drain-to-gate capacitance. This is the
most frequent cause of cross-conduction problems.
Maxim Integrated │ 27
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
BST Capacitor Selection
The selected n-channel high-side MOSFET determines the
appropriate boost capacitance values (CBST in the Typical
Operating Circuit) according to the following equation:
CBST = QG/∆VBST
where QG is the total gate charge of the high-side
MOSFET and ∆VBST is the voltage variation allowed
on the high-side MOSFET driver after turn-on. Choose
∆VBST such that the available gate-drive voltage is not
significantly degraded (e.g., ∆VBST = 100mV) when
determining CBST. Use a Schottky diode when efficiency
is most important, as this maximizes the gate-drive voltage. If the quiescent current at high temperature is important, it may be necessary to use a low-leakage switching
diode. The boost capacitor should be a low ESR ceramic
capacitor. A minimum value of 100nF works in most
cases. A minimum value of 220nF is recommended when
using a Schottky diode.
Gate-Drive Power Loss
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. Therefore, the power dissipation
in the controller due to drive losses must be checked.
MOSFETs must be selected so that their total gate charge
is low enough, such that the gate total drive current is
within the VDRV LDO capability, and that the IC can
power the drivers without overheating the device. The
total power dissipated in the internal gate drivers of the
device is given by:
PDRIVE = VDRV x (QGHS_BOOST + QGLS_BOOST) x
FSW_BOOST + VDRV x (QGHS_BUCK + QGLS_BUCK) x
FSW_BUCK
where QGHS_BOOST and QGHS_BUCK are the high-side
MOSFET gate charge, and QGLS_BOOST and QGLS_
BUCK are the low-side MOSFET gate charge for the boost
and buck, respectively.
The power dissipated in the 5V regulator in the device due
to the gate drivers is given by:
PDIS = VIN_BOOST x (PDRIVE / VDRV)
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Synchronous Boost and
Synchronous Buck LED Controllers
PCB Layout
Typically, there are two sources of noise emission in a
switching power supply: high di/dt loops and high dv/dt
surfaces. For example, traces that carry the drain current
often form high di/dt loops. Similarly, the heatsink of the
MOSFET connected to the device drain presents a dv/dt
source; therefore, minimize the surface area of the heatsink as much as is compatible with the MOSFET power
dissipation, or shield it. Keep all PCB traces carrying
switching currents as short as possible to minimize current loops. Use ground planes for best results.
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. Use a multilayer board
whenever possible for better noise immunity and power
dissipation. Follow these guidelines for good PCB layout:
1) Use a large continuous copper plane under the IC
package. Ensure that all heat-dissipating components have adequate cooling.
2) Isolate the power components and high-current path
from the sensitive analog circuitry.
3) Keep the high-current paths short, especially at
the ground terminals. This practice is essential for
stable, jitter-free operation. Keep switching loops,
power traces, and load connections short:
a) Keep the high-side and low-side FETs, input and
output capacitors, and inductors close together
for each regulator.
b) Keep the LX area as small as possible.
c) Place the boost capacitor (CBST) as close as
possible to the BST and LX pins.
d) Follow the EV kit layout example.
4) Route high-speed switching nodes and high-voltage
switching nodes away from the sensitive analog
areas. High-speed gate-drive signals can generate
significant conducted and radiated EMI. This noise
can couple with high-impedance nodes of the IC and
result in undesirable operation. A low-value resistor
(4 to 10Ω at RDH and RDL), in series with the gatedrive signals, are recommended to slow the slew
rate of the LX_ node and reduce the noise signature.
They also improve the robustness of the circuit by
reducing the noise coupling into sensitive nodes.
Maxim Integrated │ 28
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
5) Use thick-copper PCBs (2oz rather than 1oz) to
enhance full-load efficiency.
6) Connect PGND and SGND to a star-point configuration. Use an internal PCB layer for the PGND and
SGND plane as an EMI shield to keep radiated noise
away from the device, feedback dividers, and analog
bypass capacitors.
7) The exposed pad on the bottom of the package must
be soldered to ground so that the pad is connected
to ground electrically and also acts as a heatsink
thermally. To keep thermal resistance low, extend the
ground plane as much as possible, and add thermal
vias under and near the device to additional ground
planes within the circuit board.
8) The parasitic capacitance between switching node
and ground node should be minimized to reduce
common-mode noise. Other common layout techniques, such as star ground and noise suppression
using local bypass capacitors, should be followed to
maximize noise rejection and minimize EMI within
the circuit.
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Synchronous Boost and
Synchronous Buck LED Controllers
Dual-Phase Boost PCB Layout
1) It is important that the inputs of both regulators are
very close together. Place the input current-sense
resistors side by side, immediately after the input
ceramic capacitors, to ensure a common point and
input sense.
2) Place the controller such that the input current sense
traces are < 1.5in long.
3) The FB resistor should sense the boost output voltage at the mid-point between both outputs so that
the ripple is symmetrical.
4) Connect COMP and AGND of both ICs together. The
traces should be well shielded and ground referenced, and placed away from any noise sources and
fast-switching signals
Maxim Integrated │ 29
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Typical Application Circuits
LBOOST
RIN
INPUT
INP
RUVEN1
INN
CIN
SYNCOUT
RRT
DH2
DIM
RFB2
N2
DH2
N3
DH2
CBST2
LBUCK
VDRV
BUCK
VOUT
LX2
DL2
CVDRV
MAX25601
N4
CBUCK
ROUT1
CSP
OUT
RCS_LED
CVCC
RREFI1
FB
N1
BST2
RT/SYNCIN
VDRV
RFB1
LX1
DL1
PWM or ANALOG
DIMMING
BOOST
VOUT
CBOOST
CBST1
DH1
RUVEN2
VCC
ROUT2
CSN
IOUTV
REFI
RREFI2
BST1
IN
UVEN
RVCC
VDRV
CCOMP
OUT
FB
COMP
* MAX25601A/C ONLY
OUT
RIOUTV
FB
BUCK
VOUT
CIOUTV
N5
RCOMP
BUCK and
BOOST FAULT
IOUTV
SHUNT_DRV*
HUD_OUT
SHUNT_CTRL*
PWM_HUD
TON
FLT
AGND PGND EP
CTON
RTON
LED1
HUD_OUT
LEDn
BOOST
VOUT
SYNCOUT
RSYNCOUT
DL2
RDL2
POWER-ON RESISTOR STRAP
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Maxim Integrated │ 30
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Table 3. Typical Application Example
VIN Typical Operating Range
V
CASE 1
CASE 2
CASE 3
High FSW,
Low FSW,
Low FSW,
Low Power
Low Power
High Power
8V to 16V
8V to 16V
8V to 16V
VIN UV Setting
V
7V
7V
7V
Boost Fsw
Hz
2MHz
400kHz
400kHz
Buck Fsw
Hz
750kHz
750kHz
750kHz
nLED
8
8
12
VLED (max)
V
3.25V
3.25V
3.25V
VOUT Buck
V
26V
26V
39V
ILED
A
1A
1A
1.5A
POUT
W
26W
26W
58.5W
V
35V
35V
55V
LBOOST
H
3.3μH
10μH
10μH
Boost Control FET
N2
BUK9Y59-60E
(59mΩ, 6.1nC Qg)
SQJ464EP
(20mΩ, 7.35nC Qg)
SQJA84EP
(11.2mΩ, 21nC Qg)
Boost Sync FET
N1
BUK9Y59-60E
(59mΩ, 6.1nC Qg)
BUK9M19-60E
(19mΩ, 13.8nC Qg)
BUK9Y25-80E
(27mΩ, 17.1nC Qg)
COUT Boost
F
2x 22μF/ 5mΩ
2x 22μF/5mΩ
2x 22μF/5mΩ
(derate 50%)
(derate 50%)
(derate 50%)
Compensation
50kΩ/1nF
50kΩ/1nF
50kΩ/1nF
RIN
Ω
10mΩ
10mΩ
5mΩ
LBUCK
H
39μH
39μH
39μH
Buck Control FET
N3
BUK9Y52-60E dual
(55mΩ, 5.6nC Qg)
BUK9Y52-60E dual
(55mΩ, 5.6nC Qg)
BUK9Y72-80E
(78mΩ, 7.9nC Qg)
Buck Sync FET
N4
BUK9Y52-60E dual
(55mΩ, 5.6nC Qg)
BUK9Y52-60E dual
(55mΩ, 5.6nC Qg)
BUK9Y72-80E
(78mΩ, 7.9nC Qg)
COUT Buck
F
RCS_LED
Ω
VOUT Boost Output Voltage
(margin Buck Dmax - 20%)
BOOST POWER STAGE
BUCK POWER STAGE
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1x1μF
1x1μF
1x1μF
(derate 50%)
(derate 50%)
(derate 50%)
150mΩ
150mΩ
100mΩ
Maxim Integrated │ 31
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Ordering Information
PART
PIN-PACKAGE
MAX25601AATJ/VY+
32 TQFN-EP (SW)*
MAX25601BAUI/V+
28 TSSOP-EP*
MAX25601CATJ/VY+
32 TQFN-EP (SW)*
MAX25601DAUI/V+
28 TSSOP-EP*
FEATURE
FEATURE
With HUD Driver
36V
No HUD Driver
36V
With HUD Driver
48V
No HUD Driver
48V
Note: All parts operate over the -40°C to +125°C automotive temperature range.
/V denotes an automotive-qualified part.
Y denotes side-wettable package.
+ denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed Pad
(SW) = Side-Wettable.
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Maxim Integrated │ 32
MAX25601A/MAX25601B/
MAX25601C/MAX25601D
Synchronous Boost and
Synchronous Buck LED Controllers
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
6/19
Initial release
1
7/19
Updated title from MAX25601 to MAX25601A/MAX25601B
1–32
2
9/19
Updated title from MAX25601A/MAX25601B to MAX25601A/MAX25601B/
MAX25601C/MAX25601D
1–32
3
1/20
Removed all remaining future-product indications from Ordering Information section
DESCRIPTION
—
32
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2019 Maxim Integrated Products, Inc. │ 33
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