3D7622D-5

3D7622 22-BIT PROGRAMMABLE PULSE GENERATOR (SERIES 3D7622 – SERIAL INTERFACE) FEATURES • • • • • • • • • All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Programmable via serial interface Increment range: 0.25ns through 50.0ns Pulse w idth tolerance: 1% (See Table 1) Supply current: 8mA typical Temperature stability: ±1.5% max (-40C to 85C) Vdd stability: ±0.5% max (4.75V to 5.25V) data 3 delay devices, inc. PACKAGE / PINOUT TRIG RES GND NC NC SO GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUT OUTB SI SC NC AE  3D7622D-xx SOIC For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION The 3D7622 device is a versatile 22-bit programmable monolithic pulse generator. A rising-edge on the trigger input (TRIG) initiates the pulse, which is presented on the output pins (OUT,OUTB). The pulse width, programmed via the serial interface, can be varied over 4,194,303 equal steps according to the formula: tPW = tinh + addr * tinc where addr is the programmed address, tinc is the pulse width increment (equal to the device dash number), and tinh is the inherent (address zero) pulse width. The device also offers a reset input (RES), which can be used to terminate the pulse before the programmed time has expired. The all-CMOS 3D7622 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL pulse generators. It is offered in a standard 14-pin SOIC. PIN DESCRIPTIONS TRIG RES OUT OUTB AE SC SI SO VDD GND NC Trigger Input Reset Input Pulse Output Complementary Pulse Output Address Enable Input Serial Clock Input Serial Data Input Serial Data Output +5 Volts Ground No Internal Connection TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER 3D7622D-0.25 3D7622D-0.4 3D7622D-0.5 3D7622D-1 3D7622D-2 3D7622D-2.5 3D7622D-4 3D7622D-5 3D7622D-10 3D7622D-20 3D7622D-25 * 3D7622D-40 * 3D7622D-50 * Pulse Width Step (ns) 0.25 ± 0.12 0.40 ± 0.20 0.50 ± 0.25 1.00 ± 0.50 2.00 ± 1.00 2.50 ± 1.25 4.00 ± 2.00 5.00 ± 2.50 10.0 ± 5.00 20.0 ± 10.0 20.0 ± 10.0 40.0 ± 20.0 50.0 ± 25.0 Minimum P.W. (ns) 10.0 ± 2.0 10.0 ± 2.0 10.0 ± 2.0 10.0 ± 2.0 10.0 ± 2.0 10.0 ± 2.0 10.0 ± 2.0 15.0 ± 5.0 24.0 ± 6.0 42.0 ± 8.0 15.0 ± 5.0 15.0 ± 5.0 15.0 ± 5.0 Maximum Pulse Width 1.05 ms ± 10 us 1.68 ms ± 17 us 2.10 ms ± 21 us 4.19 ms ± 42 us 8.39 ms ± 84 us 10.5 ms ± 105 us 16.8 ms ± 170 us 21.0 ms ± 210 us 41.9 ms ± 420 us 83.9 ms ± 840 us 105 ms ± 1.0 ms 168 ms ± 1.7 ms 210 ms ± 2.1 ms NOTES: Any increment between 0.25 and 50 ns not shown is also available as a standard device. * Some restrictions apply to dash numbers greater than 20. See application notes for more details. 2006 Data Delay Devices Doc #06007 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 3D7622 APPLICATION NOTES GENERAL INFORMATION Figure 1 illustrates the main functional blocks of the 3D7622. Since the 3D7622 is a CMOS design, all unused input pins must be returned to well-defined logic levels, VDD or Ground. The pulse generator architecture is comprised of a number of delay cells, which are controlled by the 6 LSB bits of the address, and an oscillator & counter, which are controlled by the 16 MSB bits of the address. Each device is individually trimmed for maximum accuracy and linearity throughout the address range. The change in pulse width from one address setting to the next is called the increment, or LSB. It is nominally equal to the device dash number. The minimum pulse width, achieved by setting the address to zero, is called the inherent pulse width. For dash numbers larger than 20, the 6 LSB bits are invalid, and the address loaded must therefore be a multiple of 64 (ie, 0, 64, 128, 192, etc). When used in this manner, the device is essentially a 16-bit generator, with an effective increment equal to 64 times the dash number. For best performance, it is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. Also, signal traces should be kept as short as possible. inherent width, and tinc is the nominal increment. It is very similar to the INL, but simpler to calculate. For most dash numbers, the relative error is less than 1.0 LSB at every address (see Table 1). The absolute error is defined as follows: eabs = tPW – (tinh + addr * tinc) where tinh is the nominal inherent delay. The absolute error is limited to 1.5 LSB or 3.0 ns, whichever is greater, at every address. The inherent pulse width error is the deviation of the inherent width from its nominal value. It is limited to 1.0 LSB or 2.0 ns, whichever is greater. PULSE WIDTH STABILITY The characteristics of CMOS integrated circuits are strongly dependent on power supply and temperature. The 3D7622 utilizes novel compensation circuitry to minimize the performance variations induced by fluctuations in power supply and/or temperature. With regard to stability, the output pulse width of the 3D7622 at a given address, addr, can be split into two components: the inherent pulse width (tinh) and the relative pulse width (tPW – tinh). These components exhibit very different stability coefficients, both of which must be considered in very critical applications. The thermal coefficient of the relative pulse width is limited to ±250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of ±1.5% from the room-temperature pulse width. This holds for all dash numbers. The thermal coefficient of the inherent pulse width is nominally +10ps/C for dash numbers less than 1, and +15ps/C for all other dash numbers. The power supply sensitivity of the relative pulse width is ±0.5% over the 4.75V to 5.25V operating range, with respect to the pulse width at the nominal 5.0V power supply. This holds for all dash numbers. The sensitivity of the inherent pulse width is nominally –1ps/mV for all dash numbers. It should also be noted that the DNL is also adversely affected by thermal and supply variations, particularly at the MSL/LSB crossovers (ie, 63 to 64, 127 to 128, etc). PULSE WIDTH ACCURACY There are a number of ways of characterizing the pulse width accuracy of a programmable pulse generator. The first is the differential nonlinearity (DNL), also referred to as the increment error. It is defined as the deviation of the increment at a given address from its nominal value. For most dash numbers, the DNL is within 0.5 LSB at every address (see Table 1: Pulse Width Step). The integrated nonlinearity (INL) is determined by first constructing the least-squares best fit straight line through the pulse-width-versusaddress data. The INL is then the deviation of a given width from this line. For all dash numbers, the INL is within 1.0 LSB at every address. The relative error is defined as follows: erel = (tPW – tinh) – addr * tinc where addr is the address, tPW is the measured width at this address, tinh is the measured Doc #06007 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D7622 APPLICATION NOTES (CONT’D) TRIGGER & RESET TIMING Figure 2 shows the timing diagram of the device when the reset input (RES) is not used. In this case, the pulse is triggered by the rising edge of the TRIG signal and ends at a time determined by the address loaded into the device. While the pulse is active, any additional triggers occurring are ignored. Once the pulse has ended, and after a short recovery time, the next trigger is recognized. Figure 3 shows the timing for the case where a reset is issued before the pulse has ended. Again, there is a short recovery time required before the next trigger can occur. As shown in the figure, most of the address information for the next pulse can be loaded while the current pulse is active. It is only on the falling-edge of AE that the device adjusts to the new pulse width setting. In other words, the device controller does not need to wait for the current pulse to end before beginning an address update sequence. This can save a considerable amount of time in certain applications. As data is shifted into the serial data input (SI), the previous contents of the 22-bit input register are shifted out of the serial output pin (SO) in MSB-to-LSB order. This allows cascading of multiple devices by connecting SO of the preceding device to SI of the succeeding device, as illustrated in Figure 5. The total number of serial data bits in a cascade configuration must be 22 times the number of units, and each group of 22 bits must be transmitted in MSB-to-LSB order. ADDRESS UPDATE While observing data setup (tDS) and data hold (tDH) requirements, timing data is loaded in MSBto-LSB order by the rising edge of the clock (SC) while the enable (AE) is high, as shown in Figure 4. The falling edge of the AE activates the new pulse width value, which is reflected at the output upon the next trigger. TRIGGER TRG RESET RES INPUT LOGIC DELAY LINE OSCILLATOR/ COUNTER OUTPUT LOGIC OUT OUTB PULSE OUT 6 LSB 16 MSB ADDR ENABLE AE 22-BIT LATCH 22-BIT INPUT REGISTER SERIAL IN SI SERIAL CLK SC SO SERIAL OUT Figure 1: Functional block diagram Doc #06007 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D7622 APPLICATION NOTES (CONT’D) tTW TRIG tID OUT OUTB tPW tRTO Figure 2: Timing Diagram (RES=0) tTW TRIG tRW RES tRTR tID OUT OUTB tRD Figure 3: Timing Diagram (with reset) AE tES SC tCW tCW tEH tDH tDS SI SO TRIG A21 A20 A19 A1 A0 tEV OLD A21 OLD A20 tCQ OLD A19 OLD A18 OLD A0 tEX A21 tAT tOA OUT Figure 4: Address Update SI 3D3622 SC AE SO SI 3D3622 SC AE SO SI 3D3622 AE SO FROM SERIAL SOURCE SC TO NEXT DEVICE Figure 5: Cascading Multiple Devices Doc #06007 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 3D7622 DEVICE SPECIFICATIONS TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -10 -55 MAX 7.0 VDD+0.3 10 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 4.75V to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL TR & TF MIN 2.0 0.8 1.0 1.0 -4.0 TYP 8.0 MAX 12.0 UNITS mA V V µA µA mA mA 2.5 ns NOTES -35.0 4.0 15.0 2.0 VIH = VDD VIL = 0V VDD = 4.75V VOH = 2.4V VDD = 4.75V VOL = 0.4V CLD = 5 pf *IDD(Dynamic) = 2 * CLD * VDD * F where: CLD = Average capacitance load/output (pf) F = Trigger frequency (GHz) Input Capacitance = 5 pf typical Output Load Capacitance (CLD) = 25 pf max TABLE 4: AC ELECTRICAL CHARACTERISTICS (-40C to 85C, 4.75V to 5.25V) PARAMETER Trigger Width Trigger Inherent Delay Output Pulse Width Re-trigger Time Reset Width Reset to Output Low End of Reset to Next Trigger AE High to First Clock Edge AE High to Serial Output Valid Serial Clock Width Data Setup to Clock Data Hold from Clock Clock to Serial Output Last Clock Edge to AE Low Output Low to AE Low AE Low to Serial Output High-Z AE Low to Trigger SYMBOL tTW tID tPW tRTO tRW tRD tRTR tES tEV tCW tDS tDH tCQ tEH tOA tEX tAT MIN 5 TYP MAX 5 3 TBD 5 3 10 20 8 10 3 8 8 TBD 20 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns REFER TO Figure 2 & 3 Figure 2 & 3 Figure 2 Figure 2 Figure 3 Figure 3 Figure 3 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Doc #06007 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 5 3D7622 TYPICAL APPLICATIONS EN TRIG RES OUT OUTB FOUT AE SCLK SDAT AE SC SI 3D7622 SO FOUT = 1 / (tPW + tID + tNOR) EN tID + tNOR FOUT Figure 5: Programmable Oscillator IN 0V TRIG RES AE SC SI OUT OUTB +5 SETB D CK RESB OUT D-FF Q QB 3D7622 R-Edge Delay SO TRIG 0V RES AE SC SI OUT OUTB +5 SETB D CK RESB AE SCLK SDAT 3D7622 F-Edge Delay SO D-FF Q QB IN tPW R + tID + tFF OUT tPW F + tID + tFF Figure 6: Programmable Delay Line Doc #06007 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 6 3D7622 SILICON DEVICE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (Vcc): 5.0V ± 0.1V Input Pulse: High = 3.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 20ns Period: PERIN = 2 x Prog’d Pulse Width OUTPUT: Rload: Cload: Threshold: 10KΩ ± 10% 5pf ± 10% 1.5V (Rising & Falling) Dev ice Under Test 10KΩ 5pf Digital Scope 470Ω NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER REF PULSE GENERATOR OUT TRIG TRIG DEVICE UNDER TEST (DUT) OUT IN TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER Figure 8: Test Setup PERIN PW IN tRISE INPUT SIGNAL 2.4 1.5 0.6 tFALL VIH 2.4 1.5 0.6 VIL tPW tID OUTPUT SIGNAL 1.5 VOH 1.5 VOL Figure 9: Timing Diagram Doc #06007 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 7