AP7217

AP7217 500mA CMOS LDO Description The AP7217 low-dropout linear regulator operates from a 3.3V to 5.5V supply and delivers a guaranteed 500mA (min) continuous load current. Pin Assignments ( Top View ) NC 1 2 8 7 EN GND VDOUT NC The high-accuracy output voltage is preset to an internally trimmed voltage. An active-low open-drain reset output remains asserted for at least 20ms (TYP) after output voltage reaches VDF. The space-saving SOP-8L package is suitable for “pocket” and hand-held applications. VROUT NC VIN AP7217 3 4 6 5 SOP-8L Features • • • • • • • Very Low Dropout Voltage Low Current Consumption: Typ. 50μA Output Voltage: 3.3V Guaranteed 500mA (min) Output Input Range up to 5.5V Current Limiting Stable with either electrolytic capacitor or low-ESR MLCC (multi-layer ceramic capacitor) Low Temperature Coefficient SOP-8L: Available in “Green” Molding Compound (No Br, Sb) Lead Free Finish/ RoHS Compliant (Note 1) Applications • • • • HD/ BlueRay DVD & MP3/4 Players Mobile Handsets and Smartphones Digital Still Camera Hand-Held Computers • • Notes: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html. Typical Application Circuit U1 VIN 100K CIN 1uF VDOUT 4 VIN VROUT 2 VROUT ON AP7217 6 VDOUT GND 7 EN 8 OFF COUT 1uF AP7217 Document number: DS31292 Rev. 4 - 2 1 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Functional Block Diagram EN On Off Enable VIN Bandgap 1.2V R1 VDOUT ERROR AMP Current Limit VROUT + + VD Comp. R3 R2 R4 GND Pin Descriptions Pin Name NC VROUT NC VIN NC VDOUT GND EN Pin No. 1 2 3 4 5 6 7 8 No Connection Voltage Output No Connection Supply Voltage No connection VD Output (Reset on I/P) Ground Enable (VR On/Off) Description AP7217 Document number: DS31292 Rev. 4 - 2 2 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Absolute Maximum Ratings Symbol ESD HBM ESD MM VIN IOUT VROUT TJ TJ(MAX) PD Parameter Human Body Model ESD Protection Machine Model ESD Protection Input Voltage Output Current Output Voltage Operating Junction Temperature Range Maximum Junction Temperature Internal Power Dissipation Rating 2 450 +6 PD/ (VIN-VO) GND - 0.3 ~ VIN+ 0.3 -40 to +125 150 1.2 Unit KV V V mA V ºC ºC W Recommended Operating Conditions Symbol VIN IOUT TA Input Voltage Output Current Operating Ambient Temperature Parameter Min 3.3 0 -40 Max 5.5 500 85 Unit V mA ºC AP7217 Document number: DS31292 Rev. 4 - 2 3 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Electrical Characteristics (VIN = 12V, TA = +25°C, unless otherwise noted) (TA = 25°C, CIN = 1µF, COUT = 1µF, VEN = VIN, unless otherwise noted) Symbol IQ ISTB Parameter Quiescent Current Standby Current IO = 0mA Test Conditions VEN = Off VIN = 5.0V Min - Typ. 50 15 Max 70 30 Unit μA μA V ppm / o C Output Voltage Accuracy IO = 30mA, VIN = 5V VROUT VROUT Temperature Coefficient Dropout Voltage Maximum Output Current Current Limit Short Circuit Current -40°C to 85°C, IOUT = 30mA IOUT = 100mA VIN = 5.3V VIN = 5.3V VIN = 5.3V 4.3V ≤ VIN ≤ 5.5V; IOUT = 30mA 1mA ≤ IOUT ≤ 100mA, VIN = 5.3V F= 1KHz 3.234 3.300 ±100 100 3.366 VDROPOUT IOUT ILIMIT Ishort ΔVROUT PSRR VEH VEL IEN VDF VHysteresis 250 mV mA 500 600 50 0.01 15 55 1.6 0.25 -0.1 3.83 VDF x1.02 3.91 VDF x1.05 20 30 10 20 134 28 40 0.1 3.98 VDF x1.08 ±0.2 50 mA mA %/V mV dB V V μA V V mA ΔVLINE/ΔVIN/VROUT Line Regulation Load Regulation VIN = 4.3V+ 0.5VpPower Supply Rejection pAC, IOUT = 50mA EN Input Threshold Enable Pin Current Detect fall voltage VD Hysteresis Range VDOUT = 0.5V Output ON Output OFF IVDOUT tRP θJA θJC Notes: VD Supply Current VDOUT Delay Time Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case VIN = 2.0V 3.0V VIN = 1.8V to VDF+ 1V SOP-8L (Note 2) SOP-8L (Note 2) mSec ºC/W ºC/W 2. Test conditions for SOP-8L: Devices mounted on FR-4 PC board, MRP, 2oz copper layout, calibrate at TJ=150 ºC, measure at TA=25ºC, minimum recommended pad layout AP7217 Document number: DS31292 Rev. 4 - 2 4 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Typical Performance Characteristics Vcc vs. Quiescent current 100 90 80 Iout vs. Dropout voltage 1000 900 800 Iccq (uA) 60 50 40 30 20 10 0 3.6 4 4.3 5 5.5 Dropout (mV) 70 700 600 500 400 300 200 100 0 30 100 300 500 Vcc (V) Iout (mA) Delay time vs. Temperature 24 23 22 70 60 50 40 30 20 10 0 Vcc vs. Standby current Delay time (mS) 20 19 18 17 16 15 -40 25 85 100 I-standby (uA) 21 3.6 4 4.3 5 5.5 Temperature(o C) Vcc (V) AP7217 Document number: DS31292 Rev. 4 - 2 5 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Typical Performance Characteristics (Continued) Load Transient Response (VIN=4.3V, IOUT=0~500mA) VIN VIN VROUT IOUT VROUT IOUT Load Transient Response (VIN=5.5V, IOUT=0~500mA) Load Transient Response (VIN=4.3V, IOUT=100~300mA) VIN VIN VROUT VROUT Load Transient Response (VIN=5.5V, IOUT=100~300mA) IOUT IOUT AP7217 Document number: DS31292 Rev. 4 - 2 6 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Timing Diagram tRP 20mSec-TYP. 1.8V VIN VDOUT EN VROUT Application Note Input Capacitor A 1μF ceramic capacitor is recommended to connect between IN and GND pins to decouple input power supply glitch and noise. The amount of the capacitance may be increased without limit. A lower ESR (Equivalent Series Resistance) capacitor allows the use of less capacitance, while higher ESR type requires more capacitance. This input capacitor must be located as close as possible to the device to assure input stability and less noise. For PCB layout, a wide copper trace is required for both IN and GND. Output Capacitor The output capacitor is required to stabilize and help the transient response of the LDO. The AP7217 is designed to have excellent transient response for most applications with a small amount of output capacitance. The AP7217 is stable with any small ceramic output capacitors of 1.0μF or higher value, and the temperature coefficients of X7R or X5R type. Additional capacitance helps to reduce undershoot and overshoot during transient. For PCB layout, the output capacitor must be placed as close as possible to OUT and GND pins, and keep the leads as short as possible. ENABLE/SHUTDOWN Operation The AP7217 is turned on by setting the EN pin high, and is turned off by pulling it low. If this feature is not used, the EN pin should be tied to IN pin to keep the regulator output on at all time. To ensure proper operation, the signal source used to drive the EN pin must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. VROUT 0V 3.3V VDOUT Φ Φ EN=0 EN=1 Current Limit Protection When output current at OUT pin is higher than current limit threshold, the current limit protection will be triggered and clamp the output current to approximately 600mA to prevent over-current and to protect the regulator from damage due to overheating. AP7217 Document number: DS31292 Rev. 4 - 2 7 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Application Note Short circuit protection When VRout pin is shorted to GND or VRout voltage is less than 200mV, short circuit protection will be triggered and clamp the output current to approximately 50mA. VDOUT (reset output) ---Open-Drain Active-Low reset output--In general, VDOUT is pulled up by a resistor (100Kohm) to VIN. The AP7217 microprocess (uP) supervisory circuitry asserts a guaranteed logic-low reset during power-up and power-down. Reset is asserted asserts when VIN is below the reset threshold and remain asserted for at least tRP after VIN rises above the reset threshold. As long as VIN is lower than the reset threshold, VDOUT remains at logic "0". When VIN become higher than VTH, a logic "1" is asserted after a time delay defined by tRP. Ordering Information AP 7217 - 33 S G - 13 Output voltage 33 : 3.3V Package S : SOP-8L Green G : Green Packing 13 : Tape & Reel Device AP7217-33SG-13 Notes: Package Code S Packaging (Note 3) SOP-8L 13” Tape and Reel Quantity Part Number Suffix 2500/Tape & Reel -13 3. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. Marking Information ( Top View ) 8 5 Logo Part Number 7217-33 YY WW X X 1 4 YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X : Internal Code G : Green AP7217 Document number: DS31292 Rev. 4 - 2 8 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Package Outline Dimensions (All Dimensions in mm) 3.85/3.95 5.90/6.10 0.10/0.20 0.254 0.62/0.82 Gauge Plane Seating Plane Detail "A" 7°~9° 1.30/1.50 1.75max. 0.15/0.25 0.35max. 45° 7°~9° Detail "A" 0°/8° 1.27typ 4.85/4.95 0.3/0.5 8x-0.60 5.4 6x-1.27 8x-1.55 Land Pattern Recommendation (Unit: mm) AP7217 Document number: DS31292 Rev. 4 - 2 9 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 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