EU1020

eorex Features • 2.2V to 5.5V Input Voltage Range • 14 I/O ports in EU1020 • RAM size: 128 x 8 bits • The STACK RAM is included. • Program ROM size: 4K x 8 bits OTP • 10 bits A/D Converter input source. EU1020: 4 channels • One set of 16-bit down count timer and one set of 8-bit timer. • Operating temperature: -40 ~ +125 ℃ • Build-in Low Voltage Reset (LVR) circuit. • Oscillator: Internal RC oscillation. EU1020 8-bit MCU with 10-bit A/D Converter Description The EU1020 is an OTP type 8-bit micro-controller with 4 channels of 10-bit A/D converter using advanced CMOS process. The EU1020 is specially designed for various industrial field applications. The EU1020 incorporates two sets of 8-bit timer/counters, where timer0/1 is specially designed for PWM (Pulse Width Modulation) generator. There are 14 I/O ports with EU1020, respectively. Considering form factor and manufacturability, the EU1020 is packaged into 16-pin non-JEDEC-standard compact-size SOP. Ordering Information Feb.2009 1/21 www.eorex.com eorex Pin Assignment PB[2] PB[1] PB[0] VSS VDD PA[0] PA[1] PA[2] 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PB[3] PB[4] PB[5] PB[6] PA[6] PA[5] PA[4] PA[3] EU1020 SOP-16L Pin Description Pin Name VDD VSS PA0~PA6 I/O Function Positive power supply Ground Input and output ports. In input mode, all PA pins could be set an internal pull-up resistor (R=100Kohm). In output mode, it could be optioned as CMOS or NMOS output independently. Also, PA0~PA3 could be optioned as 4 channels of 10-bit A/D converter input pins. Input and output ports. In input mode, it could have optioned internal pull-up resistor with 100Kohm. Also, it can be set as HALT and STOP mode released source when the input signal is changed from high to low. In output mode, it could be optioned as CMOS or NMOS output independently. I/O PB0~PB6 I/O Feb.2009 2/21 www.eorex.com eorex MCU Description Item Accumulator Abbreviation ACC Description EU1020 The EU1020 has an 8-bit register used for data hold, exchange, arithmetic, transfer and I/O operation. In EU101x that builds in two index registers ( X and Y ). These two index registers could be used to count program steps or to provide an index value to be used in generating as effective address. When executing an instruction which specifies indexed addressing, the MCU fetches the operation code and the base address, and modifies the address by adding the index register to its prior to perform the desired operation. Per or post-index of indirect address is possible. The EU102x includes some special function control registers in zero-page. For more detailed information about the special function registers, please refer to next section. The stack pointer is an 8-bit register that is used to control the addressing of the variable-length stack. The stack pointer is automatically incremented and decremented under control of the microprocessor the perform stack manipulations under direction of either the program or interrupts. The stack allows a simple implementation of nested subroutines and multiple level interrupts. The stack pointer is initialized by the user ’s software. The 14-bit program counter register provides the address that step the microprocessor through sequential program instructions. The 8-bit status flag register contains seven status flags. Some of the flags are controlled by the program and others may be controlled both by the program and the MCU. Instruction set contains a number of conditional branch instructions that are designed to allow testing of these flags. Index Register (X,Y) Special Function Register SFR Stack pointer register SP Program counter PC Program Flag Register P Feb.2009 3/21 www.eorex.com eorex Memory 0000H Special Function Register 0022H Un-used 00A0H 00FFH 0100H Data & Stack RAM : 32 x 8 bits 011FH Un-used 2000H Program ROM : 4K x 8 bits 2FFFH Figure_A Memory mapping diagram EU1020 The EU1020 has a 14-bit program counter which can totally address 16K x 8 bits. All the special function registers, data RAM, stack RAM and program ROM are assigned in this area as the following diagram. ( zero page ) Data RAM : 96 x 8 bits Program ROM The EU1020 contains 4Kx8 bit program OTP and its addressing size is assigned from $2000H to $2FFFH. After power on reset, the data restored in addresses $2FFCH and $2FFDH are loaded into program counter. It means that RESET vector address is located in $2FFCH and $2FFDH. Data RAM and STACK RAM The EU1020 data RAM are located from $A0H to $11FH. All the data RAM area from $A0H to $0FFH could be accessed by zero-page addressing mode. That STACK RAM could be accessed from $100H to $11FH. Actually, the area of $100H ~ $11FH, could be accessed as data RAM or STACK RAM. User needs to preset stack pointer (SP) after power on reset. Program Counter (PC) should be initialized after power on reset that ROM address $2FFCH and $2FFDH content will be loaded into Program Counter. Feb.2009 4/21 www.eorex.com eorex Special Function Register (SFR) EU1020 Special function register area is during the addresses from $00H to $22H. These special function registers control all I/O and timer function setting. Some of memory addresses are not defined and un-used. It is unnecessary for the users to read or write data from these undefined areas. User should follow the default value or do not access these undefined area. All its functions are listed in next sections. Interrupt and Timers Address 00H Bit7 ADINT R/W 0 Bit6 # # # Bit5 # # # Bit4 T1INT R/W 0 Bit3 T0INT R/W 0 Bit2 PBINT R/W 0 Bit1 TBINT R/W 0 Bit0 RTCINT R/W 0 NAME INTEN Read or Write Default Value The EU1020 builds in 8 interrupt sources: Real Time Clock interrupt, Time Base interrupt, PB input ports falling edge interrupt, Timer0 underflow interrupt, Timer1 underflow interrupt, A/D converter interrupt and RESET interrupt. By setting control register INTEN (00H) that can enable or disable corresponding interrupt sources. Interrupt source, interrupt vector address mapping and its priority are shown in the following table. Address 2FFF0H/2FF1H 2FF2H/2FF3H 2FF4H/2FF5H 2FF6H/2FF7H 2FF8H/2FF9H 2FFAH/2FFBH 2FFCH/2FFDH 2FFEH/2FFFH Interrupt Source ADC interrupt Timer1 interrupt Timer0 interrupt PB port interrupt Time base interrupt RTC interrupt Reset Reserved Priority 7 6 5 4 3 2 1 0 Feb.2009 5/21 www.eorex.com eorex RTC timer, Base timer interrupt and Watch Dog timer EU1020 Address 03H Bit7 # W 0 Bit6 BASE1 W 0 Bit5 BASE0 W 0 Bit4 RTC1 W 0 Bit3 RTC0 W 0 Bit2 Bit1 Bit0 RESEL0 W 0 NAME UCCLK Read or Write Default Value RCSEL2 RCSEL1 W 0 W 0 Real time counter The EU1020 build-in a real time counter interrupt and its clock source is Fosc. Its frequency could be optioned by UCCLK.4 & UCCLK.3 that could select real time interrupt frequency. For example, if the clock source come from ExCLK/PB3 (when CKSEL=1) and the input frequency is 32,768Hz, select “[RTC1, RTC0] = [0, 1]” and it will cause 2Hz interrupt when real time counter interrupt enabled (RTCINT=1) & (RTCEN=1). RTC1 0 0 1 1 RTC0 0 1 0 1 TRTC TT/32 TT/64 TT/128 TT/256 Feb.2009 6/21 www.eorex.com eorex Base Timer BASE1 0 0 1 1 BASE0 0 1 0 1 TBASE TT/2 TT/4 TT/8 TT/16 EU1020 Base timer is optioned from [BASE1, BASE0] and it will cause a period timer base interrupt enabled (TBINT=1) & (TBEN=1). MCU clock selection With a built-in internal RC oscillator, the MCU frequency (Fosc) is 4MHz ±3% @4.5V. MCU system clock (Fsys) offers 4MHz, 2MHz, 1MHz, 500KHz or 250KHz by MCU clock options bit; RCSEL2~0. Please refer to the following table. Address Name 03H UCCLK bit7 # # 0 bit6 bit5 bit4 RTC1 W 0 bit3 bit2 bit1 bit0 BASE1 BASE0 W 0 W 0 RTC0 RCSEL2 RCSEL1 RCSEL0 W 0 W 0 W 0 W 0 Read or Write Default Value The MCU system clock could be switched by setting RCSEL2~0. First, pre-set RCSEL2~0 register and then execute “HALT” instruction. After then, MCU wake-up from HALT mode, MCU system frequency is already changed to the new setting frequency. RCSEL2 0 0 0 0 1 RCSEL1 0 0 1 1 # RCSEL0 0 1 0 1 # Frequency of MCU system clock (Fsys) 250KHz 500KHz 1MHz 2MHz 4MHz (Fosc) Feb.2009 7/21 www.eorex.com eorex TMRC register Address 01H Bit7 Bit6 Bit5 WDTEN R/ W 0 Bit4 WDTF R/W # Bit3 TBEN R/W 0 Bit2 TBF R/W # NAME TMRC Read or Write Default Value WDT Divide W 0 W 0 EU1020 Bit1 RTCEN R/W 0 Bit0 RTCF R/W # *TMRC.0(RTCF) : real time counter transient flag. Once TRTC signal is transient, this flag will be set as RTCF=1 by hardware. This bit could be cleared by software. *TMRC.1(RTCEN) : real time counter enable/disable flag. RTCEN = 1, enable real time counter; RTCEN = 0, disable real time counter. *TMRC.2(TBF) : base timer transient flag. Once TBASE signal is transient, this flag will be set as TBF=1 by hardware. This bit could be cleared by software. *TMRC.3(TBEN) : Base timer enable/disable flag. TBEN = 1, enable base timer; TBEN = 0, disable base timer. Watchdog Timer Watchdog timer block diagram is shown as figure_B. The clock source comes from CPU system clock. Figure_B Note: *Once TMRC.5 (WDTEN) is set as “1”, the watchdog timer will start to count till the watchdog timer overflows, and then the TMRC.4 (WDTF) is set as “1”. Meanwhile, CPU will have a warm reset by hardware and the data in addresses $2FFCH and $2FFDH will be loaded into program counter. Watchdog timer can be cleared by setting TMRC.5 (WDTEN=0). Please note well that the EU1020 watchdog timer is preset as disable after power on reset. Once watchdog timer is enabled by setting TMRC.5=1, watchdog timer won’t be stopped by software. Set TMRC.5=0 will just clear watchdog timer counter. Feb.2009 8/21 www.eorex.com eorex WDT divider TMRC (01H) FSYS/2 FSYS/4 FSYS/8 FSYS/16 bit7 0 0 1 1 bit6 0 1 0 1 EU1020 PB ports interrupt PB6~0, in input mode, could be optioned as external interrupt source by setting PBINT (00H.2) = 1. When the interrupt enabled and external signal changed from high to low, the PB port interrupt will take into action and its interrupt vector is $2FF6H and $2FF7H. A falling edge signal at PB ports will wake up CPU from HALT or STOP mode. When PB port interrupt is enabled (PBINT=1), CPU will wake up from HALT or STOP mode, and serve PB port interrupt first and then execute next instruction. If PB port interrupt is disabled, CPU will just be waked up and then execute next instruction only. User should check which PB port the falling edge signal comes from by PBF control register. If the falling edge is from PB0, the PBF.0 will be set to “1” by hardware. These flags could be cleared by software. Address NAME 02H PBF Bit7 # # # Bit6 PBF6 R/W 0 Bit5 PBF5 R/ W 0 Bit4 PBF4 R/W 0 Bit3 PBF3 R/W 0 Bit2 PBF2 R/W 0 Bit1 PBF1 R/W 0 Bit0 PBF0 R/W 0 Read or Write Default Value Timer0 Timer0 is an 8-bit down count timer. Its clock source comes from CPU main-oscillator (FOSC) or ExCLK/PB3, which is listed in figure 4-3. User can preset timer0 counter by setting data into timer0 preload buffer T0BF(04H). The data read from T0BF(04H) will be the current count of timer0. Timer0 will down count by every input clock when T0EN=1. When timer0 down count from 00H to FFH, T0F will be set to “1” and if T0INT =1, the timer0 interrupt will occur. Timer0 will automatically reload data from T0BF/04H (timer0 preset buffer). Therefore, user can preset timer0 new data into T0BF(04H) before timer0 underflow and cause different interrupt time duties. That is, timer0 data will be loaded from T0BF buffer after T0EN bit is set as “1” or timer0 underflows. Feb.2009 9/21 www.eorex.com eorex Address Name 04H T0BF bit7 1/0 R/W # bit6 1/0 R/W # bit5 1/0 R/W # bit4 1/0 R/W # bit3 1/0 R/W # bit2 1/0 R/W # Read or Write Default Value EU1020 bit1 1/0 R/W # bit0 1/0 R/W # Address Name 05H T0C bit7 T0EN R/W 0 bit6 T0F R/W # bit5 T0CK R/W # bit4 # # # bit3 # # # bit2 bit1 bit0 Timer0 pre-scaler R/W # R/W # R/W # Read or Write Default Value Note: *T0EN : timer0 enable flag T0EN = 1, load T0BF content (preload buffer data) into timer0 and enable timer0 start to down count. T0EN = 0, stop timer0 counting. User can get timer0 data by reading T0BF register. (LDA T0BF) * when T0EN=0, write data to T0BF(04H), data will be directly passed to timer0 counter. T0F : timer0 underflow flag T0F = 1, timer0 underflow; T0F = 0, timer0 not underflow. *T0CK : timer0 clock source option bit T0CK = 1, clock source from ExCLK/PB3 pin. User can set T0CK=1, ExCLK/PB3 is optioned as external clock input pin that connect to Timer0. Before this, user should set PBIO.3=1 and PBMD.3 internal pull-up resistor could be enabled or disabled. T0CK = 0, clock source from Fosc. *There is no default data with T0CK bit, user should preset this bit after power on reset. bit2 0 0 0 0 1 bit1 0 0 1 1 # bit0 0 1 0 1 # Timer0 pre-scaler(FCLK0= ) FSYS/1 FSYS/2 FSYS/4 FSYS/8 FSYS/16 Feb.2009 10/21 www.eorex.com eorex EU1020 Note: *Bit2~0 are timer0 clock source selection bits. They must follow the setting listed below. If the bit2=1, it would be divided by 16 while bit1 and bit0 could be any data. When T0CK=1, don’t care bit2~0 data. Figure_C Timer1 Address Name 06H T1BF0 bit7 1/0 R/W # bit6 1/0 R/W # bit5 1/0 R/W # bit4 1/0 R/W # bit3 1/0 R/W # bit2 1/0 R/W # bit1 1/0 R/W # bit0 1/0 R/W # Read or Write Default Value Address Name 07H T1BF1 bit7 1/0 R/W # bit6 1/0 R/W # bit5 1/0 R/W # bit4 1/0 R/W # bit3 1/0 R/W # bit2 1/0 R/W # bit1 1/0 R/W # bit0 1/0 R/W # Read or Write Default Value Timer1 is a 16-bit down count timer. T1BF0(06H)/low byte and T1BF1(07H)/high byte are timer1 preload buffer. Timer1 clock source could come from CPU main oscillator (Fosc), refer to figure_D. Timer1 can work in two kinds of operating mode. One mode is normal 16-bit timer/counter mode and the other one is specially designed for different interrupt time period. Figure_D Feb.2009 11/21 www.eorex.com eorex Timer/counter mode EU1020 If T1C.4 (08H.4)=PWM1=0, timer1 works as 16-bit timer/counter mode, register timer1 will down count by every input clock when timer1 turns on by T1EN=1. When timer1 is down count from 0000H to FFFFH, T1F bit will be set to “1”. At the same time, if T1INT=1, the timer1 interrupt occurs. Timer1 will automatically reload data from preload buffer T1BF0(06H) and T1BF1(07H). Therefore, user can preset T1BF0(06H) and T1BF1(07H) buffer data before different interrupt time duties caused by timer1 underflow. It means that timer1 data will be loaded from T1BF0(06H) and T1BF1(07H) buffer after T1EN bit is set as “1” or timer1 underflow. Address 08H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Name T1C T1EN T1F T1CK PWM # `Timer1 pre-scaler Read or Write W R/W R/W W 0 # W W W Default Value 0 # # # # # # Note: *T1EN : timer1 enable flag T1EN = 1, enable timer1 start to down count; T1EN = 0, stop timer1 down count. (when T1EN=0 and write data into T1BF0(06H) and T1BF1(07H) , the data will be directly passed to timer1 counter.) *T1F : timer1 underflow flag T1F = 1, timer1 underflow; T1F = 0, timer1 not underflow. Bit2~bit0 are timer1 clock source selection bits. It must follow the setting as below. bit2 0 0 0 0 1 bit1 0 0 1 1 # bit0 0 1 0 1 # Timer1 pre-scaler (FCLK1= ) FOSC/1 FOSC/2 FOSC/4 FOSC/8 FOSC/16 Feb.2009 12/21 www.eorex.com eorex PWM Mode EU1020 Set T1C.4=1(PWM=1), Timer-1 will work in PWM mode. User can preset T1BF0 and T1BF1. Timer1 interrupt will have two kinds of time duties based on T1BF0 and T1BF1 data. I/O ports PA ports (PA6 ~ PA0) are 8-bits I/O ports. System can either output data by writing data into PA(10H) ports or read data from input mode by reading PA(10H) ports. When PA ports are set in output mode, it can be optioned by software as CMOS or NMOS output. Set in input mode, PA ports can be optioned as internal pull up or input with floating status. Also, PA6~0 could be optioned as A/D converter analog signal input pins. Please refer to A/D Converter section. Address Name 10H PA bit7 # # bit6 1/0 # bit5 1/0 # bit4 1/0 # bit3 1/0 # bit2 1/0 # bit1 1/0 # bit0 1/0 # Default Value PAIO register: control PA port either as input mode or output mode. PAIO register can be set partially bits in input mode and partial bits in output mode. Address Name 11H PAIO bit7 # # bit6 1/0 1 bit5 1/0 1 bit4 1/0 1 bit3 1/0 1 bit2 1/0 1 bit1 1/0 1 bit0 1/0 1 Default Value Note: *PAIO.n = 1, set as input mode. PAIO.n = 0, set as output mode. (Please be noted that PAIO.0 default data is “0”.) That n = 6 ~ 0. Feb.2009 13/21 www.eorex.com eorex PACN register: control output mode as CMOS or NMOS output. Address Name 12H PACN bit7 # # bit6 1/0 0 bit5 1/0 0 bit4 1/0 0 bit3 1/0 0 bit2 1/0 0 Default Value EU1020 bit1 1/0 0 bit0 1/0 0 Note: *PACN.n = 1, set as CMOS output; PACN.n = 0, set as NMOS output. That n = 6 ~ 0. PAPH register: enable/disable PA ports internal pull high when PA port is set as input mode. Address Name 13H PAPH bit7 # # bit6 1/0 0 bit5 1/0 0 bit4 1/0 0 bit3 1/0 0 bit2 1/0 0 bit1 1/0 0 bit0 1/0 0 Default Value Note: *PAPH.n = 1, internal pull high resister enable; PAPH.n = 0, internal pull high resister disable, where n = 6 ~ 0. PB ports PB ports (PB6 ~ PB0) are 8-bit I/O ports. User can either output data by writing data into PB(14H) ports. Or read data at input mode by reading PB(14H) ports. Address Name 14H PB bit7 # # bit6 1/0 # bit5 1/0 # bit4 1/0 # bit3 1/0 # bit2 1/0 # bit1 1/0 # bit0 1/0 # Default Value PBR register Address Name 15H PBR bit7 # # bit6 1/0 0 bit5 1/0 0 bit4 1/0 0 bit3 1/0 0 bit2 1/0 0 bit1 1/0 0 bit0 1/0 0 www.eorex.com 14/21 Default Value Feb.2009 eorex Note: EU1020 *PBR.n = 1, enable HALT or STOP mode released by input falling edge signal; PBR.n = 0, disable HALT or STOP mode release, where n = 6 ~ 0. *Setting PBR.n register as “1” can enable to release HALT or STOP mode by PB port input signal from high to low. After HALT or STOP mode released, the oscillator will oscillate at the same time. If PBINT=1, PB-interrupt subroutine will start. If PBINT=0, the program counter will execute the next instruction after HALT or STOP. PBIO register: control PB port as input or output mode. Also, it can be set as partial bits in input mode and partial bits in output mode. Address Name 16H PBIO bit7 # # bit6 1/0 1 bit5 1/0 1 bit4 1/0 1 bit3 1/0 1 bit2 1/0 1 bit1 1/0 1 bit0 1/0 1 Default Value Note: *PBIO.n = 1, set as input mode; PBIO.n = 0, set as output mode.; That n =6 ~0. PBMD register Address Name 17H PBMD bit7 # # bit6 1/0 0 bit5 1/0 0 bit4 1/0 0 bit3 1/0 0 bit2 1/0 0 bit1 1/0 0 bit0 1/0 0 Default Value Note: *When PBIO corresponding bit is optioned as output mode (PBIO.n=0), PBMD.n will work as CMOS or NMOS option bit. (PBIO.n=0, PB.n works as output mode) PBMD.n = 0, PB.n is NMOS output. PBMD.n = 1, PB.n is CMOS output. *When PBIO corresponding bit is optioned as input mode (PBIO.n=1), PBMD.n will work as internal pull-up resistor enable bit or disable bit. (PBIO.n=1, PB.n works as input mode) PBMD.n = 0, disable PB.n internal pull-up resistor, PBMD.n = 1, enable PB.n internal pull-up resistor. That n = 6 ~ 0. Feb.2009 15/21 www.eorex.com eorex A/D Converter EU1020 The EU1020 is built-in with 4 channels of 10-bit Analog to Digital Converter. The analog signal input pins are shared from PA3~0. These options are controlled by ADIN(09H) and ADCC(0AH) registers. ADIN register: PA3~PA0 ports could be optioned as A/D converter analog signal input pins. User can select partial or all PA3~PA0 pins as analog input pins by ADIN3~0 for corresponding bit. Address Name 09H ADIN bit7 # # # bit6 # # # bit5 # # # bit4 COMP W 0 bit3 ADIN3 W 0 bit2 ADIN2 W 0 bit1 ADIN1 W 0 bit0 ADIN0 W 0 Read or Write Default Value Note: *ADIN3~0: option of PA3~PA0 as analog signal input pin. *ADINn = 1, set PA3~0 pin as analog signal input pin; ADINn = 0, set PA3~0 as normal input/output pin, where n=3~0. * When PA3~0 is set as analog input pin(s), PA ports control register will be inactive to access. That is, when PA port is set as analog signal input pin, all PA I/O port functions will be blocked out. Note: *COMP = 0, disable internal comparator; COMP = 1, enable internal comparator. When COMP=1, PA4 and PA5 will act as comparator input pin, and then comparator output pin will be connected to PB4 internally. ADCR register Address Name 0AH ADCR bit7 ADEN W 0 bit6 STC R/W # bit5 # # # bit4 ADS1 W # Bit3 ADS0 W # bit2 # # # bit1 # # # bit0 # # # www.eorex.com 16/21 Read or Write Default Value Feb.2009 eorex Note: EU1020 *ADCR.7(ADEN) : enable A/D converter ADCR.7 = 1, turn on or enable A/D converter; ADCR.7 = 0, turn off or disable A/D converter. *ADCR.6(STC) : A/D converter finished interrupt flag, write a high to this bit to start ADC conversion. ADCR.6 = 1, A/D converter translation is in BUSY. ADCR.6 = 0, A/D converter is standby status. ADS1/bit4 0 0 1 1 ADS0/bit3 0 1 0 1 Select pin PA0 PA1 PA2 PA3 Note: * ADCR.4~3(ADS1~0) : select acting analog channel input * User can preset A/D converter sampling rate from ADRL.2~0 control register. The sampling clock comes from internal ring oscillator. The reference sampling rate setting is listed below. A/D configuration and control block Feb.2009 17/21 www.eorex.com eorex Note: EU1020 *User should select PA3~0 ports as analog signal input pin(s) by setting ADIN.3~0. Set ADCC.7 (ADEN) = 1 to enable A/D converter circuit, and then select input pin from ADCC.4~3 (ADS1/ADS0). The converter clock comes from FADC. After system completed an A/D converting cycle, ADC interrupt takes into action (if ADINT=1). User can read the converting data from ADRH and ADRL registers. [ADRH + ADRL] are totally 10 bits in 2 bytes control registers. These 2 bytes of register will keep the last A/D convert data. When A/D conversion are all completed, user should turn off A/D converter by setting ADCC.7 (ADEN) =0. ADSP2~0 control register: A/D Converter sampling rate setting Address Name 0BH ADRL bit7 Ad1 R # bit6 Ad0 R # bit5 # # # bit4 # # # bit3 # # # bit2 ADSP2 W # bit1 ADSP1 W # bit0 ADSP0 W # Read or Write Default Value ADC sampling rate 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz 256 Hz 512 Hz 1024 Hz ADSP2 ADSP1 ADSP0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Address Name 0CH ADRH bit7 Ad9 R # bit6 Ad8 R # bit5 Ad7 R # bit4 Ad6 R # bit3 Ad5 R # bit2 Ad4 R # bit1 Ad3 R # bit0 Ad2 R # Read or Write Default Value Feb.2009 18/21 www.eorex.com eorex EU1020 Low Voltage Reset Circuit ( or Power Failed Detector ) 2.4V The EU1020 is built in Low-Voltage-Reset circuit to detect and against power noise. The low voltage reset will be active when Vdd is dropped lower than 2.4V. Note that, in STOP mode, low voltage reset function will be disabled by hardware. The low voltage reset function will be active when CPU is not working in STOP mode. HALT mode The EU1020 will enter HALT mode by setting an instruction as “STA $0EH”. The data in ACC could be any data among #00H~#FFH. In HALT mode, CPU core will suspend and just hold at that program counter. All the internal circuit will suspend, except system clock and timer/counter kept running. HALT mode could be released from timer underflow or PB ports input signal from high to low. When halt mode is released, program counter will execute next instruction after “STA $0EH”. If timer interrupt is enabled, it serves timer interrupt first, and then execute next instruction after “STA $0EH”. When HALT mode is released by PB ports falling-edge, program counter execute next instruction. If PB interrupt is enabled, PBINT =1, PB interrupt subroutine will be activated. Address Name 0EH HALT bit7 # bit6 # bit5 # bit4 # bit3 # bit2 # bit1 # bit0 # STOP mode When executed “STA $0FH”, whole chip will enter stop mode. The data in ACC could be any data of #00H~#FFH. In stop mode, system clock and timer/counter will be stopped. At this condition, operating current could be down less than 1µA. Only input signal from high to low of PB ports can release the chip from STOP mode. When STOP mode is released by PB ports, program counter will execute next instruction of “STA $0FH”. If PB interrupt is enabled, PBINT=1, PB interrupt subroutine will be activated first. Address Name 0FH STOP bit7 # bit6 # bit5 # bit4 # bit3 # bit2 # bit1 # bit0 # MCU system clock This CPU is built-in internal RC oscillator whose frequency is 4MHz. The tolerance of the frequency is within 3%. Feb.2009 19/21 www.eorex.com eorex Package Description SOP-16L EU1020 C J K H e B E DIMENSIONS REF. Min A B C D E F M H L J K e 1.47 0.375 REF. 45° 1.27 REF. 0.08 0.40 REF. 1.73 5.79 9.80 3.81 0° 0.50 0.25 REF. 0.24 Millimeters Max 6.19 10.00 3.99 5° 0.90 Feb.2009 20/21 www.eorex.com eorex Revision History Revision 0.1 (Jul 2007) - First release EU1020 Revision 0.2 (Aug. 2007).... - Pin Description . Revision 0.3 (Apr. 2008).... - EU101X .-> EU1010 Revision 0.4 (Jul. 2008).... - Modify Memory / Address Revision 0.5 (Feb. 2009).... - Modify -40C~125C Revision 0.6 (Feb. 2009).... - Modify ordering information (xxxx = customer/product code ) Feb.2009 21/21 www.eorex.com