EPC2037

eGaN® FET DATASHEET EPC2037 EPC2037 – Enhancement Mode Power Transistor VDSS , 100 V RDS(on) , 550 m ID , 1.7 A EFFICIENT POWER CONVERSION HAL Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. EPC2037 eGaN® FETs are supplied only in passivated die form with solder bumps. Die size: 0.9 mm x 0.9 mm Maximum Ratings VDS ID VGS TJ TSTG Drain-to-Source Voltage (Continuous) 100 Drain-to-Source Voltage (up to 10,000 5ms pulses at 150˚C) 120 Continuous (TA = 25˚C, R θJA= 44˚C/W) 1.7 Pulsed (25˚C, TPULSE = 300 µs) 2.4 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 Operating Temperature -40 to 150 Storage Temperature -40 to 150 Applications • High Speed DC-DC Conversion • Wireless Power Transfer • LiDAR/Pulsed Power Applications • Class-D Audio Benefits • Ultra High Efficiency • Ultra Low RDS(on) • Ultra Low QG • Ultra Small Footprint V A V ˚C www.epc-co.com/epc/Products/eGaNFETs/EPC2037.aspx Static Characteristics (TJ= 25˚C unless otherwise stated) PARAMETER BVDSS IDSS TEST CONDITIONS MIN Drain-to-Source Voltage VGS = 0 V, ID = 125 µA 100 TYP MAX UNIT V Drain Source Leakage VDS = 80 V, VGS = 0 V 10 100 µA Gate-to-Source Forward Leakage VGS = 5 V 0.1 1 Gate-to-Source Reverse Leakage VGS = -4 V 10 100 mA µA VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.8 mA 1.5 2.5 V RDS(on) VSD Drain-Source On Resistance Source-Drain Forward Voltage VGS = 5 V, ID = 0.1 A IS = 0.3 A, VGS = 0 V 400 2.5 550 mΩ V IGSS 0.8 All measurements were done with substrate shorted to source. Thermal Characteristics TYP UNIT RθJC Thermal Resistance, Junction to Case 14 ˚C/W RθJB Thermal Resistance, Junction to Board 79 ˚C/W RθJA Thermal Resistance, Junction to Ambient (Note 1) 100 ˚C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 1 eGaN® FET DATASHEET EPC2037 Dynamic Characteristics (TJ= 25˚C unless otherwise stated) PARAMETER TEST CONDITIONS CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) RG Gate Resistance QG Total Gate Charge QGS Gate to Source Charge QGD Gate to Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge MIN VDS = 50 V, VGS = 0 V TYP MAX 14 17 UNIT 0.1 6.5 10 pF 9.5 VDS = 0 to 50 V, VGS = 0 V 12 0.5 Ω 115 VDS = 50 V, VGS = 5 V, ID = 0.1 A 145 32 VDS = 50 V, ID = 0.1 A 25 pC 24 VDS = 50 V, VGS = 0 V 600 900 0 Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 50% BVDSS. Figure 1: Typical Output Characteristics at 25°C 1.5 1.0 VDS = 3 V 1.5 1.0 0.5 0.5 0 25˚C 125˚C 2.0 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V ID – Drain Current (A) ID – Drain Current (A) 2.0 Figure 2: Transfer Characteristics 0 0.5 1.0 1.5 2.0 2.5 0 3.0 VDS – Drain-to-Source Voltage (V) 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 4: RDS(on) vs. VGS for Various Temperatures 1600 1600 RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 1.5 VGS – Gate-to-Source Voltage (V) Figure 3: RDS(on) vs. VGS for Various Drain Currents ID = 0.05 A ID = 0.1A ID = 0.2 A ID = 0.4 A 1200 400 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 25˚C 125˚C 1200 800 0 2.5 1.0 4.5 5.0 ID = 0.1 A 800 400 0 2.5 3.0 EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 | 2 eGaN® FET DATASHEET EPC2037 Figure 5a: Capacitance (Linear Scale) Figure 5b: Capacitance (Log Scale) 25 100 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 Capacitance (pF) Capacitance (pF) 20 15 10 0.1 5 0 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1 0 25 50 75 0.01 100 VDS – Drain-to-Source Voltage (V) 0 25 50 75 100 VDS – Drain-to-Source Voltage (V) Figure 7: Reverse Drain-Source Characteristics Figure 6: Gate Charge 2.0 ID = 0.1 A VDS = 50 V 4 ISD – Source-to-Drain Current (A) VGS – Gate-to-Source Voltage (V) 5 3 2 1 0 0 0.02 0.04 0.06 0.08 0.1 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 QG – Gate Charge (nC) VSD – Source-to-Drain Voltage (V) Figure 8: Normalized On-State Resistance vs. Temperature Figure 9: Normalized Threshold Voltage vs. Temperature 1.4 1.3 1.8 Normalized Threshold Voltage Normalized On-State Resistance RDS(on) VGS = 0 V 1.5 0 0.12 2.0 ID = 0.1 A VGS = 5 V 1.6 1.4 1.2 1.0 0.8 25˚C 125˚C ID = 0.08 mA 1.2 1.1 1.0 0.9 0.8 0.7 0 25 50 75 100 125 150 0.6 0 TJ – Junction Temperature (°C) EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | 25 50 75 100 TJ – Junction Temperature (°C) 125 150 | 3 eGaN® FET DATASHEET EPC2037 Figure 10: Safe Operating Area ID – Drain Current (A) 10 1 Limited by RDS(on) Pulse Width 100 ms 10 ms 1 ms 0.1 0.1 1 10 100 VDS – Drain-Source Voltage (V) Figure 11: Transient Thermal Response Curves Junction-to-Case ZθJC, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 PDM t1 0.01 Single Pulse 0.001 10-5 10-4 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC 10-3 10-2 10-1 1 101 tp, Rectangular Pulse Duration, seconds Junction-to-Board ZθJB, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.1 0.1 0.05 0.02 0.01 0.01 PDM t1 0.001 Single Pulse 0.0001 10-5 10-4 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB 10-3 10-2 10-1 1 101 tp, Rectangular Pulse Duration, seconds EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 4 eGaN® FET DATASHEET EPC2037 TAPE AND REEL CONFIGURATION b 4mm pitch, 8mm wide tape on 7” reel e d f g Loaded Tape Feed Direction 7” reel YYY c AC a a b c (see note) d e f (see note) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 max 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Gate solder bump is under this corner Die is placed into pocket solder bump side down (face side down) EPC2037 (note 1) Dimension (mm) target min Die orientation dot Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS Die orientation dot Gate Pad bump is under this corner AC YYY Part Number EPC2037 Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 AC YYY EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 5 eGaN® FET DATASHEET EPC2037 A DIE OUTLINE DIM g Solder Bump View 2 A B c d e f g d B 4 1 Pad 1 is Gate; Pad 3 is Drain; Pads 2, 4 are Source 3 c 930 930 450 450 240 240 229 815 Max (625) SEATING PLANE 900 The land pattern is solder mask defined Solder mask is 10μm smaller per side than bump 200 ±10 (*) X4 (measurements in µm) MAX 900 900 450 450 225 225 208 165+/- 17 Side View RECOMMENDED LAND PATTERN Nominal 870 870 450 450 210 210 187 f e MIN Pad 1 is Gate; 1 3 Pad 3 is Drain; 450 900 Pads 2, 4 are Source 225 4 225 242 2 450 * minimum 190 RECOMMENDED STENCIL DRAWING 900 Recommended stencil should be 4mil (100µm) thick, must be laser cut, openings per drawing. 250 Intended for use with SAC305 Type 4 solder, reference 88.5% metals content. 225 450 Additional assembly resources available at http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx 225 450 900 R6 0 (measurements in µm) Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | Information subject to change without notice. Revised April, 2017 | 6