AM79Q4457J

Am79Q4457/5457 Quad Subscriber Line Audio Processing CircuitNon-Programmable (QSLAC™-NP) Devices DISTINCTIVE CHARACTERISTICS n n n n Performs the function of four Codec/Filters A-law or µ-law coding Single PCM port — Up to 4.096 MHz operation (64 channels) Hardware programmable (via external components) — Transhybrid balance impedance — Transmit and receive gains n Additional Am79Q4457 device capabilities (per channel, set external) — Three selectable transmit gains — Three selectable receive gains — Two selectable balance networks — Simple serial control interface Separate PCM and Master clocks 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz master clock options — Internal timing automatically adjusted based on MCLK and frame sync signal Low power 5.0 V CMOS technology 5.0 V only operation n n n n GENERAL DESCRIPTION The Am79Q4457/5457 Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) device integrates the key functions of analog linecards into a high-performance, four-channel Codec/Filter device. The QSLAC-NP devices are based on the proven design of the reliable Am79C02/03/031(A) Dual Sub scr ibe r Line Aud io-Processing Circu it (DSLAC ™ ) devices, and the Am79C202 Advanced Subscriber Line Audio-Processing Circuit (ASLAC ™) device. The advanced architecture of the QSLAC-NP devices implements four independent channels in a single integrated circuit, providing a cost-effective solution for the audio-processing function of Plain Old Telephone Service (POTS) linecards. The Am79Q4457/5457 QSLAC-NP device provides four industry-standard Codec/Filter devices in a single integrated circuit. The Am79Q4457/5457 device provides a transmit and receive frame synchronization input per channel. A-law or µ-law compression is selected via a device pin. In addition, the Am79Q4457 device provides the ability to select one of three independent gain settings (both transmit and receive) and one of two balance networks on a per-channel basis. The transmit and receive gain leve ls ar e set once fo r th e device via exte r na l components. Gain level selection and the balance network selection is achieved through an integrated serial shift register and latch per channel. The Am79Q5457 device provides four industr ystandard Codec/Filter devices in a 32-pin PLCC or 44pin TQFP package. The Am79Q4457 device provides four industr y-standard Codec/Filter devices and selectable gain and balance functions in a 44-pin PLCC or 44-pin TQFP package. Advanced submicron CMOS technology enables the Am79Q4457/5457 QSLAC-NP device to have both the functionality and the low power consumption required in linecard designs, maximizing linecard density at a minimum cost. When used with four Legerity SLICs, a QSLAC-NP device provides a complete solution to the BORSCHT function of a POTS linecard. Although the name and logo have changed, the data contained herein remains the same as the most recent AMD revision of this document. Publication# 20031 Rev: D Amendment: /0 Issue Date: January 2000 TABLE OF CONTENTS Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams (PLCC packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagrams (44-pin TQFP packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supply for the Am79Q4457/5457 Devices: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Characteristics over operating ranges (unless otherwise noted) . . . . . . . . . . . . . . . . . 12 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Variation of Gain with Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Total Distortion, Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Discrimination against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Discrimination against 12 kHz and 16 kHz Metering Signals . . . . . . . . . . . . . . . . . . . . . . . 19 Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Switching Characteristics over operating ranges (unless otherwise noted). . . . . . . . . . . . . . . . . 20 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input and Output Waveforms for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Control Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Control Interface (Output Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PCM Highway Timing (Short Frame Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCM Highway Timing (Long Frame Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating The QSLAC-NP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Control of the Am79Q4457/5457 QSLAC-NP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Parallel Control (Am79Q5457 Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial Control Register (Am79Q4457 Device Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Setting Gain Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Gain Settings for the Am79Q4457 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Gain Settings for the Am79Q5457 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Calculation of Balance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Considerations For Connection To Slics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Effects of CRX and CTX Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Placement of the Balance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SLIC Connection Consideration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PL032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PL044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PQT044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2 Am79Q4457/5457 Data Sheet List of Figures Figure 1. Figure 2. Figure 3a. Figure 3b. Figure 4a. Figure 4b. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9a. Figure 9b. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 A-law Gain Tracking with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . 16 m-law Gain Tracking with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . 16 A-law Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . 17 m-law Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . 17 Discrimination against Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Spurious Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Am79Q4457 QSLAC-NP Device Serial Control Interface . . . . . . . . . . . . . . . . . 26 QSLAC-NP Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Am79Q4457JC Device (Channel 1 Shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Am79Q5457 Device (Channel 1 Shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Am79Q4457JC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Am79Q5457JC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Balance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Balance Network Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Alternate Balance Network Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 List of Tables Table 1. Table 2. Table 3. 0 dBm0 Voltage Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transmit Gain Select (Am79Q4457 Device Only). . . . . . . . . . . . . . . . . . . . . . . . 28 Receive Gain Select (Am79Q4457 Device Only) . . . . . . . . . . . . . . . . . . . . . . . . 29 SLAC Products 3 BLOCK DIAGRAM Quad SLAC-NP Device Analog I1 IN1 I2IN1 VOUT1 I1IN2 I2IN2 VOUT2 I1IN3 I2IN3 VOUT3 I1 IN4 I2IN4 VOUT4 Signal Processing Channel 1 (CH 1) Signal Processing Channel 2 (CH 2) Single PCM Highway DXA DRA PCM Interface TSCA *2 *2 *2 Signal Processing Channel 3 (CH 3) Signal Processing Channel 4 (CH 4) *2 A/µ Clock & Reference Circuits FSR1–4 FSX1–4 PCLK MCLK IREF1 IREF2*2 IREF3*2 VREF1 VREF2*2 VREF3*2 PDN1–4*1 Control Interface 20031A-001 VCCA Notes: *1 = Am79Q5457 only. *2 = Am79Q4457 only. AGND VCCD DGND CO *2 CS1–4 *2 CI *2 CCLK *2 4 Am79Q4457/5457 Data Sheet ORDERING INFORMATION Standard Products Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79Q4457/5457 J C TEMPERATURE RANGE *C = Commercial (0°C to 70°C; Relative Humidity = 15% to 95%) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) —Am79Q4457 Only 32-Pin Plastic Leaded Chip Carrier (PL 032) —Am79Q5457 Only V = 44-Pin Thin Quad Flat Pack (PQT 044) —Am79Q4457 and Am79Q5457 DEVICE NUMBER/DESCRIPTION Am79Q4457/5457 Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Device Valid Combinations Am79Q4457 Am79Q5457 Am79Q4457 Am79Q5457 JC JC VC VC Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on Legerity’s standard military–grade products. Note: * The performance specifications contained in this data sheet for 0 °C to +70 °C operation are guaranteed by 100% factory testing at 65 °C. Extended temperature range specifications (–40°C to +85°C) are guaranteed by characterization and periodic sampling of production units. SLAC Products 5 CONNECTION DIAGRAMS (PLCC PACKAGES) Top View CS4 MCLK PCLK I1IN1 VOUT1 I2IN1 VREF1 6 5 4 3 2 1 44 43 42 41 40 I1IN2 VOUT2 I2IN2 IREF2 VREF2 CS1 CS2 CS3 VCCA IREF1 AGND IREF3 I2IN3 VOUT3 I1IN3 7 8 9 10 11 Am79Q4457JC 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VREF3 A/µ RSRVD I1IN4 VOUT4 I2IN4 39 38 37 36 35 34 33 32 31 30 29 28 CI CCLK TSCA DGND CO DXA VCCD DRA FSR1 FSX 1 FSR 2 FSX4 FSR4 FSX3 FSR3 FSX2 20031A-002 4 I1IN1 I1IN2 VOUT2 VCCA IREF1 AGND VOUT3 I1IN3 I1IN4 5 6 7 8 9 10 11 12 13 VREF1 3 2 1 32 31 30 29 28 27 26 PCLK TSCA DGND DXA VCCD DRA FSR1 FSX1 FSR2 Am79Q5457JC MCLK 25 24 23 22 21 FSX2 20031A-003 PDN1 PDN2 PDN3 FSX3 14 15 16 17 18 19 20 FSX4 FSR4 FSR3 VOUT4 A/µ Note: Pin 1 is marked for orientation. 6 Am79Q4457/5457 Data Sheet PDN4 VOUT1 CONNECTION DIAGRAMS (44-PIN TQFP PACKAGES) Top View 44 43 42 41 40 39 38 37 36 35 34 I1IN2 VOUT2 I2IN2 IREF2 VCCA IREF1 AGND IREF3 I2IN3 VOUT3 I1IN3 1 2 3 4 5 6 7 8 9 10 11 Am79Q4457VC 33 32 31 30 29 28 27 26 25 24 23 CI CCLK TSCA DGND CO DXA VCCD DRA FSR1 FSX1 FSR2 12 13 14 15 16 17 18 19 20 21 22 VREF3 FSX4 FSR4 FSX3 FSR3 FSX2 MCLK PCLK I1IN4 I2IN4 VOUT4 A/U N/C PDN1 44 43 42 41 40 39 38 37 36 35 34 I1IN2 VOUT2 N/C N/C VCCA IREF1 AGND N/C N/C VOUT3 I1IN3 1 2 3 4 5 6 7 8 9 10 11 Am79Q5457VC 33 32 31 30 29 28 27 26 25 24 23 N/C N/C TSCA DGND N/C DXA VCCD DRA FSR1 FSX1 FSR 2 12 13 14 15 16 17 18 19 20 21 22 VOUT4 N/C N/C A/U I1IN4 N/C FSX4 FSR4 FSX3 FSR3 FSX2 Note: Pin 1 is marked for orientation. SLAC Products PDN2 PDN3 PDN4 VOUT1 N/C VREF1 I1IN1 N/C MCLK PCLK VOUT1 I2IN1 VREF1 VREF2 I1IN1 CS1 CS2 CS3 CS4 7 PIN DESCRIPTIONS Pin Name Type Description A-law or µ-law Select. The A-law/µ-law select pin is used to inform the QSLAC-NP device which compression/expansion standard to use. A logic Low signal (0 V) on the A-law/µ-law pin selects the µ-law standard, and a logic High (+5 V) selects the A-law standard. The A-law/µ-law input can be connected to VCCD directly, eliminating the need for a external pull-up resistor. Therefore, the device can be programmed for A-law by connecting the A/µ input to V CCD and can be programmed for µ-law by connecting the device pin to DGND. (Am79Q4457 Device Only) Control Clock. The Control Clock input shifts data into and out of the Serial Interface of the QSLAC-NP device. The maximum clock rate is 4.096 MHz. (Serial control on the Am79Q4457 device only.) (Am79Q4457 Device Only) Control Data. Control Data is written into the selected Channel Control Register (see CSN) via the CI pin. The data is shifted in the Most Significant Bit (MSB) first. The data rate is determined by CCLK. (Serial control on the Am79Q4457 device only.) (Am79Q4457 Device Only) Control Data. Control Data is read in serial form from the Enabled Channel Register (see CSN) via the CO pin. Data is shifted out with the MSB first. The data rate is determined by the Control Clock (CCLK). (Serial control available on the Am79Q4457 device only.) (Am79Q4457 Device Only) Chip Select. The Chip Select (CSN) input (active Low) enables Channel N of the device so that control data can be written to or read from the channel. CS1 enables Channel 1, CS2 enables Channel 2, CS3 enables Channel 3, and CS4 enables Channel 4. (Serial control on the Am79Q4457 device only.) PCM. The PCM data for Channels 1, 2, 3, and 4 is serially received on the DRA port during the time slot determined by the Receive Frame Sync Signal (FSRN). Data is always received with the MSB first. A byte of data for each channel is received every 125 µs at the PCLK rate. PCM. The transmit data from Channels 1, 2, 3, and 4 is sent serially out the DXA port during time slots determined by the Transmit Frame Sync (FSXN ) signal for that channel. Data is always transmitted with the MSB first. The output is available every 125 µs and the data is shifted out in 8-bit bursts at the PCLK rate. DXA is high impedance between time slots. Receive Frame Sync. The Receive Frame Sync pulse for Channel N is an 8 kHz signal that identifies the receive time slot for Channel N on a system ’s receive PCM frame. The QSLACNP device references channel time slots with respect to this input, which must be synchronized to PCLK. There are both Long-Frame Sync and Short-Frame Sync modes available on the QSLAC-NP device. Transmit Frame Sync. The Transmit Frame Sync pulse for Channel N is an 8 kHz signal that identifies the transmit time slot for Channel N during the system ’s transmit PCM frame. The QSLAC-NP device references individual channel time slots with respect to this input, which must be synchronized to PCLK. There are both Long Frame Sync and Short Frame Sync modes available on the QSLAC-NP device. (I2IN on Am79Q4457 Device Only) Analog Inputs. The analog voice band voltage signal is applied to the IIN input of the QSLAC-NP device through a resistor. The IIN input is a virtual AC ground input (summing node). IIN is biased at the voltage on the VREF1 pin. The audio signal is sampled, digitally processed and encoded, and then made available at the TTL-compatible PCM output (DXA). There are two inputs per channel in the 44-pin QSLAC-NP device. I1IN1 is input 1 of Channel 1 and I2IN1 is input 2 of Channel 1; I1IN2 and I2IN2 are inputs 1 and 2 of Channel 2; I1IN3 and I2IN3 are inputs 1 and 2 of Channel 3; and I1IN4 and I2IN4 are inputs 1 and 2 of Channel 4. See Figure 9 for more details. (IREF2 and IREF3 on Am79Q4457 Device Only). Reference Current. The IREF outputs are biased at the internal reference voltage, which is the same as the voltage on the VREF1 pin. A resistor placed from IREFn (n = 1, 2, or 3) to ground sets one of three reference currents used by the Analog-to-Digital (Ato-D) converter to encode the signal current present on IyINn (n = channel number [1 to 4] and y = input number [1 or 2]) into digital form. By setting different levels for I REFx, three different transmit gains can be achieved. The reference current used by a channel A-to-D is determined by the Transmit Gain Select (TGS) bits in the channel control register. The absolute transmit gain is determined by the reference current selected and the input resistance connected to IIN. See Figure 9 and Table 2 for more details. A/µ Input CCLK Input CI Input CO Output CS1, CS2, CS3, CS4 Input DRA Input DXA Output FSR1, FSR2, FSR3, FSR4 Input FSX1, FSX2, FSX3, FSX4 Input I1IN1, I2IN1, I1IN2, I2IN2, I1IN3, I2IN3, I1IN4, I2IN4 Current IREF1, IREF2, IREF3 Output 8 Am79Q4457/5457 Data Sheet Pin Name Type Description Master Clock. The Master Clock frequency can be 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz for use by the digital signal processor. Using the Transmit Frame Sync (FSX) Inputs, the QSLAC-NP device determines the MCLK frequency and makes the necessary internal adjustments automatically. The master clock frequency must be an exact integer multiple of the frame sync frequency. PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum clock frequency is 4.096 MHz, and the minimum clock frequency is 256 kHz, due to a single PCM highway. PCLK frequencies between 1.03 MHz and 1.53 MHz are not allowed. The digital signal processor clock can be derived from PCLK by connecting MCLK and PCLK together. See frequency restrictions under MCLK. (Am79Q5457 Device Only) Power Down. The power-down inputs provide direct control over the channel circuitry. A logic High on PDN n (n = 1 to 4) powers Channel n down while a logic Low powers the channel up. PDN1 controls Channel 1, PDN2 controls Channel 2, PDN3 controls Channel 3, and PDN4 controls Channel 4. The PDN pins are used in the initialization of the internal circuitry. Refer to the Power-Up Sequence section on 24 for initialization using the PDN pins. Time Slot Control. The Time Slot Control output is an open drain output (requiring a pull-up resistor to VCCD) and is normally inactive (high impedance). TSCA is active (Low) when PCM data is transmitted on the DXA pin for any of the four channels. Analog Outputs. The received digital data at DRA is processed and converted to an analog signal at the VOUT pin. VOUT1 is the output from Channel 1; VOUT2 is the output for Channel 2; VOUT3 is the output from Channel 3; and VOUT4 is the output for Channel 4. The VOUT voltages are referenced to V REF1. Voltage Reference. The V REF1 output is provided in order for an external 0.1-µF capacitor (or larger) to be connected from VREF1 to ground, filtering noise present on the internal voltage reference. VREF1 is buffered before it is used by internal circuitry. The voltage on V REF1 is nominally 2.1 V, and the output resistance is 115 kW. The leakage current in the capacitor must be less than 20 nA. A larger filter capacitor will provide better filtering, but will increase the settling time. (Am79Q4457 Device Only). Voltage Reference. VREF2 and VREF3 are buffered and are available as alternative reference voltages for the channel Digital-to-Analog (D-to-A) converters. The D-to-A converters decode the received PCM data into analog voltage levels. VREF1, VREF2, or VREF3 can be selected by the Receive Gain Select (RGS) bits as the reference for the D-to-A converter in order to select the receive gain of the channel. MCLK Input PCLK Input PDN1, PDN2, PDN3, PDN4 Input TSCA Output VOUT1, VOUT2, VOUT3, VOUT4 Voltage VREF1 Output VREF2, VREF3 Input Power Supply for the Am79Q4457/5457 Devices: AGND DGND VCCA VCCD Analog Ground Digital Ground +5.0 V Analog Power Supply +5.0 V Digital Power Supply Two separate power supply inputs are provided to allow for noise isolation and good power supply decoupling techniques; however, the two pins have a low impedance connection inside the part. For best performance, all of the +5.0 power supply pins should be connected together at the connector of the printed circuit board, and all of the grounds should be connected together at the connector of the printed circuit board. SLAC Products 9 FUNCTIONAL DESCRIPTION The QSLAC-NP device performs the Codec/Filter and two-to-four-wire conversion function (requires external balance impedance) required of the subscriber line interface circuitry in telecommunications equipment. These functions involve converting an audio signal into digital PCM samples and converting digital PCM samples back into an audio signal. During conversion, digital filters are used to band limit the voice signals. All of the digital filtering is performed in digital signal processors operating from an internal clock, which is derived from MCLK. The fixed filters set the transmit and receive gain and frequency response. The transmit and receive gain can be altered on a perchannel basis and the per-channel balance impedance can be selected between two external impedances by the Am79Q4457 QSLAC-NP device. Control of these functions is provided by an integrated serial shift register and latch per channel. These additional functions are available on the Am79Q4457 device only. Data transmitted or received on the PCM highway is an 8-bit, A-law or µ-law companded code. The QSLAC-NP device is compatible with both codes. Code selection is provided via a device pin (A/µ). The 8-bit codes appear 1 byte per time slot. The PCM data is read and written to the PCM highway in time slots determined by the individual Frame Sync signals (FSRN and FSXN) at rates from 256 kHz to 4.096 MHz. Both Long- and ShortFrame Sync modes are available in the QSLAC-NP device. Two configurations of the QSLAC-NP device are offered as pictured previously. The Am79Q4457 dev ic e w i t h s e r i a l c o n t r o l o f g a i n a n d b a la n c e impedance is available in the 44-pin PLCC package and 44-pin TQFP package. The Am79Q5457 device without serial control is available in a 32-pin PLCC package and 44-pin TQFP package. Serial Control Yes No Yes No Package 44 PLCC 32 PLCC 44 TQFP 44 TQFP Part Number Am79Q4457 Am79Q5457 JC JC Am79Q4457 VC Am79Q5457 VC 10 Am79Q4457/5457 Data Sheet ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . –60°C < TA < +125°C Ambient Operating Temp . . . . . . . –40°C < TA < +85°C Ambient Relative Humidity . . . . . . . . . . . . 5% to 95% (non condensing) VCCA with respect to VCCD . . . . . . . . . . . . . . . . ±50 mV VCCA with respect to AGND. . . . . . . . . –0.4 V to +7.0 V VCCD with respect to DGND . . . . . . . . –0.4 V to +7.0 V AGND with respect to DGND . . . . . . . . . . . . . . ±0.4 V IIN Current . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Other pins with respect to DGND . . . . . . –0.4 V to VCCD +0.4 V Latch-up immunity (any pin). . . . . . . . . . . . . . ±30 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES VCCA, Analog Supply . . . . . . . . . . . . . . . . VCCD ±10 mV VCCA, Analog Supply . . . . . . . . . . . . . +5.0 V ± 0.25 V VCCD, Digital Supply . . . . . . . . . . . . . +5.0 V ± 0.25 V DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mV Ambient Temperature . . . . . . . . . . . .0°C < TA < +70°C Ambient Relative Humidity . . . . . . . . . . . .15% to 95% Operating Ranges define those limits between which functionality of the device is guaranteed by 100% production testing. Specifications in this data sheet are guaranteed by testing from 0° C to +70° C. Performance from –40 °C to +85 °C is guaranteed by characterization and periodic sampling of production units. SLAC Products 11 ELECTRICAL CHARACTERISTICS over operating ranges (unless otherwise noted) Typical values are for TA = 25°C and nominal supply voltages. Minimum and maximum specifications are over the temperature and supply voltage ranges shown in Operating Ranges. Symbol VIL VIH IIL VOL Parameter Descriptions Input Low voltage Input High voltage Input leakage current Output Low voltage TSCA (IOL = 14 mA) All other digital outputs (IOL = 2 mA) Output High voltage All digital outputs (IOH = 400 µA) Output leakage current (H I = Z State) Analog input current range, RREF = 13 kΩ Offset current allowed on IIN Offset voltage on IIN relative to VREF1 VOUT output impedance VREF1 output impedance (F < 3400 Hz) VOUT output current (F